1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ov4689 driver 4 * 5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. 6 * Copyright (C) 2022, 2024 Mikhail Rudenko 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <media/media-entity.h> 17 #include <media/v4l2-async.h> 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-subdev.h> 21 #include <media/v4l2-fwnode.h> 22 23 #define OV4689_REG_CTRL_MODE CCI_REG8(0x0100) 24 #define OV4689_MODE_SW_STANDBY 0x0 25 #define OV4689_MODE_STREAMING BIT(0) 26 27 #define OV4689_REG_CHIP_ID CCI_REG16(0x300a) 28 #define CHIP_ID 0x004688 29 30 #define OV4689_REG_EXPOSURE CCI_REG24(0x3500) 31 #define OV4689_EXPOSURE_MIN 4 32 #define OV4689_EXPOSURE_STEP 1 33 #define OV4689_VTS_MAX 0x7fff 34 35 #define OV4689_REG_GAIN CCI_REG16(0x3508) 36 #define OV4689_GAIN_STEP 1 37 #define OV4689_GAIN_DEFAULT 0x80 38 39 #define OV4689_REG_VTS CCI_REG16(0x380e) 40 41 #define OV4689_REG_TEST_PATTERN CCI_REG8(0x5040) 42 #define OV4689_TEST_PATTERN_ENABLE 0x80 43 #define OV4689_TEST_PATTERN_DISABLE 0x0 44 45 #define OV4689_LANES 4 46 #define OV4689_XVCLK_FREQ 24000000 47 48 static const char *const ov4689_supply_names[] = { 49 "avdd", /* Analog power */ 50 "dovdd", /* Digital I/O power */ 51 "dvdd", /* Digital core power */ 52 }; 53 54 enum ov4689_mode_id { 55 OV4689_MODE_2688_1520 = 0, 56 OV4689_NUM_MODES, 57 }; 58 59 struct ov4689_mode { 60 enum ov4689_mode_id id; 61 u32 width; 62 u32 height; 63 u32 max_fps; 64 u32 hts_def; 65 u32 vts_def; 66 u32 exp_def; 67 u32 pixel_rate; 68 u32 sensor_width; 69 u32 sensor_height; 70 u32 crop_top; 71 u32 crop_left; 72 const struct cci_reg_sequence *reg_list; 73 unsigned int num_regs; 74 }; 75 76 struct ov4689 { 77 struct device *dev; 78 struct regmap *regmap; 79 struct clk *xvclk; 80 struct gpio_desc *reset_gpio; 81 struct gpio_desc *pwdn_gpio; 82 struct regulator_bulk_data supplies[ARRAY_SIZE(ov4689_supply_names)]; 83 84 struct v4l2_subdev subdev; 85 struct media_pad pad; 86 87 u32 clock_rate; 88 89 struct v4l2_ctrl_handler ctrl_handler; 90 struct v4l2_ctrl *exposure; 91 92 const struct ov4689_mode *cur_mode; 93 }; 94 95 #define to_ov4689(sd) container_of(sd, struct ov4689, subdev) 96 97 struct ov4689_gain_range { 98 u32 logical_min; 99 u32 logical_max; 100 u32 offset; 101 u32 divider; 102 u32 physical_min; 103 u32 physical_max; 104 }; 105 106 /* 107 * Xclk 24Mhz 108 * max_framerate 30fps 109 * mipi_datarate per lane 1008Mbps 110 */ 111 static const struct cci_reg_sequence ov4689_2688x1520_regs[] = { 112 /* System control*/ 113 { CCI_REG8(0x0103), 0x01 }, /* SC_CTRL0103 software_reset = 1 */ 114 { CCI_REG8(0x3000), 0x20 }, /* SC_CMMN_PAD_OEN0 FSIN_output_enable = 1 */ 115 { CCI_REG8(0x3021), 0x03 }, /* 116 * SC_CMMN_MISC_CTRL fst_stby_ctr = 0, 117 * sleep_no_latch_enable = 0 118 */ 119 120 /* AEC PK */ 121 { CCI_REG8(0x3503), 0x04 }, /* AEC_MANUAL gain_input_as_sensor_gain_format = 1 */ 122 { CCI_REG8(0x352a), 0x08 }, /* DIG_GAIN_FRAC_LONG dig_gain_long[14:8] = 0x08 (2x) */ 123 124 /* ADC and analog control*/ 125 { CCI_REG8(0x3603), 0x40 }, 126 { CCI_REG8(0x3604), 0x02 }, 127 { CCI_REG8(0x3609), 0x12 }, 128 { CCI_REG8(0x360c), 0x08 }, 129 { CCI_REG8(0x360f), 0xe5 }, 130 { CCI_REG8(0x3608), 0x8f }, 131 { CCI_REG8(0x3611), 0x00 }, 132 { CCI_REG8(0x3613), 0xf7 }, 133 { CCI_REG8(0x3616), 0x58 }, 134 { CCI_REG8(0x3619), 0x99 }, 135 { CCI_REG8(0x361b), 0x60 }, 136 { CCI_REG8(0x361e), 0x79 }, 137 { CCI_REG8(0x3634), 0x10 }, 138 { CCI_REG8(0x3635), 0x10 }, 139 { CCI_REG8(0x3636), 0x15 }, 140 { CCI_REG8(0x3646), 0x86 }, 141 { CCI_REG8(0x364a), 0x0b }, 142 143 /* Sensor control */ 144 { CCI_REG8(0x3700), 0x17 }, 145 { CCI_REG8(0x3701), 0x22 }, 146 { CCI_REG8(0x3703), 0x10 }, 147 { CCI_REG8(0x370a), 0x37 }, 148 { CCI_REG8(0x3706), 0x63 }, 149 { CCI_REG8(0x3709), 0x3c }, 150 { CCI_REG8(0x370c), 0x30 }, 151 { CCI_REG8(0x3710), 0x24 }, 152 { CCI_REG8(0x3720), 0x28 }, 153 { CCI_REG8(0x3729), 0x7b }, 154 { CCI_REG8(0x372b), 0xbd }, 155 { CCI_REG8(0x372c), 0xbc }, 156 { CCI_REG8(0x372e), 0x52 }, 157 { CCI_REG8(0x373c), 0x0e }, 158 { CCI_REG8(0x373e), 0x33 }, 159 { CCI_REG8(0x3743), 0x10 }, 160 { CCI_REG8(0x3744), 0x88 }, 161 { CCI_REG8(0x3745), 0xc0 }, 162 { CCI_REG8(0x374c), 0x00 }, 163 { CCI_REG8(0x374e), 0x23 }, 164 { CCI_REG8(0x3751), 0x7b }, 165 { CCI_REG8(0x3753), 0xbd }, 166 { CCI_REG8(0x3754), 0xbc }, 167 { CCI_REG8(0x3756), 0x52 }, 168 { CCI_REG8(0x376b), 0x20 }, 169 { CCI_REG8(0x3774), 0x51 }, 170 { CCI_REG8(0x3776), 0xbd }, 171 { CCI_REG8(0x3777), 0xbd }, 172 { CCI_REG8(0x3781), 0x18 }, 173 { CCI_REG8(0x3783), 0x25 }, 174 { CCI_REG8(0x3798), 0x1b }, 175 176 /* Timing control */ 177 { CCI_REG8(0x3801), 0x08 }, /* H_CROP_START_L h_crop_start[7:0] = 0x08 */ 178 { CCI_REG8(0x3805), 0x97 }, /* H_CROP_END_L h_crop_end[7:0] = 0x97 */ 179 { CCI_REG8(0x380c), 0x0a }, /* TIMING_HTS_H hts[14:8] = 0x0a */ 180 { CCI_REG8(0x380d), 0x0e }, /* TIMING_HTS_L hts[7:0] = 0x0e */ 181 { CCI_REG8(0x3811), 0x08 }, /* H_WIN_OFF_L h_win_off[7:0] = 0x08*/ 182 { CCI_REG8(0x3813), 0x04 }, /* V_WIN_OFF_L v_win_off[7:0] = 0x04 */ 183 { CCI_REG8(0x3819), 0x01 }, /* VSYNC_END_L vsync_end_point[7:0] = 0x01 */ 184 { CCI_REG8(0x3821), 0x06 }, /* TIMING_FORMAT2 array_h_mirror = 1, digital_h_mirror = 1 */ 185 186 /* OTP control */ 187 { CCI_REG8(0x3d85), 0x36 }, /* OTP_REG85 OTP_power_up_load_setting_enable = 1, 188 * OTP_power_up_load_data_enable = 1, 189 * OTP_bist_select = 1 (compare with zero) 190 */ 191 { CCI_REG8(0x3d8c), 0x71 }, /* OTP_SETTING_STT_ADDRESS_H */ 192 { CCI_REG8(0x3d8d), 0xcb }, /* OTP_SETTING_STT_ADDRESS_L */ 193 194 /* BLC registers*/ 195 { CCI_REG8(0x4001), 0x40 }, /* DEBUG_MODE */ 196 { CCI_REG8(0x401b), 0x00 }, /* DEBUG_MODE */ 197 { CCI_REG8(0x401d), 0x00 }, /* DEBUG_MODE */ 198 { CCI_REG8(0x401f), 0x00 }, /* DEBUG_MODE */ 199 { CCI_REG8(0x4020), 0x00 }, /* ANCHOR_LEFT_START_H anchor_left_start[11:8] = 0 */ 200 { CCI_REG8(0x4021), 0x10 }, /* ANCHOR_LEFT_START_L anchor_left_start[7:0] = 0x10 */ 201 { CCI_REG8(0x4022), 0x07 }, /* ANCHOR_LEFT_END_H anchor_left_end[11:8] = 0x07 */ 202 { CCI_REG8(0x4023), 0xcf }, /* ANCHOR_LEFT_END_L anchor_left_end[7:0] = 0xcf */ 203 { CCI_REG8(0x4024), 0x09 }, /* ANCHOR_RIGHT_START_H anchor_right_start[11:8] = 0x09 */ 204 { CCI_REG8(0x4025), 0x60 }, /* ANCHOR_RIGHT_START_L anchor_right_start[7:0] = 0x60 */ 205 { CCI_REG8(0x4026), 0x09 }, /* ANCHOR_RIGHT_END_H anchor_right_end[11:8] = 0x09 */ 206 { CCI_REG8(0x4027), 0x6f }, /* ANCHOR_RIGHT_END_L anchor_right_end[7:0] = 0x6f */ 207 208 /* ADC sync control */ 209 { CCI_REG8(0x4500), 0x6c }, /* ADC_SYNC_CTRL */ 210 { CCI_REG8(0x4503), 0x01 }, /* ADC_SYNC_CTRL */ 211 212 /* VFIFO */ 213 { CCI_REG8(0x4601), 0xa7 }, /* VFIFO_CTRL_01 r_vfifo_read_start[7:0] = 0xa7 */ 214 215 /* Temperature monitor */ 216 { CCI_REG8(0x4d00), 0x04 }, /* TPM_CTRL_00 tmp_slope[15:8] = 0x04 */ 217 { CCI_REG8(0x4d01), 0x42 }, /* TPM_CTRL_01 tmp_slope[7:0] = 0x42 */ 218 { CCI_REG8(0x4d02), 0xd1 }, /* TPM_CTRL_02 tpm_offset[31:24] = 0xd1 */ 219 { CCI_REG8(0x4d03), 0x93 }, /* TPM_CTRL_03 tpm_offset[23:16] = 0x93 */ 220 { CCI_REG8(0x4d04), 0xf5 }, /* TPM_CTRL_04 tpm_offset[15:8] = 0xf5 */ 221 { CCI_REG8(0x4d05), 0xc1 }, /* TPM_CTRL_05 tpm_offset[7:0] = 0xc1 */ 222 223 /* pre-ISP control */ 224 { CCI_REG8(0x5050), 0x0c }, /* DEBUG_MODE */ 225 226 /* OTP-DPC control */ 227 { CCI_REG8(0x5501), 0x10 }, /* OTP_DPC_START_L otp_start_address[7:0] = 0x10 */ 228 { CCI_REG8(0x5503), 0x0f }, /* OTP_DPC_END_L otp_end_address[7:0] = 0x0f */ 229 }; 230 231 static const struct ov4689_mode supported_modes[] = { 232 { 233 .id = OV4689_MODE_2688_1520, 234 .width = 2688, 235 .height = 1520, 236 .sensor_width = 2720, 237 .sensor_height = 1536, 238 .crop_top = 8, 239 .crop_left = 16, 240 .max_fps = 30, 241 .exp_def = 1536, 242 .hts_def = 4 * 2574, 243 .vts_def = 1554, 244 .pixel_rate = 480000000, 245 .reg_list = ov4689_2688x1520_regs, 246 .num_regs = ARRAY_SIZE(ov4689_2688x1520_regs), 247 }, 248 }; 249 250 static const u64 link_freq_menu_items[] = { 504000000 }; 251 252 static const char *const ov4689_test_pattern_menu[] = { 253 "Disabled", 254 "Vertical Color Bar Type 1", 255 "Vertical Color Bar Type 2", 256 "Vertical Color Bar Type 3", 257 "Vertical Color Bar Type 4" 258 }; 259 260 /* 261 * These coefficients are based on those used in Rockchip's camera 262 * engine, with minor tweaks for continuity. 263 */ 264 static const struct ov4689_gain_range ov4689_gain_ranges[] = { 265 { 266 .logical_min = 0, 267 .logical_max = 255, 268 .offset = 0, 269 .divider = 1, 270 .physical_min = 0, 271 .physical_max = 255, 272 }, 273 { 274 .logical_min = 256, 275 .logical_max = 511, 276 .offset = 252, 277 .divider = 2, 278 .physical_min = 376, 279 .physical_max = 504, 280 }, 281 { 282 .logical_min = 512, 283 .logical_max = 1023, 284 .offset = 758, 285 .divider = 4, 286 .physical_min = 884, 287 .physical_max = 1012, 288 }, 289 { 290 .logical_min = 1024, 291 .logical_max = 2047, 292 .offset = 1788, 293 .divider = 8, 294 .physical_min = 1912, 295 .physical_max = 2047, 296 }, 297 }; 298 299 static void ov4689_fill_fmt(const struct ov4689_mode *mode, 300 struct v4l2_mbus_framefmt *fmt) 301 { 302 fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; 303 fmt->width = mode->width; 304 fmt->height = mode->height; 305 fmt->field = V4L2_FIELD_NONE; 306 } 307 308 static int ov4689_set_fmt(struct v4l2_subdev *sd, 309 struct v4l2_subdev_state *sd_state, 310 struct v4l2_subdev_format *fmt) 311 { 312 struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; 313 struct ov4689 *ov4689 = to_ov4689(sd); 314 315 /* only one mode supported for now */ 316 ov4689_fill_fmt(ov4689->cur_mode, mbus_fmt); 317 318 return 0; 319 } 320 321 static int ov4689_enum_mbus_code(struct v4l2_subdev *sd, 322 struct v4l2_subdev_state *sd_state, 323 struct v4l2_subdev_mbus_code_enum *code) 324 { 325 if (code->index != 0) 326 return -EINVAL; 327 code->code = MEDIA_BUS_FMT_SBGGR10_1X10; 328 329 return 0; 330 } 331 332 static int ov4689_enum_frame_sizes(struct v4l2_subdev *sd, 333 struct v4l2_subdev_state *sd_state, 334 struct v4l2_subdev_frame_size_enum *fse) 335 { 336 if (fse->index >= ARRAY_SIZE(supported_modes)) 337 return -EINVAL; 338 339 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10) 340 return -EINVAL; 341 342 fse->min_width = supported_modes[fse->index].width; 343 fse->max_width = supported_modes[fse->index].width; 344 fse->max_height = supported_modes[fse->index].height; 345 fse->min_height = supported_modes[fse->index].height; 346 347 return 0; 348 } 349 350 static int ov4689_enable_test_pattern(struct ov4689 *ov4689, u32 pattern) 351 { 352 u32 val; 353 354 if (pattern) 355 val = (pattern - 1) | OV4689_TEST_PATTERN_ENABLE; 356 else 357 val = OV4689_TEST_PATTERN_DISABLE; 358 359 return cci_write(ov4689->regmap, OV4689_REG_TEST_PATTERN, 360 val, NULL); 361 } 362 363 static int ov4689_get_selection(struct v4l2_subdev *sd, 364 struct v4l2_subdev_state *state, 365 struct v4l2_subdev_selection *sel) 366 { 367 const struct ov4689_mode *mode = to_ov4689(sd)->cur_mode; 368 369 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 370 return -EINVAL; 371 372 switch (sel->target) { 373 case V4L2_SEL_TGT_CROP_BOUNDS: 374 sel->r.top = 0; 375 sel->r.left = 0; 376 sel->r.width = mode->sensor_width; 377 sel->r.height = mode->sensor_height; 378 return 0; 379 case V4L2_SEL_TGT_CROP: 380 case V4L2_SEL_TGT_CROP_DEFAULT: 381 sel->r.top = mode->crop_top; 382 sel->r.left = mode->crop_left; 383 sel->r.width = mode->width; 384 sel->r.height = mode->height; 385 return 0; 386 } 387 388 return -EINVAL; 389 } 390 391 static int ov4689_s_stream(struct v4l2_subdev *sd, int on) 392 { 393 struct ov4689 *ov4689 = to_ov4689(sd); 394 struct v4l2_subdev_state *sd_state; 395 struct device *dev = ov4689->dev; 396 int ret = 0; 397 398 sd_state = v4l2_subdev_lock_and_get_active_state(&ov4689->subdev); 399 400 if (on) { 401 ret = pm_runtime_resume_and_get(dev); 402 if (ret < 0) 403 goto unlock_and_return; 404 405 ret = cci_multi_reg_write(ov4689->regmap, 406 ov4689->cur_mode->reg_list, 407 ov4689->cur_mode->num_regs, 408 NULL); 409 if (ret) { 410 pm_runtime_put(dev); 411 goto unlock_and_return; 412 } 413 414 ret = __v4l2_ctrl_handler_setup(&ov4689->ctrl_handler); 415 if (ret) { 416 pm_runtime_put(dev); 417 goto unlock_and_return; 418 } 419 420 ret = cci_write(ov4689->regmap, OV4689_REG_CTRL_MODE, 421 OV4689_MODE_STREAMING, NULL); 422 if (ret) { 423 pm_runtime_put(dev); 424 goto unlock_and_return; 425 } 426 } else { 427 cci_write(ov4689->regmap, OV4689_REG_CTRL_MODE, 428 OV4689_MODE_SW_STANDBY, NULL); 429 pm_runtime_put(dev); 430 } 431 432 unlock_and_return: 433 v4l2_subdev_unlock_state(sd_state); 434 435 return ret; 436 } 437 438 /* Calculate the delay in us by clock rate and clock cycles */ 439 static inline u32 ov4689_cal_delay(struct ov4689 *ov4689, u32 cycles) 440 { 441 return DIV_ROUND_UP(cycles * 1000, 442 DIV_ROUND_UP(ov4689->clock_rate, 1000)); 443 } 444 445 static int __maybe_unused ov4689_power_on(struct device *dev) 446 { 447 struct v4l2_subdev *sd = dev_get_drvdata(dev); 448 struct ov4689 *ov4689 = to_ov4689(sd); 449 u32 delay_us; 450 int ret; 451 452 ret = clk_prepare_enable(ov4689->xvclk); 453 if (ret < 0) { 454 dev_err(dev, "Failed to enable xvclk\n"); 455 return ret; 456 } 457 458 gpiod_set_value_cansleep(ov4689->reset_gpio, 1); 459 460 ret = regulator_bulk_enable(ARRAY_SIZE(ov4689_supply_names), 461 ov4689->supplies); 462 if (ret < 0) { 463 dev_err(dev, "Failed to enable regulators\n"); 464 goto disable_clk; 465 } 466 467 gpiod_set_value_cansleep(ov4689->reset_gpio, 0); 468 usleep_range(500, 1000); 469 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 0); 470 471 /* 8192 cycles prior to first SCCB transaction */ 472 delay_us = ov4689_cal_delay(ov4689, 8192); 473 usleep_range(delay_us, delay_us * 2); 474 475 return 0; 476 477 disable_clk: 478 clk_disable_unprepare(ov4689->xvclk); 479 480 return ret; 481 } 482 483 static int __maybe_unused ov4689_power_off(struct device *dev) 484 { 485 struct v4l2_subdev *sd = dev_get_drvdata(dev); 486 struct ov4689 *ov4689 = to_ov4689(sd); 487 488 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 1); 489 clk_disable_unprepare(ov4689->xvclk); 490 gpiod_set_value_cansleep(ov4689->reset_gpio, 1); 491 regulator_bulk_disable(ARRAY_SIZE(ov4689_supply_names), 492 ov4689->supplies); 493 return 0; 494 } 495 496 static int ov4689_init_state(struct v4l2_subdev *sd, 497 struct v4l2_subdev_state *sd_state) 498 { 499 struct v4l2_mbus_framefmt *fmt = 500 v4l2_subdev_state_get_format(sd_state, 0); 501 502 ov4689_fill_fmt(&supported_modes[OV4689_MODE_2688_1520], fmt); 503 504 return 0; 505 } 506 507 static const struct dev_pm_ops ov4689_pm_ops = { 508 SET_RUNTIME_PM_OPS(ov4689_power_off, ov4689_power_on, NULL) 509 }; 510 511 static const struct v4l2_subdev_video_ops ov4689_video_ops = { 512 .s_stream = ov4689_s_stream, 513 }; 514 515 static const struct v4l2_subdev_pad_ops ov4689_pad_ops = { 516 .enum_mbus_code = ov4689_enum_mbus_code, 517 .enum_frame_size = ov4689_enum_frame_sizes, 518 .get_fmt = v4l2_subdev_get_fmt, 519 .set_fmt = ov4689_set_fmt, 520 .get_selection = ov4689_get_selection, 521 }; 522 523 static const struct v4l2_subdev_internal_ops ov4689_internal_ops = { 524 .init_state = ov4689_init_state, 525 }; 526 527 static const struct v4l2_subdev_ops ov4689_subdev_ops = { 528 .video = &ov4689_video_ops, 529 .pad = &ov4689_pad_ops, 530 }; 531 532 /* 533 * Map userspace (logical) gain to sensor (physical) gain using 534 * ov4689_gain_ranges table. 535 */ 536 static int ov4689_map_gain(struct ov4689 *ov4689, int logical_gain, int *result) 537 { 538 const struct ov4689_gain_range *range; 539 unsigned int n; 540 541 for (n = 0; n < ARRAY_SIZE(ov4689_gain_ranges); n++) { 542 if (logical_gain >= ov4689_gain_ranges[n].logical_min && 543 logical_gain <= ov4689_gain_ranges[n].logical_max) 544 break; 545 } 546 547 if (n == ARRAY_SIZE(ov4689_gain_ranges)) { 548 dev_warn_ratelimited(ov4689->dev, 549 "no mapping found for gain %d\n", 550 logical_gain); 551 return -EINVAL; 552 } 553 554 range = &ov4689_gain_ranges[n]; 555 556 *result = clamp(range->offset + (logical_gain) / range->divider, 557 range->physical_min, range->physical_max); 558 return 0; 559 } 560 561 static int ov4689_set_ctrl(struct v4l2_ctrl *ctrl) 562 { 563 struct ov4689 *ov4689 = 564 container_of(ctrl->handler, struct ov4689, ctrl_handler); 565 struct regmap *regmap = ov4689->regmap; 566 struct device *dev = ov4689->dev; 567 int sensor_gain = 0; 568 s64 max_expo; 569 int ret = 0; 570 571 /* Propagate change of current control to all related controls */ 572 switch (ctrl->id) { 573 case V4L2_CID_VBLANK: 574 /* Update max exposure while meeting expected vblanking */ 575 max_expo = ov4689->cur_mode->height + ctrl->val - 4; 576 __v4l2_ctrl_modify_range(ov4689->exposure, 577 ov4689->exposure->minimum, max_expo, 578 ov4689->exposure->step, 579 ov4689->exposure->default_value); 580 break; 581 } 582 583 if (!pm_runtime_get_if_in_use(dev)) 584 return 0; 585 586 switch (ctrl->id) { 587 case V4L2_CID_EXPOSURE: 588 /* 4 least significant bits of exposure are fractional part */ 589 cci_write(regmap, OV4689_REG_EXPOSURE, ctrl->val << 4, &ret); 590 break; 591 case V4L2_CID_ANALOGUE_GAIN: 592 ret = ov4689_map_gain(ov4689, ctrl->val, &sensor_gain); 593 cci_write(regmap, OV4689_REG_GAIN, sensor_gain, &ret); 594 break; 595 case V4L2_CID_VBLANK: 596 cci_write(regmap, OV4689_REG_VTS, 597 ctrl->val + ov4689->cur_mode->height, &ret); 598 break; 599 case V4L2_CID_TEST_PATTERN: 600 ret = ov4689_enable_test_pattern(ov4689, ctrl->val); 601 break; 602 default: 603 dev_warn(dev, "%s Unhandled id:0x%x, val:0x%x\n", 604 __func__, ctrl->id, ctrl->val); 605 ret = -EINVAL; 606 break; 607 } 608 609 pm_runtime_put(dev); 610 611 return ret; 612 } 613 614 static const struct v4l2_ctrl_ops ov4689_ctrl_ops = { 615 .s_ctrl = ov4689_set_ctrl, 616 }; 617 618 static int ov4689_initialize_controls(struct ov4689 *ov4689) 619 { 620 struct i2c_client *client = v4l2_get_subdevdata(&ov4689->subdev); 621 struct v4l2_fwnode_device_properties props; 622 struct v4l2_ctrl_handler *handler; 623 const struct ov4689_mode *mode; 624 s64 exposure_max, vblank_def; 625 struct v4l2_ctrl *ctrl; 626 s64 h_blank_def; 627 int ret; 628 629 handler = &ov4689->ctrl_handler; 630 mode = ov4689->cur_mode; 631 ret = v4l2_ctrl_handler_init(handler, 10); 632 if (ret) 633 return ret; 634 635 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0, 636 link_freq_menu_items); 637 if (ctrl) 638 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 639 640 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, 641 mode->pixel_rate, 1, mode->pixel_rate); 642 643 h_blank_def = mode->hts_def - mode->width; 644 ctrl = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, h_blank_def, 645 h_blank_def, 1, h_blank_def); 646 if (ctrl) 647 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 648 649 vblank_def = mode->vts_def - mode->height; 650 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_VBLANK, 651 vblank_def, OV4689_VTS_MAX - mode->height, 1, 652 vblank_def); 653 654 exposure_max = mode->vts_def - 4; 655 ov4689->exposure = 656 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_EXPOSURE, 657 OV4689_EXPOSURE_MIN, exposure_max, 658 OV4689_EXPOSURE_STEP, mode->exp_def); 659 660 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 661 ov4689_gain_ranges[0].logical_min, 662 ov4689_gain_ranges[ARRAY_SIZE(ov4689_gain_ranges) - 1] 663 .logical_max, 664 OV4689_GAIN_STEP, OV4689_GAIN_DEFAULT); 665 666 v4l2_ctrl_new_std_menu_items(handler, &ov4689_ctrl_ops, 667 V4L2_CID_TEST_PATTERN, 668 ARRAY_SIZE(ov4689_test_pattern_menu) - 1, 669 0, 0, ov4689_test_pattern_menu); 670 671 if (handler->error) { 672 ret = handler->error; 673 dev_err(ov4689->dev, "Failed to init controls(%d)\n", ret); 674 goto err_free_handler; 675 } 676 677 ret = v4l2_fwnode_device_parse(&client->dev, &props); 678 if (ret) 679 goto err_free_handler; 680 681 ret = v4l2_ctrl_new_fwnode_properties(handler, &ov4689_ctrl_ops, 682 &props); 683 if (ret) 684 goto err_free_handler; 685 686 ov4689->subdev.ctrl_handler = handler; 687 688 return 0; 689 690 err_free_handler: 691 v4l2_ctrl_handler_free(handler); 692 693 return ret; 694 } 695 696 static int ov4689_check_sensor_id(struct ov4689 *ov4689, 697 struct i2c_client *client) 698 { 699 struct device *dev = ov4689->dev; 700 u64 id = 0; 701 int ret; 702 703 ret = cci_read(ov4689->regmap, OV4689_REG_CHIP_ID, &id, NULL); 704 if (ret) { 705 dev_err(dev, "Cannot read sensor ID\n"); 706 return ret; 707 } 708 709 if (id != CHIP_ID) { 710 dev_err(dev, "Unexpected sensor ID %06llx, expected %06x\n", 711 id, CHIP_ID); 712 return -ENODEV; 713 } 714 715 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID); 716 717 return 0; 718 } 719 720 static int ov4689_configure_regulators(struct ov4689 *ov4689) 721 { 722 unsigned int i; 723 724 for (i = 0; i < ARRAY_SIZE(ov4689_supply_names); i++) 725 ov4689->supplies[i].supply = ov4689_supply_names[i]; 726 727 return devm_regulator_bulk_get(ov4689->dev, 728 ARRAY_SIZE(ov4689_supply_names), 729 ov4689->supplies); 730 } 731 732 static u64 ov4689_check_link_frequency(struct v4l2_fwnode_endpoint *ep) 733 { 734 const u64 *freqs = link_freq_menu_items; 735 unsigned int i, j; 736 737 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 738 for (j = 0; j < ep->nr_of_link_frequencies; j++) 739 if (freqs[i] == ep->link_frequencies[j]) 740 return freqs[i]; 741 } 742 743 return 0; 744 } 745 746 static int ov4689_check_hwcfg(struct device *dev) 747 { 748 struct fwnode_handle *fwnode = dev_fwnode(dev); 749 struct v4l2_fwnode_endpoint bus_cfg = { 750 .bus_type = V4L2_MBUS_CSI2_DPHY, 751 }; 752 struct fwnode_handle *endpoint; 753 int ret; 754 755 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 756 if (!endpoint) 757 return -EINVAL; 758 759 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 760 fwnode_handle_put(endpoint); 761 if (ret) 762 return ret; 763 764 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV4689_LANES) { 765 dev_err(dev, "Only a 4-lane CSI2 config is supported"); 766 ret = -EINVAL; 767 goto out_free_bus_cfg; 768 } 769 770 if (!ov4689_check_link_frequency(&bus_cfg)) { 771 dev_err(dev, "No supported link frequency found\n"); 772 ret = -EINVAL; 773 } 774 775 out_free_bus_cfg: 776 v4l2_fwnode_endpoint_free(&bus_cfg); 777 778 return ret; 779 } 780 781 static int ov4689_probe(struct i2c_client *client) 782 { 783 struct device *dev = &client->dev; 784 struct v4l2_subdev *sd; 785 struct ov4689 *ov4689; 786 int ret; 787 788 ret = ov4689_check_hwcfg(dev); 789 if (ret) 790 return ret; 791 792 ov4689 = devm_kzalloc(dev, sizeof(*ov4689), GFP_KERNEL); 793 if (!ov4689) 794 return -ENOMEM; 795 796 ov4689->dev = dev; 797 798 ov4689->cur_mode = &supported_modes[OV4689_MODE_2688_1520]; 799 800 ov4689->xvclk = devm_clk_get_optional(dev, NULL); 801 if (IS_ERR(ov4689->xvclk)) 802 return dev_err_probe(dev, PTR_ERR(ov4689->xvclk), 803 "Failed to get external clock\n"); 804 805 if (!ov4689->xvclk) { 806 dev_dbg(dev, 807 "No clock provided, using clock-frequency property\n"); 808 device_property_read_u32(dev, "clock-frequency", 809 &ov4689->clock_rate); 810 } else { 811 ov4689->clock_rate = clk_get_rate(ov4689->xvclk); 812 } 813 814 if (ov4689->clock_rate != OV4689_XVCLK_FREQ) { 815 dev_err(dev, 816 "External clock rate mismatch: got %d Hz, expected %d Hz\n", 817 ov4689->clock_rate, OV4689_XVCLK_FREQ); 818 return -EINVAL; 819 } 820 821 ov4689->regmap = devm_cci_regmap_init_i2c(client, 16); 822 if (IS_ERR(ov4689->regmap)) { 823 ret = PTR_ERR(ov4689->regmap); 824 dev_err(dev, "failed to initialize CCI: %d\n", ret); 825 return ret; 826 } 827 828 ov4689->reset_gpio = devm_gpiod_get_optional(dev, "reset", 829 GPIOD_OUT_LOW); 830 if (IS_ERR(ov4689->reset_gpio)) { 831 dev_err(dev, "Failed to get reset-gpios\n"); 832 return PTR_ERR(ov4689->reset_gpio); 833 } 834 835 ov4689->pwdn_gpio = devm_gpiod_get_optional(dev, "pwdn", GPIOD_OUT_LOW); 836 if (IS_ERR(ov4689->pwdn_gpio)) { 837 dev_err(dev, "Failed to get pwdn-gpios\n"); 838 return PTR_ERR(ov4689->pwdn_gpio); 839 } 840 841 ret = ov4689_configure_regulators(ov4689); 842 if (ret) 843 return dev_err_probe(dev, ret, 844 "Failed to get power regulators\n"); 845 846 sd = &ov4689->subdev; 847 v4l2_i2c_subdev_init(sd, client, &ov4689_subdev_ops); 848 sd->internal_ops = &ov4689_internal_ops; 849 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 850 ret = ov4689_initialize_controls(ov4689); 851 if (ret) { 852 dev_err(dev, "Failed to initialize controls\n"); 853 return ret; 854 } 855 856 ret = ov4689_power_on(dev); 857 if (ret) 858 goto err_free_handler; 859 860 ret = ov4689_check_sensor_id(ov4689, client); 861 if (ret) 862 goto err_power_off; 863 864 865 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 866 ov4689->pad.flags = MEDIA_PAD_FL_SOURCE; 867 ret = media_entity_pads_init(&sd->entity, 1, &ov4689->pad); 868 if (ret < 0) 869 goto err_power_off; 870 871 sd->state_lock = ov4689->ctrl_handler.lock; 872 ret = v4l2_subdev_init_finalize(sd); 873 if (ret) { 874 dev_err(dev, "Could not register v4l2 device\n"); 875 goto err_clean_entity; 876 } 877 878 pm_runtime_set_active(dev); 879 pm_runtime_enable(dev); 880 pm_runtime_idle(dev); 881 882 ret = v4l2_async_register_subdev_sensor(sd); 883 if (ret) { 884 dev_err(dev, "v4l2 async register subdev failed\n"); 885 goto err_clean_subdev_pm; 886 } 887 888 return 0; 889 890 err_clean_subdev_pm: 891 pm_runtime_disable(dev); 892 pm_runtime_set_suspended(dev); 893 v4l2_subdev_cleanup(sd); 894 err_clean_entity: 895 media_entity_cleanup(&sd->entity); 896 err_power_off: 897 ov4689_power_off(dev); 898 err_free_handler: 899 v4l2_ctrl_handler_free(&ov4689->ctrl_handler); 900 901 return ret; 902 } 903 904 static void ov4689_remove(struct i2c_client *client) 905 { 906 struct v4l2_subdev *sd = i2c_get_clientdata(client); 907 struct ov4689 *ov4689 = to_ov4689(sd); 908 909 v4l2_async_unregister_subdev(sd); 910 media_entity_cleanup(&sd->entity); 911 v4l2_subdev_cleanup(sd); 912 v4l2_ctrl_handler_free(&ov4689->ctrl_handler); 913 914 pm_runtime_disable(&client->dev); 915 if (!pm_runtime_status_suspended(&client->dev)) 916 ov4689_power_off(&client->dev); 917 pm_runtime_set_suspended(&client->dev); 918 } 919 920 static const struct of_device_id ov4689_of_match[] = { 921 { .compatible = "ovti,ov4689" }, 922 {}, 923 }; 924 MODULE_DEVICE_TABLE(of, ov4689_of_match); 925 926 static struct i2c_driver ov4689_i2c_driver = { 927 .driver = { 928 .name = "ov4689", 929 .pm = &ov4689_pm_ops, 930 .of_match_table = ov4689_of_match, 931 }, 932 .probe = ov4689_probe, 933 .remove = ov4689_remove, 934 }; 935 936 module_i2c_driver(ov4689_i2c_driver); 937 938 MODULE_DESCRIPTION("OmniVision ov4689 sensor driver"); 939 MODULE_LICENSE("GPL"); 940