1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ov2732 driver 4 * 5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. 6 * Copyright (C) 2025-2026 Walter Werner Schneider <contact@schnwalter.eu> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regulator/consumer.h> 17 #include <media/v4l2-cci.h> 18 #include <media/v4l2-common.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-fwnode.h> 22 23 #define OV2732_LANES 2 24 #define OV2732_BITS_PER_SAMPLE 10 25 #define OV2732_LINK_FREQ_DEFAULT 360000000 26 #define OV2732_XVCLK_FREQ 24000000 27 #define OV2732_PIXEL_RATE \ 28 (OV2732_LINK_FREQ_DEFAULT * 2 * OV2732_LANES / OV2732_BITS_PER_SAMPLE) 29 #define OV2732_NATIVE_WIDTH 1920U 30 #define OV2732_NATIVE_HEIGHT 1080U 31 32 /* Delay from power up to the first SCCB transaction. */ 33 #define OV2732_POWER_UP_DELAY_CYCLES 8192 34 /* Delay from the last SCCB transaction to power down. */ 35 #define OV2732_POWER_DOWN_DELAY_CYCLES 512 36 #define OV2732_DELAY_US(cycles) \ 37 (DIV_ROUND_UP((cycles), OV2732_XVCLK_FREQ / USEC_PER_SEC)) 38 39 #define OV2732_REG_CHIP_ID CCI_REG24(0x300a) 40 #define OV2732_CHIP_ID 0x002732 41 42 #define OV2732_REG_MODE_SELECT CCI_REG8(0x0100) 43 #define OV2732_MODE_STANDBY 0x00 44 #define OV2732_MODE_STREAMING 0x01 45 46 #define OV2732_REG_ANALOGUE_GAIN CCI_REG16(0x3508) 47 #define OV2732_REG_DIGITAL_GAIN CCI_REG16(0x350a) 48 #define OV2732_REG_EXPOSURE CCI_REG24(0x3500) 49 #define OV2732_REG_HTS CCI_REG16(0x380c) 50 #define OV2732_REG_VTS CCI_REG16(0x380e) 51 #define OV2732_ANALOGUE_GAIN_MIN 0x80 52 /* Max analogue gain is documented as 0x3fff, but it overflows after 0x3ff. */ 53 #define OV2732_ANALOGUE_GAIN_MAX 0x3ff 54 #define OV2732_ANALOGUE_GAIN_DEFAULT 0x80 55 #define OV2732_DIGITAL_GAIN_MIN 0x00 56 #define OV2732_DIGITAL_GAIN_MAX 0x3fff 57 #define OV2732_DIGITAL_GAIN_DEFAULT 0x0400 58 #define OV2732_EXPOSURE_DEFAULT 0x40 59 #define OV2732_EXPOSURE_MIN 0x10 60 #define OV2732_EXPOSURE_OFFSET 4 61 #define OV2732_HBLANK_DEFAULT 0x0068 62 #define OV2732_VTS_MAX 0x7fff 63 64 #define OV2732_REG_TEST_PATTERN CCI_REG8(0x5080) 65 #define OV2732_TEST_PATTERN_DISABLE 0x00 66 #define OV2732_TEST_PATTERN_BAR1 0x80 67 #define OV2732_TEST_PATTERN_BAR2 0x84 68 #define OV2732_TEST_PATTERN_BAR3 0x88 69 #define OV2732_TEST_PATTERN_BAR4 0x8c 70 #define OV2732_TEST_PATTERN_BAR5 0xC0 71 #define OV2732_TEST_PATTERN_RANDOM 0x81 72 #define OV2732_TEST_PATTERN_SQUARES_C 0x82 73 #define OV2732_TEST_PATTERN_SQUARES_BW 0x92 74 75 static const char * const ov2732_supply_names[] = { 76 "avdd", /* Analog power */ 77 "dovdd", /* Digital I/O power */ 78 "dvdd", /* Digital core power */ 79 }; 80 81 static const struct cci_reg_sequence ov2732_common_regs[] = { 82 /* PLL control, reset all registers. */ 83 { CCI_REG8(0x0103), 0x01 }, 84 85 /* Analog control. */ 86 { CCI_REG8(0x3600), 0x55 }, 87 { CCI_REG8(0x3601), 0x52 }, 88 { CCI_REG8(0x3612), 0xb5 }, 89 { CCI_REG8(0x3613), 0xb3 }, 90 { CCI_REG8(0x3616), 0x83 }, 91 { CCI_REG8(0x3621), 0x00 }, 92 { CCI_REG8(0x3624), 0x06 }, 93 { CCI_REG8(0x3642), 0x88 }, 94 { CCI_REG8(0x3660), 0x00 }, 95 { CCI_REG8(0x3661), 0x00 }, 96 { CCI_REG8(0x366a), 0x64 }, 97 { CCI_REG8(0x366c), 0x00 }, 98 { CCI_REG8(0x366e), 0xff }, 99 { CCI_REG8(0x366f), 0xff }, 100 { CCI_REG8(0x3677), 0x11 }, 101 { CCI_REG8(0x3678), 0x11 }, 102 { CCI_REG8(0x3679), 0x0c }, 103 { CCI_REG8(0x3680), 0xff }, 104 { CCI_REG8(0x3681), 0x16 }, 105 { CCI_REG8(0x3682), 0x16 }, 106 { CCI_REG8(0x3683), 0x90 }, 107 { CCI_REG8(0x3684), 0x90 }, 108 109 /* ADC sync control. */ 110 { CCI_REG8(0x4503), 0x00 }, 111 { CCI_REG8(0x4508), 0x14 }, 112 { CCI_REG8(0x450a), 0x00 }, 113 { CCI_REG8(0x450b), 0x40 }, 114 115 /* ISP control, enable: WIN, DPC & ISP. */ 116 { CCI_REG8(0x5000), 0xa1 }, 117 }; 118 119 struct ov2732_mode { 120 u32 width; 121 u32 height; 122 u32 vts; 123 }; 124 125 static const struct ov2732_mode supported_modes[] = { 126 { 127 .width = 1920, 128 .height = 1080, 129 .vts = 1184, 130 }, 131 }; 132 133 struct ov2732 { 134 struct device *dev; 135 struct regmap *regmap; 136 137 struct media_pad pad; 138 struct v4l2_subdev sd; 139 struct v4l2_ctrl_handler ctrl_handler; 140 struct v4l2_ctrl *hblank; 141 struct v4l2_ctrl *vblank; 142 struct v4l2_ctrl *exposure; 143 144 struct clk *xvclk; 145 u32 xvclk_freq; 146 struct gpio_desc *powerdown_gpio; 147 struct gpio_desc *reset_gpio; 148 struct regulator_bulk_data supplies[ARRAY_SIZE(ov2732_supply_names)]; 149 }; 150 151 #define to_ov2732(_sd) container_of(_sd, struct ov2732, sd) 152 153 static const s64 link_freq_menu_items[] = { 154 OV2732_LINK_FREQ_DEFAULT, 155 }; 156 157 static const char * const ov2732_test_pattern_menu[] = { 158 "Disabled", 159 "Vertical Color Bar Type 1", 160 "Vertical Color Bar Type 2", 161 "Vertical Color Bar Type 3", 162 "Vertical Color Bar Type 4", 163 "Vertical Color Bar Type 5", 164 "Random", 165 "Color Squares", 166 "Black and White Squares", 167 }; 168 169 static const int ov2732_test_pattern_val[] = { 170 OV2732_TEST_PATTERN_DISABLE, 171 OV2732_TEST_PATTERN_BAR1, 172 OV2732_TEST_PATTERN_BAR2, 173 OV2732_TEST_PATTERN_BAR3, 174 OV2732_TEST_PATTERN_BAR4, 175 OV2732_TEST_PATTERN_BAR5, 176 OV2732_TEST_PATTERN_RANDOM, 177 OV2732_TEST_PATTERN_SQUARES_C, 178 OV2732_TEST_PATTERN_SQUARES_BW, 179 }; 180 181 static int ov2732_power_on(struct device *dev) 182 { 183 struct v4l2_subdev *sd = dev_get_drvdata(dev); 184 struct ov2732 *ov2732 = to_ov2732(sd); 185 int ret; 186 187 ret = regulator_bulk_enable(ARRAY_SIZE(ov2732_supply_names), 188 ov2732->supplies); 189 if (ret) { 190 dev_err(dev, "failed to enable regulators\n"); 191 return ret; 192 } 193 194 ret = clk_prepare_enable(ov2732->xvclk); 195 if (ret) { 196 dev_err(dev, "failed to enable clock\n"); 197 goto reg_off; 198 } 199 200 /* Wait 10ms before power up, as per datasheet. */ 201 fsleep(10 * USEC_PER_MSEC); 202 203 gpiod_set_value_cansleep(ov2732->reset_gpio, 0); 204 gpiod_set_value_cansleep(ov2732->powerdown_gpio, 0); 205 206 /* Datasheet requires an 8192 cycles wait, but that isn't enough. */ 207 fsleep(OV2732_DELAY_US(OV2732_POWER_UP_DELAY_CYCLES * 2)); 208 209 return 0; 210 211 reg_off: 212 regulator_bulk_disable(ARRAY_SIZE(ov2732_supply_names), 213 ov2732->supplies); 214 215 return ret; 216 } 217 218 static int ov2732_power_off(struct device *dev) 219 { 220 struct v4l2_subdev *sd = dev_get_drvdata(dev); 221 struct ov2732 *ov2732 = to_ov2732(sd); 222 223 clk_disable_unprepare(ov2732->xvclk); 224 225 /* Wait for 512 cycles as per datasheet. */ 226 fsleep(OV2732_DELAY_US(OV2732_POWER_DOWN_DELAY_CYCLES)); 227 228 gpiod_set_value_cansleep(ov2732->powerdown_gpio, 1); 229 gpiod_set_value_cansleep(ov2732->reset_gpio, 1); 230 231 regulator_bulk_disable(ARRAY_SIZE(ov2732_supply_names), 232 ov2732->supplies); 233 234 return 0; 235 } 236 237 static int ov2732_identify_chip(struct ov2732 *ov2732) 238 { 239 struct i2c_client *client = v4l2_get_subdevdata(&ov2732->sd); 240 int ret; 241 u64 val; 242 243 ret = cci_read(ov2732->regmap, OV2732_REG_CHIP_ID, &val, NULL); 244 if (ret) 245 return dev_err_probe(&client->dev, ret, 246 "failed to read chip id\n"); 247 248 if (val != OV2732_CHIP_ID) 249 return dev_err_probe(&client->dev, -ENODEV, 250 "chip id mismatch: %x!=%llx\n", 251 OV2732_CHIP_ID, val); 252 253 return 0; 254 } 255 256 static int ov2732_enum_mbus_code(struct v4l2_subdev *sd, 257 struct v4l2_subdev_state *state, 258 struct v4l2_subdev_mbus_code_enum *code) 259 { 260 if (code->index != 0) 261 return -EINVAL; 262 263 code->code = MEDIA_BUS_FMT_SBGGR10_1X10; 264 265 return 0; 266 } 267 268 static int ov2732_enum_frame_size(struct v4l2_subdev *sd, 269 struct v4l2_subdev_state *state, 270 struct v4l2_subdev_frame_size_enum *fse) 271 { 272 if (fse->index >= ARRAY_SIZE(supported_modes)) 273 return -EINVAL; 274 275 fse->min_width = supported_modes[fse->index].width; 276 fse->max_width = fse->min_width; 277 fse->min_height = supported_modes[fse->index].height; 278 fse->max_height = fse->min_height; 279 280 return 0; 281 } 282 283 static int ov2732_set_fmt(struct v4l2_subdev *sd, 284 struct v4l2_subdev_state *state, 285 struct v4l2_subdev_format *fmt) 286 { 287 struct ov2732 *ov2732 = to_ov2732(sd); 288 const struct ov2732_mode *mode; 289 s64 vblank_def; 290 int ret; 291 292 mode = v4l2_find_nearest_size(supported_modes, 293 ARRAY_SIZE(supported_modes), 294 width, height, 295 fmt->format.width, fmt->format.height); 296 297 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; 298 fmt->format.width = mode->width; 299 fmt->format.height = mode->height; 300 fmt->format.field = V4L2_FIELD_NONE; 301 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 302 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 303 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 304 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 305 306 *v4l2_subdev_state_get_format(state, fmt->pad) = fmt->format; 307 308 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 309 return 0; 310 311 vblank_def = mode->vts - mode->height; 312 ret = __v4l2_ctrl_modify_range(ov2732->vblank, vblank_def, 313 OV2732_VTS_MAX - mode->height, 1, 314 vblank_def); 315 316 return ret; 317 } 318 319 static int ov2732_get_selection(struct v4l2_subdev *sd, 320 struct v4l2_subdev_state *state, 321 struct v4l2_subdev_selection *sel) 322 { 323 switch (sel->target) { 324 case V4L2_SEL_TGT_CROP: 325 sel->r = *v4l2_subdev_state_get_crop(state, 0); 326 return 0; 327 328 case V4L2_SEL_TGT_NATIVE_SIZE: 329 case V4L2_SEL_TGT_CROP_DEFAULT: 330 case V4L2_SEL_TGT_CROP_BOUNDS: 331 sel->r.top = 0; 332 sel->r.left = 0; 333 sel->r.width = OV2732_NATIVE_WIDTH; 334 sel->r.height = OV2732_NATIVE_HEIGHT; 335 336 return 0; 337 } 338 339 return -EINVAL; 340 } 341 342 static int ov2732_enable_streams(struct v4l2_subdev *sd, 343 struct v4l2_subdev_state *state, u32 pad, 344 u64 streams_mask) 345 { 346 struct ov2732 *ov2732 = to_ov2732(sd); 347 struct i2c_client *client = v4l2_get_subdevdata(&ov2732->sd); 348 int ret; 349 350 ret = pm_runtime_resume_and_get(&client->dev); 351 if (ret < 0) 352 return ret; 353 354 /* Set stream off register for PLL changes. */ 355 ret = cci_write(ov2732->regmap, OV2732_REG_MODE_SELECT, 356 OV2732_MODE_STANDBY, NULL); 357 if (ret) 358 goto err_put_autosuspend; 359 360 /* Send all registers that are common to all modes */ 361 ret = cci_multi_reg_write(ov2732->regmap, ov2732_common_regs, 362 ARRAY_SIZE(ov2732_common_regs), NULL); 363 if (ret) { 364 dev_err(&client->dev, "failed to init registers\n"); 365 goto err_put_autosuspend; 366 } 367 368 /* Apply customized values from user */ 369 ret = __v4l2_ctrl_handler_setup(ov2732->sd.ctrl_handler); 370 if (ret) 371 goto err_put_autosuspend; 372 373 /* Set stream on register */ 374 ret = cci_write(ov2732->regmap, OV2732_REG_MODE_SELECT, 375 OV2732_MODE_STREAMING, NULL); 376 if (ret) 377 goto err_put_autosuspend; 378 379 return 0; 380 381 err_put_autosuspend: 382 pm_runtime_put_autosuspend(&client->dev); 383 384 return ret; 385 } 386 387 static int ov2732_disable_streams(struct v4l2_subdev *sd, 388 struct v4l2_subdev_state *state, u32 pad, 389 u64 streams_mask) 390 { 391 struct ov2732 *ov2732 = to_ov2732(sd); 392 struct i2c_client *client = v4l2_get_subdevdata(&ov2732->sd); 393 int ret; 394 395 /* set stream off register */ 396 ret = cci_write(ov2732->regmap, OV2732_REG_MODE_SELECT, 397 OV2732_MODE_STANDBY, NULL); 398 if (ret) 399 dev_err(&client->dev, "%s failed to set stream\n", __func__); 400 401 /* Wait for 512 cycles as per datasheet. */ 402 fsleep(OV2732_DELAY_US(OV2732_POWER_DOWN_DELAY_CYCLES)); 403 404 pm_runtime_put_autosuspend(&client->dev); 405 406 return ret; 407 } 408 409 static const struct v4l2_subdev_video_ops ov2732_video_ops = { 410 .s_stream = v4l2_subdev_s_stream_helper, 411 }; 412 413 static const struct v4l2_subdev_pad_ops ov2732_pad_ops = { 414 .enum_mbus_code = ov2732_enum_mbus_code, 415 .enum_frame_size = ov2732_enum_frame_size, 416 .get_fmt = v4l2_subdev_get_fmt, 417 .set_fmt = ov2732_set_fmt, 418 .get_selection = ov2732_get_selection, 419 .enable_streams = ov2732_enable_streams, 420 .disable_streams = ov2732_disable_streams, 421 }; 422 423 static const struct v4l2_subdev_ops ov2732_subdev_ops = { 424 .video = &ov2732_video_ops, 425 .pad = &ov2732_pad_ops, 426 }; 427 428 static int ov2732_init_state(struct v4l2_subdev *sd, 429 struct v4l2_subdev_state *sd_state) 430 { 431 struct v4l2_subdev_format fmt = { 432 .which = V4L2_SUBDEV_FORMAT_TRY, 433 .format = { 434 .width = 1920, 435 .height = 1080, 436 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 437 .colorspace = V4L2_COLORSPACE_RAW, 438 .field = V4L2_FIELD_NONE, 439 .quantization = V4L2_QUANTIZATION_FULL_RANGE, 440 .xfer_func = V4L2_XFER_FUNC_NONE, 441 .ycbcr_enc = V4L2_YCBCR_ENC_601, 442 } 443 }; 444 445 return ov2732_set_fmt(sd, sd_state, &fmt); 446 } 447 448 static const struct v4l2_subdev_internal_ops ov2732_internal_ops = { 449 .init_state = ov2732_init_state, 450 }; 451 452 static int ov2732_set_ctrl(struct v4l2_ctrl *ctrl) 453 { 454 struct ov2732 *ov2732 = 455 container_of(ctrl->handler, struct ov2732, ctrl_handler); 456 struct i2c_client *client = v4l2_get_subdevdata(&ov2732->sd); 457 const struct v4l2_mbus_framefmt *format; 458 struct v4l2_subdev_state *state; 459 int ret = 0; 460 461 state = v4l2_subdev_get_locked_active_state(&ov2732->sd); 462 format = v4l2_subdev_state_get_format(state, 0); 463 464 if (ctrl->id == V4L2_CID_VBLANK) { 465 int exposure_max, exposure_def; 466 467 exposure_max = format->height + ctrl->val - 468 OV2732_EXPOSURE_OFFSET; 469 exposure_def = exposure_max; 470 ret = __v4l2_ctrl_modify_range(ov2732->exposure, 471 OV2732_EXPOSURE_MIN, 472 exposure_max, 473 ov2732->exposure->step, 474 exposure_def); 475 if (ret) 476 return ret; 477 } 478 479 if (pm_runtime_get_if_in_use(&client->dev) == 0) 480 return 0; 481 482 switch (ctrl->id) { 483 case V4L2_CID_ANALOGUE_GAIN: 484 cci_write(ov2732->regmap, OV2732_REG_ANALOGUE_GAIN, 485 ctrl->val, &ret); 486 break; 487 case V4L2_CID_DIGITAL_GAIN: 488 cci_write(ov2732->regmap, OV2732_REG_DIGITAL_GAIN, 489 ctrl->val, &ret); 490 break; 491 case V4L2_CID_EXPOSURE: 492 /* Lowest 4 bits are fraction bits. */ 493 cci_write(ov2732->regmap, OV2732_REG_EXPOSURE, 494 (u32)ctrl->val << 4, &ret); 495 break; 496 case V4L2_CID_VBLANK: 497 cci_write(ov2732->regmap, OV2732_REG_VTS, 498 format->height + ctrl->val, &ret); 499 break; 500 case V4L2_CID_TEST_PATTERN: 501 cci_write(ov2732->regmap, OV2732_REG_TEST_PATTERN, 502 ov2732_test_pattern_val[ctrl->val], &ret); 503 break; 504 default: 505 dev_info(&client->dev, 506 "ctrl(id:0x%x,val:0x%x) is not handled\n", 507 ctrl->id, ctrl->val); 508 ret = -EINVAL; 509 break; 510 } 511 512 pm_runtime_put(&client->dev); 513 514 return ret; 515 }; 516 517 static const struct v4l2_ctrl_ops ov2732_ctrl_ops = { 518 .s_ctrl = ov2732_set_ctrl, 519 }; 520 521 static int ov2732_init_controls(struct ov2732 *ov2732) 522 { 523 const struct ov2732_mode *mode = &supported_modes[0]; 524 struct v4l2_ctrl_handler *handler; 525 struct v4l2_ctrl *ctrl; 526 struct v4l2_fwnode_device_properties props; 527 s64 exposure_max, vblank_def, vblank_max; 528 int ret; 529 530 handler = &ov2732->ctrl_handler; 531 ret = v4l2_ctrl_handler_init(handler, 10); 532 533 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 534 OV2732_PIXEL_RATE, OV2732_PIXEL_RATE, 535 1, OV2732_PIXEL_RATE); 536 537 ctrl = v4l2_ctrl_new_int_menu(handler, &ov2732_ctrl_ops, 538 V4L2_CID_LINK_FREQ, 0, 0, 539 link_freq_menu_items); 540 if (ctrl) 541 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 542 543 ov2732->hblank = v4l2_ctrl_new_std(handler, &ov2732_ctrl_ops, 544 V4L2_CID_HBLANK, 545 OV2732_HBLANK_DEFAULT, 546 OV2732_HBLANK_DEFAULT, 547 1, OV2732_HBLANK_DEFAULT); 548 if (ov2732->hblank) 549 ov2732->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 550 551 vblank_def = mode->vts - mode->height; 552 vblank_max = OV2732_VTS_MAX - mode->height; 553 ov2732->vblank = v4l2_ctrl_new_std(handler, &ov2732_ctrl_ops, 554 V4L2_CID_VBLANK, 555 vblank_def, vblank_max, 556 1, vblank_def); 557 558 exposure_max = mode->vts - OV2732_EXPOSURE_OFFSET; 559 ov2732->exposure = v4l2_ctrl_new_std(handler, &ov2732_ctrl_ops, 560 V4L2_CID_EXPOSURE, 561 OV2732_EXPOSURE_MIN, exposure_max, 562 1, OV2732_EXPOSURE_DEFAULT); 563 564 v4l2_ctrl_new_std(handler, &ov2732_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 565 OV2732_ANALOGUE_GAIN_MIN, OV2732_ANALOGUE_GAIN_MAX, 566 1, OV2732_ANALOGUE_GAIN_DEFAULT); 567 568 v4l2_ctrl_new_std(handler, &ov2732_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 569 OV2732_DIGITAL_GAIN_MIN, OV2732_DIGITAL_GAIN_MAX, 570 1, OV2732_DIGITAL_GAIN_DEFAULT); 571 572 v4l2_ctrl_new_std_menu_items(handler, &ov2732_ctrl_ops, 573 V4L2_CID_TEST_PATTERN, 574 ARRAY_SIZE(ov2732_test_pattern_menu) - 1, 575 0, 0, ov2732_test_pattern_menu); 576 577 if (handler->error) { 578 ret = handler->error; 579 dev_err_probe(ov2732->dev, ret, "Control init failed\n"); 580 goto err_handler_free; 581 } 582 583 ret = v4l2_fwnode_device_parse(ov2732->dev, &props); 584 if (ret) 585 goto err_handler_free; 586 587 ret = v4l2_ctrl_new_fwnode_properties(handler, &ov2732_ctrl_ops, &props); 588 if (ret) 589 goto err_handler_free; 590 591 ov2732->sd.ctrl_handler = handler; 592 593 return 0; 594 595 err_handler_free: 596 v4l2_ctrl_handler_free(handler); 597 598 return ret; 599 } 600 601 static int ov2632_probe_dt(struct ov2732 *ov2732) 602 { 603 struct fwnode_handle *ep; 604 struct fwnode_handle *fwnode = dev_fwnode(ov2732->dev); 605 struct v4l2_fwnode_endpoint bus_cfg = { 606 .bus_type = V4L2_MBUS_CSI2_DPHY, 607 }; 608 int ret; 609 610 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0); 611 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 612 fwnode_handle_put(ep); 613 if (ret) { 614 dev_err_probe(ov2732->dev, -EINVAL, "could not parse endpoint\n"); 615 goto err_probe_dt; 616 } 617 618 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2732_LANES) { 619 dev_err(ov2732->dev, "only a 2-lane CSI2 config is supported\n"); 620 ret = -EINVAL; 621 } 622 623 err_probe_dt: 624 v4l2_fwnode_endpoint_free(&bus_cfg); 625 626 return ret; 627 } 628 629 static int ov2732_get_regulators(struct ov2732 *ov2732) 630 { 631 for (unsigned int i = 0; i < ARRAY_SIZE(ov2732_supply_names); i++) 632 ov2732->supplies[i].supply = ov2732_supply_names[i]; 633 634 return devm_regulator_bulk_get(ov2732->dev, 635 ARRAY_SIZE(ov2732_supply_names), 636 ov2732->supplies); 637 } 638 639 static int ov2732_probe(struct i2c_client *client) 640 { 641 struct ov2732 *ov2732; 642 int ret; 643 644 ov2732 = devm_kzalloc(&client->dev, sizeof(*ov2732), GFP_KERNEL); 645 if (!ov2732) 646 return -ENOMEM; 647 648 ov2732->dev = &client->dev; 649 650 ret = ov2632_probe_dt(ov2732); 651 if (ret) 652 return ret; 653 654 ov2732->xvclk = devm_v4l2_sensor_clk_get(ov2732->dev, NULL); 655 if (IS_ERR(ov2732->xvclk)) 656 return dev_err_probe(ov2732->dev, PTR_ERR(ov2732->xvclk), 657 "failed to get xvclk\n"); 658 659 ov2732->xvclk_freq = clk_get_rate(ov2732->xvclk); 660 if (ov2732->xvclk_freq != OV2732_XVCLK_FREQ) 661 return dev_err_probe(ov2732->dev, -EINVAL, 662 "xvclk frequency not supported: %dHz\n", 663 ov2732->xvclk_freq); 664 665 ov2732->powerdown_gpio = devm_gpiod_get_optional(ov2732->dev, 666 "powerdown", 667 GPIOD_OUT_HIGH); 668 669 ov2732->reset_gpio = devm_gpiod_get_optional(ov2732->dev, "reset", 670 GPIOD_OUT_HIGH); 671 672 ov2732->regmap = devm_cci_regmap_init_i2c(client, 16); 673 if (IS_ERR(ov2732->regmap)) 674 return dev_err_probe(ov2732->dev, PTR_ERR(ov2732->regmap), 675 "failed to init CCI\n"); 676 677 ret = ov2732_get_regulators(ov2732); 678 if (ret) 679 return dev_err_probe(ov2732->dev, ret, 680 "failed to get regulators\n"); 681 682 v4l2_i2c_subdev_init(&ov2732->sd, client, &ov2732_subdev_ops); 683 684 /* Device must be powered on for ov2732_identify_chip(). */ 685 ret = ov2732_power_on(ov2732->dev); 686 if (ret) 687 return ret; 688 689 pm_runtime_set_active(ov2732->dev); 690 pm_runtime_enable(ov2732->dev); 691 692 ret = ov2732_identify_chip(ov2732); 693 if (ret) 694 goto err_power_off; 695 696 ret = ov2732_init_controls(ov2732); 697 if (ret) 698 goto err_power_off; 699 700 /* Initialize subdev */ 701 ov2732->sd.internal_ops = &ov2732_internal_ops; 702 ov2732->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 703 ov2732->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 704 705 /* Initialize source pad */ 706 ov2732->pad.flags = MEDIA_PAD_FL_SOURCE; 707 708 ret = media_entity_pads_init(&ov2732->sd.entity, 1, &ov2732->pad); 709 if (ret) { 710 dev_err_probe(ov2732->dev, ret, "failed to init entity pads\n"); 711 goto error_handler_free; 712 } 713 714 ov2732->sd.state_lock = ov2732->ctrl_handler.lock; 715 ret = v4l2_subdev_init_finalize(&ov2732->sd); 716 if (ret < 0) { 717 dev_err_probe(ov2732->dev, ret, "subdev init error\n"); 718 goto err_media_entity; 719 } 720 721 ret = v4l2_async_register_subdev_sensor(&ov2732->sd); 722 if (ret < 0) { 723 dev_err_probe(ov2732->dev, ret, 724 "failed to register sensor sub-device\n"); 725 goto err_subdev_cleanup; 726 } 727 728 pm_runtime_set_autosuspend_delay(ov2732->dev, 1000); 729 pm_runtime_use_autosuspend(ov2732->dev); 730 pm_runtime_idle(ov2732->dev); 731 732 return 0; 733 734 err_subdev_cleanup: 735 v4l2_subdev_cleanup(&ov2732->sd); 736 737 err_media_entity: 738 media_entity_cleanup(&ov2732->sd.entity); 739 740 error_handler_free: 741 v4l2_ctrl_handler_free(&ov2732->ctrl_handler); 742 743 err_power_off: 744 pm_runtime_disable(ov2732->dev); 745 pm_runtime_set_suspended(ov2732->dev); 746 ov2732_power_off(ov2732->dev); 747 748 return ret; 749 } 750 751 static void ov2732_remove(struct i2c_client *client) 752 { 753 struct v4l2_subdev *sd = i2c_get_clientdata(client); 754 struct ov2732 *ov2732 = to_ov2732(sd); 755 756 v4l2_async_unregister_subdev(sd); 757 v4l2_subdev_cleanup(sd); 758 media_entity_cleanup(&sd->entity); 759 v4l2_ctrl_handler_free(&ov2732->ctrl_handler); 760 761 pm_runtime_disable(ov2732->dev); 762 if (!pm_runtime_status_suspended(ov2732->dev)) { 763 ov2732_power_off(ov2732->dev); 764 pm_runtime_set_suspended(ov2732->dev); 765 } 766 } 767 768 static const struct of_device_id ov2732_of_match[] = { 769 { .compatible = "ovti,ov2732", }, 770 { }, 771 }; 772 MODULE_DEVICE_TABLE(of, ov2732_of_match); 773 774 static DEFINE_RUNTIME_DEV_PM_OPS(ov2732_pm_ops, ov2732_power_off, 775 ov2732_power_on, NULL); 776 777 static struct i2c_driver ov2732_i2c_driver = { 778 .driver = { 779 .name = "ov2732", 780 .of_match_table = ov2732_of_match, 781 .pm = pm_sleep_ptr(&ov2732_pm_ops), 782 }, 783 .probe = ov2732_probe, 784 .remove = ov2732_remove, 785 }; 786 module_i2c_driver(ov2732_i2c_driver); 787 788 MODULE_DESCRIPTION("OmniVision ov2732 sensor driver"); 789 MODULE_LICENSE("GPL"); 790 MODULE_AUTHOR("Walter Werner Schneider <contact@schnwalter.eu>"); 791