1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * imx471.c - imx471 sensor driver 4 * 5 * Copyright (C) 2025 Intel Corporation 6 * Copyright (C) 2026 Kate Hsuan <hpa@redhat.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 #include <media/v4l2-cci.h> 16 #include <media/v4l2-ctrls.h> 17 #include <media/v4l2-subdev.h> 18 #include <media/v4l2-fwnode.h> 19 20 #define IMX471_REG_MODE_SELECT CCI_REG8(0x0100) 21 #define IMX471_MODE_STANDBY 0x00 22 #define IMX471_MODE_STREAMING 0x01 23 24 /* Chip ID */ 25 #define IMX471_REG_CHIP_ID CCI_REG16(0x0016) 26 #define IMX471_CHIP_ID 0x0471 27 28 /* V_TIMING internal */ 29 #define IMX471_REG_FLL CCI_REG16(0x0340) 30 #define IMX471_FLL_MAX 0xffff 31 32 /* Exposure control */ 33 #define IMX471_REG_EXPOSURE CCI_REG16(0x0202) 34 #define IMX471_EXPOSURE_MIN 1 35 #define IMX471_EXPOSURE_STEP 1 36 #define IMX471_EXPOSURE_DEFAULT 1270 37 38 /* Default exposure margin */ 39 #define IMX471_EXPOSURE_MARGIN 18 40 41 /* Analog gain control */ 42 #define IMX471_REG_ANALOG_GAIN CCI_REG16(0x0204) 43 #define IMX471_ANA_GAIN_MIN 0 44 #define IMX471_ANA_GAIN_MAX 800 45 #define IMX471_ANA_GAIN_STEP 1 46 #define IMX471_ANA_GAIN_DEFAULT 0 47 48 /* Digital gain control */ 49 #define IMX471_REG_DPGA_USE_GLOBAL_GAIN CCI_REG16(0x3ff9) 50 #define IMX471_REG_DIG_GAIN_GLOBAL CCI_REG16(0x020e) 51 #define IMX471_DGTL_GAIN_MIN 256 52 #define IMX471_DGTL_GAIN_MAX 4095 53 #define IMX471_DGTL_GAIN_STEP 1 54 #define IMX471_DGTL_GAIN_DEFAULT 256 55 56 /* HFLIP and VFLIP control */ 57 #define IMX471_REG_ORIENTATION CCI_REG8(0x0101) 58 59 /* Test Pattern Control */ 60 #define IMX471_REG_TEST_PATTERN CCI_REG8(0x0600) 61 62 /* default link frequency and external clock */ 63 #define IMX471_LINK_FREQ_DEFAULT 200000000LL 64 #define IMX471_EXT_CLK 19200000 65 66 /* PLL */ 67 #define IMX471_REG_VTPXCK_DIV CCI_REG8(0x0301) 68 #define IMX471_REG_VTSYCK_DIV CCI_REG8(0x0303) 69 #define IMX471_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305) 70 #define IMX471_REG_PLL_VT_MPY CCI_REG16(0x0306) 71 #define IMX471_REG_OPPXCK_DIV CCI_REG8(0x0309) 72 #define IMX471_REG_OPSYCK_DIV CCI_REG8(0x030b) 73 #define IMX471_REG_PLL_MULT_DRIV CCI_REG8(0x0310) 74 #define IMX471_PLL_SINGLE 0 75 #define IMX471_PLL_DUAL 1 76 77 /* IMX471 native and active pixel array size */ 78 #define IMX471_NATIVE_WIDTH 4672 79 #define IMX471_NATIVE_HEIGHT 3512 80 #define IMX471_PIXEL_ARRAY_LEFT 8 81 #define IMX471_PIXEL_ARRAY_TOP 8 82 #define IMX471_PIXEL_ARRAY_WIDTH 4656 83 #define IMX471_PIXEL_ARRAY_HEIGHT 3496 84 85 #define IMX471_REG_EXCK_FREQ CCI_REG16(0x0136) 86 87 #define IMX471_REG_CSI_DATA_FORMAT CCI_REG16(0x0112) 88 #define IMX471_CSI_DATA_FORMAT_RAW10 0x0a0a 89 90 #define IMX471_REG_CSI_LANE_MODE CCI_REG8(0x0114) 91 #define IMX471_CSI_2_LANE_MODE 1 92 #define IMX471_CSI_4_LANE_MODE 3 93 94 #define IMX471_REG_X_ADD_STA CCI_REG16(0x0344) 95 #define IMX471_REG_Y_ADD_STA CCI_REG16(0x0346) 96 #define IMX471_REG_X_ADD_END CCI_REG16(0x0348) 97 #define IMX471_REG_Y_ADD_END CCI_REG16(0x034a) 98 #define IMX471_REG_X_OUTPUT_SIZE CCI_REG16(0x034c) 99 #define IMX471_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e) 100 #define IMX471_REG_X_EVEN_INC CCI_REG8(0x0381) 101 #define IMX471_REG_X_ODD_INC CCI_REG8(0x0383) 102 #define IMX471_REG_Y_EVEN_INC CCI_REG8(0x0385) 103 #define IMX471_REG_Y_ODD_INC CCI_REG8(0x0387) 104 105 #define IMX471_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408) 106 #define IMX471_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a) 107 #define IMX471_REG_DIG_CROP_WIDTH CCI_REG16(0x040c) 108 #define IMX471_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e) 109 110 /* Binning mode */ 111 #define IMX471_REG_BINNING_MODE CCI_REG8(0x0900) 112 #define IMX471_BINNING_NONE 0 113 #define IMX471_BINNING_ENABLE 1 114 #define IMX471_REG_BINNING_TYPE CCI_REG8(0x0901) 115 #define IMX471_REG_BINNING_WEIGHTING CCI_REG8(0x0902) 116 117 #define to_imx471(_sd) container_of_const(_sd, struct imx471, sd) 118 119 static const char * const imx471_supply_name[] = { 120 "vana", 121 }; 122 123 struct imx471_mode { 124 u32 width; 125 u32 height; 126 127 /* V-timing */ 128 u32 fll_def; 129 u32 fll_min; 130 131 /* H-timing */ 132 u32 llp; 133 134 const struct cci_reg_sequence *default_mode_regs; 135 unsigned int default_mode_regs_length; 136 }; 137 138 struct imx471 { 139 struct v4l2_subdev sd; 140 struct media_pad pad; 141 142 struct v4l2_ctrl_handler ctrl_handler; 143 struct v4l2_ctrl *vblank; 144 struct v4l2_ctrl *hblank; 145 struct v4l2_ctrl *vflip; 146 struct v4l2_ctrl *hflip; 147 struct v4l2_ctrl *exposure; 148 149 struct gpio_desc *reset_gpio; 150 struct regulator_bulk_data supplies[ARRAY_SIZE(imx471_supply_name)]; 151 struct clk *img_clk; 152 153 struct device *dev; 154 struct regmap *regmap; 155 }; 156 157 static const struct cci_reg_sequence imx471_global_regs[] = { 158 { IMX471_REG_EXCK_FREQ, 0x1333 }, 159 { CCI_REG8(0x3c7e), 0x08 }, 160 { CCI_REG8(0x3c7f), 0x05 }, 161 { CCI_REG8(0x3e35), 0x00 }, 162 { CCI_REG8(0x3e36), 0x00 }, 163 { CCI_REG8(0x3e37), 0x00 }, 164 { CCI_REG8(0x3f7f), 0x01 }, 165 { CCI_REG8(0x4431), 0x04 }, 166 { CCI_REG8(0x531c), 0x01 }, 167 { CCI_REG8(0x531d), 0x02 }, 168 { CCI_REG8(0x531e), 0x04 }, 169 { CCI_REG8(0x5928), 0x00 }, 170 { CCI_REG8(0x5929), 0x2f }, 171 { CCI_REG8(0x592a), 0x00 }, 172 { CCI_REG8(0x592b), 0x85 }, 173 { CCI_REG8(0x592c), 0x00 }, 174 { CCI_REG8(0x592d), 0x32 }, 175 { CCI_REG8(0x592e), 0x00 }, 176 { CCI_REG8(0x592f), 0x88 }, 177 { CCI_REG8(0x5930), 0x00 }, 178 { CCI_REG8(0x5931), 0x3d }, 179 { CCI_REG8(0x5932), 0x00 }, 180 { CCI_REG8(0x5933), 0x93 }, 181 { CCI_REG8(0x5938), 0x00 }, 182 { CCI_REG8(0x5939), 0x24 }, 183 { CCI_REG8(0x593a), 0x00 }, 184 { CCI_REG8(0x593b), 0x7a }, 185 { CCI_REG8(0x593c), 0x00 }, 186 { CCI_REG8(0x593d), 0x24 }, 187 { CCI_REG8(0x593e), 0x00 }, 188 { CCI_REG8(0x593f), 0x7a }, 189 { CCI_REG8(0x5940), 0x00 }, 190 { CCI_REG8(0x5941), 0x2f }, 191 { CCI_REG8(0x5942), 0x00 }, 192 { CCI_REG8(0x5943), 0x85 }, 193 { CCI_REG8(0x5f0e), 0x6e }, 194 { CCI_REG8(0x5f11), 0xc6 }, 195 { CCI_REG8(0x5f17), 0x5e }, 196 { CCI_REG8(0x7990), 0x01 }, 197 { CCI_REG8(0x7993), 0x5d }, 198 { CCI_REG8(0x7994), 0x5d }, 199 { CCI_REG8(0x7995), 0xa1 }, 200 { CCI_REG8(0x799a), 0x01 }, 201 { CCI_REG8(0x799d), 0x00 }, 202 { CCI_REG8(0x8169), 0x01 }, 203 { CCI_REG8(0x8359), 0x01 }, 204 { CCI_REG8(0x9302), 0x1e }, 205 { CCI_REG8(0x9306), 0x1f }, 206 { CCI_REG8(0x930a), 0x26 }, 207 { CCI_REG8(0x930e), 0x23 }, 208 { CCI_REG8(0x9312), 0x23 }, 209 { CCI_REG8(0x9316), 0x2c }, 210 { CCI_REG8(0x9317), 0x19 }, 211 { CCI_REG8(0xb046), 0x01 }, 212 { CCI_REG8(0xb048), 0x01 }, 213 }; 214 215 static const struct cci_reg_sequence mode_1928x1088_regs[] = { 216 { IMX471_REG_CSI_DATA_FORMAT, IMX471_CSI_DATA_FORMAT_RAW10 }, 217 { IMX471_REG_CSI_LANE_MODE, IMX471_CSI_4_LANE_MODE }, 218 { IMX471_REG_X_ADD_STA, 8 }, 219 { IMX471_REG_Y_ADD_STA, 408 }, 220 { IMX471_REG_X_ADD_END, 4647 }, 221 { IMX471_REG_Y_ADD_END, 3051 }, 222 { IMX471_REG_X_EVEN_INC, 1 }, 223 { IMX471_REG_X_ODD_INC, 1 }, 224 { IMX471_REG_Y_EVEN_INC, 1 }, 225 { IMX471_REG_Y_ODD_INC, 1 }, 226 { IMX471_REG_BINNING_MODE, IMX471_BINNING_ENABLE }, 227 { IMX471_REG_BINNING_TYPE, 0x22 }, 228 { IMX471_REG_BINNING_WEIGHTING, 0x08 }, 229 { IMX471_REG_DIG_CROP_X_OFFSET, 208 }, 230 { IMX471_REG_DIG_CROP_Y_OFFSET, 108 }, 231 { IMX471_REG_DIG_CROP_WIDTH, 1928 }, 232 { IMX471_REG_DIG_CROP_HEIGHT, 1088 }, 233 { IMX471_REG_X_OUTPUT_SIZE, 1928 }, 234 { IMX471_REG_Y_OUTPUT_SIZE, 1088 }, 235 { IMX471_REG_VTPXCK_DIV, 0x06 }, 236 { IMX471_REG_VTSYCK_DIV, 0x02 }, 237 { IMX471_REG_PREPLLCK_VT_DIV, 0x02 }, 238 { IMX471_REG_PLL_VT_MPY, 0x0079 }, 239 { IMX471_REG_OPSYCK_DIV, 0x01 }, 240 { CCI_REG8(0x030d), 0x02 }, 241 { CCI_REG8(0x030e), 0x00 }, 242 { CCI_REG8(0x030f), 0x53 }, 243 { IMX471_REG_PLL_MULT_DRIV, IMX471_PLL_DUAL }, 244 { CCI_REG8(0x3f4c), 0x81 }, 245 { CCI_REG8(0x3f4d), 0x81 }, 246 { CCI_REG8(0x3f78), 0x01 }, 247 { CCI_REG8(0x3f79), 0x31 }, 248 { CCI_REG8(0x3ffe), 0x00 }, 249 { CCI_REG8(0x3fff), 0x8a }, 250 { CCI_REG8(0x5f0a), 0xb6 }, 251 }; 252 253 static const char * const imx471_test_pattern_menu[] = { 254 "Disabled", 255 "Solid Colour", 256 "Eight Vertical Colour Bars", 257 "Colour Bars With Fade to Grey", 258 "Pseudorandom Sequence (PN9)", 259 }; 260 261 static const s64 link_freq_menu_items[] = { 262 IMX471_LINK_FREQ_DEFAULT, 263 }; 264 265 /* 266 * The Bayer formats for the flipping. 267 * - no flip 268 * - h flip 269 * - v flip 270 * - h and v flips 271 */ 272 static const u32 imx471_hv_flips_bayer_order[] = { 273 MEDIA_BUS_FMT_SRGGB10_1X10, 274 MEDIA_BUS_FMT_SGRBG10_1X10, 275 MEDIA_BUS_FMT_SGBRG10_1X10, 276 MEDIA_BUS_FMT_SBGGR10_1X10, 277 }; 278 279 static const struct imx471_mode imx471_modes[] = { 280 { 281 .width = 1928, 282 .height = 1088, 283 .fll_def = 1308, 284 .fll_min = 1308, 285 .llp = 2328, 286 .default_mode_regs = mode_1928x1088_regs, 287 .default_mode_regs_length = ARRAY_SIZE(mode_1928x1088_regs), 288 }, 289 }; 290 291 static int imx471_get_regulators(struct device *dev, struct imx471 *sensor) 292 { 293 for (unsigned int i = 0; i < ARRAY_SIZE(imx471_supply_name); i++) 294 sensor->supplies[i].supply = imx471_supply_name[i]; 295 296 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx471_supply_name), 297 sensor->supplies); 298 } 299 300 static int imx471_set_ctrl(struct v4l2_ctrl *ctrl) 301 { 302 struct imx471 *sensor = container_of_const(ctrl->handler, 303 struct imx471, 304 ctrl_handler); 305 struct v4l2_subdev_state *state = 306 v4l2_subdev_get_locked_active_state(&sensor->sd); 307 const struct v4l2_mbus_framefmt *format = 308 v4l2_subdev_state_get_format(state, 0); 309 int ret; 310 311 if (ctrl->id == V4L2_CID_VBLANK) { 312 s64 exposure_max = format->height + ctrl->val - 313 IMX471_EXPOSURE_MARGIN; 314 ret = __v4l2_ctrl_modify_range(sensor->exposure, 315 sensor->exposure->minimum, 316 exposure_max, 317 sensor->exposure->step, 318 exposure_max); 319 if (ret) 320 return ret; 321 } 322 323 if (!pm_runtime_get_if_in_use(sensor->dev)) 324 return 0; 325 326 switch (ctrl->id) { 327 case V4L2_CID_ANALOGUE_GAIN: 328 ret = cci_write(sensor->regmap, IMX471_REG_ANALOG_GAIN, 329 ctrl->val, NULL); 330 break; 331 case V4L2_CID_DIGITAL_GAIN: 332 ret = cci_write(sensor->regmap, IMX471_REG_DIG_GAIN_GLOBAL, 333 ctrl->val, NULL); 334 break; 335 case V4L2_CID_EXPOSURE: 336 ret = cci_write(sensor->regmap, IMX471_REG_EXPOSURE, 337 ctrl->val, NULL); 338 break; 339 case V4L2_CID_VBLANK: 340 /* Update FLL that meets expected vertical blanking */ 341 ret = cci_write(sensor->regmap, IMX471_REG_FLL, 342 format->height + ctrl->val, NULL); 343 break; 344 case V4L2_CID_TEST_PATTERN: 345 ret = cci_write(sensor->regmap, IMX471_REG_TEST_PATTERN, 346 ctrl->val, NULL); 347 break; 348 case V4L2_CID_HFLIP: 349 case V4L2_CID_VFLIP: 350 ret = cci_write(sensor->regmap, IMX471_REG_ORIENTATION, 351 sensor->hflip->val | sensor->vflip->val << 1, 352 NULL); 353 break; 354 default: 355 ret = -EINVAL; 356 dev_err(sensor->dev, "ctrl(id:0x%x,val:0x%x) is not handled\n", 357 ctrl->id, ctrl->val); 358 break; 359 } 360 361 pm_runtime_put(sensor->dev); 362 363 return ret; 364 } 365 366 static const struct v4l2_ctrl_ops imx471_ctrl_ops = { 367 .s_ctrl = imx471_set_ctrl, 368 }; 369 370 static u32 imx471_get_format_code(struct imx471 *sensor) 371 { 372 unsigned int i; 373 374 i = (sensor->vflip->val ? 2 : 0) | (sensor->hflip->val ? 1 : 0); 375 376 return imx471_hv_flips_bayer_order[i]; 377 } 378 379 static int imx471_enum_mbus_code(struct v4l2_subdev *sd, 380 struct v4l2_subdev_state *sd_state, 381 struct v4l2_subdev_mbus_code_enum *code) 382 { 383 struct imx471 *sensor = to_imx471(sd); 384 385 if (code->index >= (ARRAY_SIZE(imx471_hv_flips_bayer_order) / 4)) 386 return -EINVAL; 387 388 code->code = imx471_get_format_code(sensor); 389 390 return 0; 391 } 392 393 static int imx471_enum_frame_size(struct v4l2_subdev *sd, 394 struct v4l2_subdev_state *sd_state, 395 struct v4l2_subdev_frame_size_enum *fse) 396 { 397 if (fse->index >= ARRAY_SIZE(imx471_modes)) 398 return -EINVAL; 399 400 fse->min_width = imx471_modes[fse->index].width; 401 fse->max_width = fse->min_width; 402 fse->min_height = imx471_modes[fse->index].height; 403 fse->max_height = fse->min_height; 404 405 return 0; 406 } 407 408 static void imx471_update_pad_format(struct imx471 *sensor, 409 const struct imx471_mode *mode, 410 struct v4l2_subdev_format *fmt) 411 { 412 fmt->format.code = imx471_get_format_code(sensor); 413 fmt->format.width = mode->width; 414 fmt->format.height = mode->height; 415 fmt->format.field = V4L2_FIELD_NONE; 416 } 417 418 static int imx471_set_pad_format(struct v4l2_subdev *sd, 419 struct v4l2_subdev_state *sd_state, 420 struct v4l2_subdev_format *fmt) 421 { 422 struct imx471 *sensor = to_imx471(sd); 423 const struct imx471_mode *mode; 424 int h_blank, ret; 425 426 mode = v4l2_find_nearest_size(imx471_modes, ARRAY_SIZE(imx471_modes), 427 width, height, fmt->format.width, 428 fmt->format.height); 429 430 imx471_update_pad_format(sensor, mode, fmt); 431 432 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 433 434 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 435 return 0; 436 437 if (media_entity_is_streaming(&sensor->sd.entity)) 438 return -EBUSY; 439 440 ret = __v4l2_ctrl_modify_range(sensor->vblank, 441 mode->fll_min - mode->height, 442 IMX471_FLL_MAX - mode->height, 443 1, 444 mode->fll_def - mode->height); 445 if (ret) 446 return ret; 447 448 h_blank = mode->llp - mode->width; 449 /* 450 * Currently hblank is not changeable. 451 * So FPS control is done only by vblank. 452 */ 453 return __v4l2_ctrl_modify_range(sensor->hblank, h_blank, 454 h_blank, 1, h_blank); 455 } 456 457 static int imx471_get_selection(struct v4l2_subdev *sd, 458 struct v4l2_subdev_state *sd_state, 459 struct v4l2_subdev_selection *sel) 460 { 461 switch (sel->target) { 462 case V4L2_SEL_TGT_CROP: 463 sel->r = *v4l2_subdev_state_get_crop(sd_state, sel->pad); 464 break; 465 466 case V4L2_SEL_TGT_NATIVE_SIZE: 467 sel->r.top = 0; 468 sel->r.left = 0; 469 sel->r.width = IMX471_NATIVE_WIDTH; 470 sel->r.height = IMX471_NATIVE_HEIGHT; 471 return 0; 472 473 case V4L2_SEL_TGT_CROP_DEFAULT: 474 case V4L2_SEL_TGT_CROP_BOUNDS: 475 sel->r.top = IMX471_PIXEL_ARRAY_TOP; 476 sel->r.left = IMX471_PIXEL_ARRAY_LEFT; 477 sel->r.width = IMX471_PIXEL_ARRAY_WIDTH; 478 sel->r.height = IMX471_PIXEL_ARRAY_HEIGHT; 479 return 0; 480 } 481 482 return -EINVAL; 483 } 484 485 static int imx471_init_state(struct v4l2_subdev *sd, 486 struct v4l2_subdev_state *sd_state) 487 { 488 struct v4l2_subdev_format fmt = { 489 .which = V4L2_SUBDEV_FORMAT_TRY, 490 .format = { 491 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 492 .width = imx471_modes[0].width, 493 .height = imx471_modes[0].height, 494 }, 495 }; 496 497 return imx471_set_pad_format(sd, sd_state, &fmt); 498 } 499 500 static int imx471_identify_module(struct imx471 *sensor) 501 { 502 int ret; 503 u64 val; 504 505 ret = cci_read(sensor->regmap, IMX471_REG_CHIP_ID, &val, NULL); 506 if (ret) 507 return dev_err_probe(sensor->dev, ret, 508 "failed to read chip id\n"); 509 510 if (val != IMX471_CHIP_ID) 511 return dev_err_probe(sensor->dev, -EIO, 512 "chip id mismatch: %x!=%llx\n", 513 IMX471_CHIP_ID, val); 514 515 return 0; 516 } 517 518 static int imx471_power_off(struct device *dev) 519 { 520 struct v4l2_subdev *sd = dev_get_drvdata(dev); 521 struct imx471 *sensor = to_imx471(sd); 522 523 clk_disable_unprepare(sensor->img_clk); 524 gpiod_set_value_cansleep(sensor->reset_gpio, 1); 525 526 regulator_bulk_disable(ARRAY_SIZE(imx471_supply_name), 527 sensor->supplies); 528 529 return 0; 530 } 531 532 static int imx471_power_on(struct device *dev) 533 { 534 struct v4l2_subdev *sd = dev_get_drvdata(dev); 535 struct imx471 *sensor = to_imx471(sd); 536 int ret; 537 538 ret = regulator_bulk_enable(ARRAY_SIZE(imx471_supply_name), 539 sensor->supplies); 540 if (ret < 0) { 541 dev_err(dev, "failed to enable regulators: %d\n", ret); 542 return ret; 543 } 544 545 ret = clk_prepare_enable(sensor->img_clk); 546 if (ret < 0) { 547 regulator_bulk_disable(ARRAY_SIZE(imx471_supply_name), 548 sensor->supplies); 549 dev_err(dev, "failed to enable imaging clock: %d\n", ret); 550 return ret; 551 } 552 553 gpiod_set_value_cansleep(sensor->reset_gpio, 0); 554 555 usleep_range(10000, 15000); 556 557 return 0; 558 } 559 560 static int imx471_enable_stream(struct v4l2_subdev *sd, 561 struct v4l2_subdev_state *state, 562 u32 pad, u64 streams_mask) 563 { 564 struct imx471 *sensor = to_imx471(sd); 565 const struct imx471_mode *mode; 566 struct v4l2_mbus_framefmt *fmt; 567 int ret; 568 569 ret = pm_runtime_resume_and_get(sensor->dev); 570 if (ret) 571 return ret; 572 573 ret = imx471_identify_module(sensor); 574 if (ret) 575 goto error_powerdown; 576 577 ret = cci_multi_reg_write(sensor->regmap, imx471_global_regs, 578 ARRAY_SIZE(imx471_global_regs), NULL); 579 if (ret) { 580 dev_err(sensor->dev, "failed to set global settings: %d\n", 581 ret); 582 goto error_powerdown; 583 } 584 585 fmt = v4l2_subdev_state_get_format(state, 0); 586 mode = v4l2_find_nearest_size(imx471_modes, ARRAY_SIZE(imx471_modes), 587 width, height, fmt->width, fmt->height); 588 589 ret = cci_multi_reg_write(sensor->regmap, mode->default_mode_regs, 590 mode->default_mode_regs_length, NULL); 591 if (ret) { 592 dev_err(sensor->dev, "failed to set mode: %d\n", ret); 593 goto error_powerdown; 594 } 595 596 ret = cci_write(sensor->regmap, IMX471_REG_DPGA_USE_GLOBAL_GAIN, 1, 597 NULL); 598 if (ret) 599 goto error_powerdown; 600 601 ret = __v4l2_ctrl_handler_setup(&sensor->ctrl_handler); 602 if (ret) 603 goto error_powerdown; 604 605 ret = cci_write(sensor->regmap, IMX471_REG_MODE_SELECT, 606 IMX471_MODE_STREAMING, NULL); 607 if (ret) 608 goto error_powerdown; 609 610 __v4l2_ctrl_grab(sensor->vflip, true); 611 __v4l2_ctrl_grab(sensor->hflip, true); 612 613 return ret; 614 615 error_powerdown: 616 pm_runtime_put(sensor->dev); 617 618 return ret; 619 } 620 621 static int imx471_disable_stream(struct v4l2_subdev *sd, 622 struct v4l2_subdev_state *state, 623 u32 pad, u64 streams_mask) 624 { 625 struct imx471 *sensor = to_imx471(sd); 626 int ret; 627 628 ret = cci_write(sensor->regmap, IMX471_REG_MODE_SELECT, 629 IMX471_MODE_STANDBY, NULL); 630 pm_runtime_put(sensor->dev); 631 632 if (ret) 633 dev_err(sensor->dev, 634 "failed to disable stream with return value: %d\n", 635 ret); 636 637 __v4l2_ctrl_grab(sensor->vflip, false); 638 __v4l2_ctrl_grab(sensor->hflip, false); 639 640 return 0; 641 } 642 643 static const struct v4l2_subdev_video_ops imx471_video_ops = { 644 .s_stream = v4l2_subdev_s_stream_helper, 645 }; 646 647 static const struct v4l2_subdev_pad_ops imx471_pad_ops = { 648 .enum_mbus_code = imx471_enum_mbus_code, 649 .get_fmt = v4l2_subdev_get_fmt, 650 .set_fmt = imx471_set_pad_format, 651 .get_selection = imx471_get_selection, 652 .enum_frame_size = imx471_enum_frame_size, 653 .enable_streams = imx471_enable_stream, 654 .disable_streams = imx471_disable_stream, 655 }; 656 657 static const struct v4l2_subdev_ops imx471_subdev_ops = { 658 .video = &imx471_video_ops, 659 .pad = &imx471_pad_ops, 660 }; 661 662 static const struct v4l2_subdev_internal_ops imx471_internal_ops = { 663 .init_state = imx471_init_state, 664 }; 665 666 static int imx471_init_controls(struct imx471 *sensor) 667 { 668 const struct imx471_mode *mode = &imx471_modes[0]; 669 struct v4l2_fwnode_device_properties props; 670 struct v4l2_ctrl_handler *ctrl_hdlr; 671 struct v4l2_ctrl *link_freq; 672 s64 exposure_max, hblank; 673 u64 pixel_rate; 674 int ret; 675 676 ret = v4l2_fwnode_device_parse(sensor->dev, &props); 677 if (ret) { 678 dev_err(sensor->dev, "failed to parse fwnode: %d\n", ret); 679 return ret; 680 } 681 682 ctrl_hdlr = &sensor->ctrl_handler; 683 v4l2_ctrl_handler_init(ctrl_hdlr, 12); 684 685 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx471_ctrl_ops, &props); 686 687 link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 688 &imx471_ctrl_ops, 689 V4L2_CID_LINK_FREQ, 690 ARRAY_SIZE(link_freq_menu_items) - 1, 691 0, 692 link_freq_menu_items); 693 694 /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 695 pixel_rate = div_u64(IMX471_LINK_FREQ_DEFAULT * 2 * 4, 10); 696 697 v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, 698 V4L2_CID_PIXEL_RATE, pixel_rate, 699 pixel_rate, 1, pixel_rate); 700 701 sensor->vblank = v4l2_ctrl_new_std(ctrl_hdlr, 702 &imx471_ctrl_ops, 703 V4L2_CID_VBLANK, 704 mode->fll_min - mode->height, 705 IMX471_FLL_MAX - mode->height, 706 1, 707 mode->fll_def - mode->height); 708 709 hblank = mode->llp - mode->width; 710 sensor->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, 711 V4L2_CID_HBLANK, hblank, hblank, 712 1, hblank); 713 714 /* fll >= exposure time + adjust parameter (default value is 18) */ 715 exposure_max = mode->fll_def - IMX471_EXPOSURE_MARGIN; 716 sensor->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, 717 V4L2_CID_EXPOSURE, 718 IMX471_EXPOSURE_MIN, exposure_max, 719 IMX471_EXPOSURE_STEP, 720 IMX471_EXPOSURE_DEFAULT); 721 722 v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 723 IMX471_ANA_GAIN_MIN, IMX471_ANA_GAIN_MAX, 724 IMX471_ANA_GAIN_STEP, IMX471_ANA_GAIN_DEFAULT); 725 726 v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 727 IMX471_DGTL_GAIN_MIN, IMX471_DGTL_GAIN_MAX, 728 IMX471_DGTL_GAIN_STEP, IMX471_DGTL_GAIN_DEFAULT); 729 730 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx471_ctrl_ops, 731 V4L2_CID_TEST_PATTERN, 732 ARRAY_SIZE(imx471_test_pattern_menu) - 1, 733 0, 0, imx471_test_pattern_menu); 734 735 sensor->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, 736 V4L2_CID_HFLIP, 0, 1, 1, 0); 737 738 sensor->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops, 739 V4L2_CID_VFLIP, 0, 1, 1, 0); 740 741 if (ctrl_hdlr->error) { 742 dev_err(sensor->dev, "%s control init failed: %d\n", 743 __func__, ctrl_hdlr->error); 744 goto error; 745 } 746 747 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 748 sensor->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 749 sensor->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 750 sensor->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 751 752 sensor->sd.ctrl_handler = ctrl_hdlr; 753 754 return 0; 755 756 error: 757 v4l2_ctrl_handler_free(ctrl_hdlr); 758 759 return ctrl_hdlr->error; 760 } 761 762 static int imx471_check_hwcfg(struct imx471 *sensor) 763 { 764 struct v4l2_fwnode_endpoint bus_cfg = { 765 .bus_type = V4L2_MBUS_CSI2_DPHY, 766 }; 767 struct fwnode_handle *ep, *fwnode = dev_fwnode(sensor->dev); 768 unsigned long link_freq_bitmap; 769 struct clk *clk; 770 int ret; 771 772 clk = devm_v4l2_sensor_clk_get(sensor->dev, NULL); 773 if (IS_ERR(clk)) 774 return dev_err_probe(sensor->dev, PTR_ERR(clk), 775 "can't get clock frequency\n"); 776 777 if (clk_get_rate(clk) != IMX471_EXT_CLK) 778 return dev_err_probe(sensor->dev, -EINVAL, 779 "external clock %lu is not supported\n", 780 clk_get_rate(clk)); 781 782 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0); 783 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 784 fwnode_handle_put(ep); 785 if (ret) 786 return dev_err_probe(sensor->dev, ret, 787 "parsing endpoint failed\n"); 788 789 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) { 790 ret = dev_err_probe(sensor->dev, -EINVAL, 791 "number of CSI2 data lanes %u is not supported\n", 792 bus_cfg.bus.mipi_csi2.num_data_lanes); 793 goto done_endpoint_free; 794 } 795 796 ret = v4l2_link_freq_to_bitmap(sensor->dev, bus_cfg.link_frequencies, 797 bus_cfg.nr_of_link_frequencies, 798 link_freq_menu_items, 799 ARRAY_SIZE(link_freq_menu_items), 800 &link_freq_bitmap); 801 802 done_endpoint_free: 803 v4l2_fwnode_endpoint_free(&bus_cfg); 804 805 return ret; 806 } 807 808 static int imx471_probe(struct i2c_client *client) 809 { 810 struct imx471 *sensor; 811 int ret; 812 813 sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL); 814 if (!sensor) 815 return dev_err_probe(&client->dev, -ENOMEM, 816 "failed to allocate memory\n"); 817 818 sensor->dev = &client->dev; 819 820 ret = imx471_check_hwcfg(sensor); 821 if (ret) 822 return dev_err_probe(sensor->dev, ret, 823 "failed to check hwcfg: %d\n", ret); 824 825 ret = imx471_get_regulators(sensor->dev, sensor); 826 if (ret) 827 return dev_err_probe(sensor->dev, ret, 828 "failed to get regulators\n"); 829 830 sensor->reset_gpio = devm_gpiod_get_optional(sensor->dev, "reset", 831 GPIOD_OUT_HIGH); 832 if (IS_ERR(sensor->reset_gpio)) 833 return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset_gpio), 834 "failed to get reset gpio\n"); 835 836 sensor->img_clk = devm_v4l2_sensor_clk_get(sensor->dev, NULL); 837 if (IS_ERR(sensor->img_clk)) 838 return dev_err_probe(sensor->dev, PTR_ERR(sensor->img_clk), 839 "failed to get imaging clock\n"); 840 841 v4l2_i2c_subdev_init(&sensor->sd, client, &imx471_subdev_ops); 842 843 sensor->regmap = devm_cci_regmap_init_i2c(client, 16); 844 if (IS_ERR(sensor->regmap)) 845 return dev_err_probe(sensor->dev, PTR_ERR(sensor->regmap), 846 "failed to initialize CCI\n"); 847 848 ret = imx471_power_on(sensor->dev); 849 if (ret) 850 return dev_err_probe(sensor->dev, ret, 851 "failed to power on\n"); 852 853 ret = imx471_identify_module(sensor); 854 if (ret) { 855 dev_err_probe(sensor->dev, ret, "failed to find sensor: %d\n", 856 ret); 857 goto error_power_off; 858 } 859 860 ret = imx471_init_controls(sensor); 861 if (ret) { 862 dev_err_probe(sensor->dev, ret, "failed to init controls: %d\n", 863 ret); 864 goto error_power_off; 865 } 866 867 sensor->sd.internal_ops = &imx471_internal_ops; 868 sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 869 sensor->pad.flags = MEDIA_PAD_FL_SOURCE; 870 sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 871 872 ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad); 873 if (ret) { 874 dev_err_probe(sensor->dev, ret, 875 "failed to init entity pads: %d\n", ret); 876 goto error_v4l2_ctrl_handler_free; 877 } 878 879 sensor->sd.state_lock = sensor->ctrl_handler.lock; 880 ret = v4l2_subdev_init_finalize(&sensor->sd); 881 if (ret < 0) { 882 dev_err_probe(sensor->dev, ret, "failed to init subdev: %d\n", 883 ret); 884 goto error_media_entity_pm; 885 } 886 887 pm_runtime_set_active(sensor->dev); 888 pm_runtime_enable(sensor->dev); 889 890 ret = v4l2_async_register_subdev_sensor(&sensor->sd); 891 if (ret < 0) 892 goto error_v4l2_subdev_cleanup; 893 894 pm_runtime_idle(sensor->dev); 895 896 return 0; 897 898 error_v4l2_subdev_cleanup: 899 pm_runtime_disable(sensor->dev); 900 pm_runtime_set_suspended(sensor->dev); 901 v4l2_subdev_cleanup(&sensor->sd); 902 903 error_media_entity_pm: 904 media_entity_cleanup(&sensor->sd.entity); 905 906 error_v4l2_ctrl_handler_free: 907 v4l2_ctrl_handler_free(sensor->sd.ctrl_handler); 908 909 error_power_off: 910 imx471_power_off(sensor->dev); 911 912 return ret; 913 } 914 915 static void imx471_remove(struct i2c_client *client) 916 { 917 struct v4l2_subdev *sd = i2c_get_clientdata(client); 918 919 v4l2_async_unregister_subdev(sd); 920 v4l2_subdev_cleanup(sd); 921 media_entity_cleanup(&sd->entity); 922 v4l2_ctrl_handler_free(sd->ctrl_handler); 923 924 pm_runtime_disable(&client->dev); 925 926 if (!pm_runtime_status_suspended(&client->dev)) { 927 imx471_power_off(&client->dev); 928 pm_runtime_set_suspended(&client->dev); 929 } 930 } 931 932 static DEFINE_RUNTIME_DEV_PM_OPS(imx471_pm_ops, imx471_power_off, 933 imx471_power_on, NULL); 934 935 static const struct acpi_device_id imx471_acpi_ids[] __maybe_unused = { 936 { "SONY471A" }, 937 { "TBE20A0" }, 938 { /* sentinel */ } 939 }; 940 MODULE_DEVICE_TABLE(acpi, imx471_acpi_ids); 941 942 static struct i2c_driver imx471_i2c_driver = { 943 .driver = { 944 .name = "imx471", 945 .acpi_match_table = ACPI_PTR(imx471_acpi_ids), 946 .pm = pm_sleep_ptr(&imx471_pm_ops), 947 }, 948 .probe = imx471_probe, 949 .remove = imx471_remove, 950 }; 951 module_i2c_driver(imx471_i2c_driver); 952 953 MODULE_AUTHOR("Jimmy Su <jimmy.su@intel.com>"); 954 MODULE_AUTHOR("Serin Yeh <serin.yeh@intel.com>"); 955 MODULE_AUTHOR("Kate Hsuan <hpa@redhat.com>"); 956 MODULE_DESCRIPTION("Sony imx471 sensor driver"); 957 MODULE_LICENSE("GPL"); 958