1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig MAILBOX 3 bool "Mailbox Hardware Support" 4 help 5 Mailbox is a framework to control hardware communication between 6 on-chip processors through queued messages and interrupt driven 7 signals. Say Y if your platform supports hardware mailboxes. 8 9if MAILBOX 10 11config ARM_MHU 12 tristate "ARM MHU Mailbox" 13 depends on ARM_AMBA 14 help 15 Say Y here if you want to build the ARM MHU controller driver. 16 The controller has 3 mailbox channels, the last of which can be 17 used in Secure mode only. 18 19config ARM_MHU_V2 20 tristate "ARM MHUv2 Mailbox" 21 depends on ARM_AMBA 22 help 23 Say Y here if you want to build the ARM MHUv2 controller driver, 24 which provides unidirectional mailboxes between processing elements. 25 26config IMX_MBOX 27 tristate "i.MX Mailbox" 28 depends on ARCH_MXC || COMPILE_TEST 29 help 30 Mailbox implementation for i.MX Messaging Unit (MU). 31 32config PLATFORM_MHU 33 tristate "Platform MHU Mailbox" 34 depends on OF 35 depends on HAS_IOMEM 36 help 37 Say Y here if you want to build a platform specific variant MHU 38 controller driver. 39 The controller has a maximum of 3 mailbox channels, the last of 40 which can be used in Secure mode only. 41 42config PL320_MBOX 43 bool "ARM PL320 Mailbox" 44 depends on ARM_AMBA 45 help 46 An implementation of the ARM PL320 Interprocessor Communication 47 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to 48 send short messages between Highbank's A9 cores and the EnergyCore 49 Management Engine, primarily for cpufreq. Say Y here if you want 50 to use the PL320 IPCM support. 51 52config ARMADA_37XX_RWTM_MBOX 53 tristate "Armada 37xx rWTM BIU Mailbox" 54 depends on ARCH_MVEBU || COMPILE_TEST 55 depends on OF 56 help 57 Mailbox implementation for communication with the the firmware 58 running on the Cortex-M3 rWTM secure processor of the Armada 37xx 59 SOC. Say Y here if you are building for such a device (for example 60 the Turris Mox router). 61 62config OMAP2PLUS_MBOX 63 tristate "OMAP2+ Mailbox framework support" 64 depends on ARCH_OMAP2PLUS || ARCH_K3 65 help 66 Mailbox implementation for OMAP family chips with hardware for 67 interprocessor communication involving DSP, IVA1.0 and IVA2 in 68 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you 69 want to use OMAP2+ Mailbox framework support. 70 71config OMAP_MBOX_KFIFO_SIZE 72 int "Mailbox kfifo default buffer size (bytes)" 73 depends on OMAP2PLUS_MBOX 74 default 256 75 help 76 Specify the default size of mailbox's kfifo buffers (bytes). 77 This can also be changed at runtime (via the mbox_kfifo_size 78 module parameter). 79 80config ROCKCHIP_MBOX 81 bool "Rockchip Soc Integrated Mailbox Support" 82 depends on ARCH_ROCKCHIP || COMPILE_TEST 83 help 84 This driver provides support for inter-processor communication 85 between CPU cores and MCU processor on Some Rockchip SOCs. 86 Please check it that the Soc you use have Mailbox hardware. 87 Say Y here if you want to use the Rockchip Mailbox support. 88 89config PCC 90 bool "Platform Communication Channel Driver" 91 depends on ACPI 92 default n 93 help 94 ACPI 5.0+ spec defines a generic mode of communication 95 between the OS and a platform such as the BMC. This medium 96 (PCC) is typically used by CPPC (ACPI CPU Performance management), 97 RAS (ACPI reliability protocol) and MPST (ACPI Memory power 98 states). Select this driver if your platform implements the 99 PCC clients mentioned above. 100 101config ALTERA_MBOX 102 tristate "Altera Mailbox" 103 depends on HAS_IOMEM 104 help 105 An implementation of the Altera Mailbox soft core. It is used 106 to send message between processors. Say Y here if you want to use the 107 Altera mailbox support. 108 109config BCM2835_MBOX 110 tristate "BCM2835 Mailbox" 111 depends on ARCH_BCM2835 112 help 113 An implementation of the BCM2385 Mailbox. It is used to invoke 114 the services of the Videocore. Say Y here if you want to use the 115 BCM2835 Mailbox. 116 117config STI_MBOX 118 tristate "STI Mailbox framework support" 119 depends on ARCH_STI && OF 120 help 121 Mailbox implementation for STMicroelectonics family chips with 122 hardware for interprocessor communication. 123 124config TI_MESSAGE_MANAGER 125 tristate "Texas Instruments Message Manager Driver" 126 depends on ARCH_KEYSTONE || ARCH_K3 127 default ARCH_K3 128 help 129 An implementation of Message Manager slave driver for Keystone 130 and K3 architecture SoCs from Texas Instruments. Message Manager 131 is a communication entity found on few of Texas Instrument's keystone 132 and K3 architecture SoCs. These may be used for communication between 133 multiple processors within the SoC. Select this driver if your 134 platform has support for the hardware block. 135 136config HI3660_MBOX 137 tristate "Hi3660 Mailbox" if EXPERT 138 depends on (ARCH_HISI || COMPILE_TEST) 139 depends on OF 140 default ARCH_HISI 141 help 142 An implementation of the hi3660 mailbox. It is used to send message 143 between application processors and other processors/MCU/DSP. Select 144 Y here if you want to use Hi3660 mailbox controller. 145 146config HI6220_MBOX 147 tristate "Hi6220 Mailbox" if EXPERT 148 depends on (ARCH_HISI || COMPILE_TEST) 149 depends on OF 150 default ARCH_HISI 151 help 152 An implementation of the hi6220 mailbox. It is used to send message 153 between application processors and MCU. Say Y here if you want to 154 build Hi6220 mailbox controller driver. 155 156config MAILBOX_TEST 157 tristate "Mailbox Test Client" 158 depends on OF 159 depends on HAS_IOMEM 160 help 161 Test client to help with testing new Controller driver 162 implementations. 163 164config POLARFIRE_SOC_MAILBOX 165 tristate "PolarFire SoC (MPFS) Mailbox" 166 depends on HAS_IOMEM 167 depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST 168 help 169 This driver adds support for the PolarFire SoC (MPFS) mailbox controller. 170 171 To compile this driver as a module, choose M here. the 172 module will be called mailbox-mpfs. 173 174 If unsure, say N. 175 176config QCOM_APCS_IPC 177 tristate "Qualcomm APCS IPC driver" 178 depends on ARCH_QCOM || COMPILE_TEST 179 help 180 Say y here to enable support for the APCS IPC mailbox driver, 181 providing an interface for invoking the inter-process communication 182 signals from the application processor to other masters. 183 184config TEGRA_HSP_MBOX 185 bool "Tegra HSP (Hardware Synchronization Primitives) Driver" 186 depends on ARCH_TEGRA 187 help 188 The Tegra HSP driver is used for the interprocessor communication 189 between different remote processors and host processors on Tegra186 190 and later SoCs. Say Y here if you want to have this support. 191 If unsure say N. 192 193config XGENE_SLIMPRO_MBOX 194 tristate "APM SoC X-Gene SLIMpro Mailbox Controller" 195 depends on ARCH_XGENE 196 help 197 An implementation of the APM X-Gene Interprocessor Communication 198 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller. 199 It is used to send short messages between ARM64-bit cores and 200 the SLIMpro Management Engine, primarily for PM. Say Y here if you 201 want to use the APM X-Gene SLIMpro IPCM support. 202 203config BCM_PDC_MBOX 204 tristate "Broadcom FlexSparx DMA Mailbox" 205 depends on ARCH_BCM_IPROC || COMPILE_TEST 206 help 207 Mailbox implementation for the Broadcom FlexSparx DMA ring manager, 208 which provides access to various offload engines on Broadcom 209 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2. 210 211config BCM_FLEXRM_MBOX 212 tristate "Broadcom FlexRM Mailbox" 213 depends on ARM64 214 depends on ARCH_BCM_IPROC || COMPILE_TEST 215 select GENERIC_MSI_IRQ 216 default m if ARCH_BCM_IPROC 217 help 218 Mailbox implementation of the Broadcom FlexRM ring manager, 219 which provides access to various offload engines on Broadcom 220 SoCs. Say Y here if you want to use the Broadcom FlexRM. 221 222config STM32_IPCC 223 tristate "STM32 IPCC Mailbox" 224 depends on MACH_STM32MP157 || COMPILE_TEST 225 help 226 Mailbox implementation for STMicroelectonics STM32 family chips 227 with hardware for Inter-Processor Communication Controller (IPCC) 228 between processors. Say Y here if you want to have this support. 229 230config MTK_ADSP_MBOX 231 tristate "MediaTek ADSP Mailbox Controller" 232 depends on ARCH_MEDIATEK || COMPILE_TEST 233 help 234 Say yes here to add support for "MediaTek ADSP Mailbox Controller. 235 This mailbox driver is used to send notification or short message 236 between processors with ADSP. It will place the message to share 237 buffer and will access the ipc control. 238 239config MTK_CMDQ_MBOX 240 tristate "MediaTek CMDQ Mailbox Support" 241 depends on ARCH_MEDIATEK || COMPILE_TEST 242 select MTK_INFRACFG 243 help 244 Say yes here to add support for the MediaTek Command Queue (CMDQ) 245 mailbox driver. The CMDQ is used to help read/write registers with 246 critical time limitation, such as updating display configuration 247 during the vblank. 248 249config ZYNQMP_IPI_MBOX 250 tristate "Xilinx ZynqMP IPI Mailbox" 251 depends on ARCH_ZYNQMP && OF 252 help 253 Say yes here to add support for Xilinx IPI mailbox driver. 254 This mailbox driver is used to send notification or short message 255 between processors with Xilinx ZynqMP IPI. It will place the 256 message to the IPI buffer and will access the IPI control 257 registers to kick the other processor or enquire status. 258 259config SUN6I_MSGBOX 260 tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box" 261 depends on ARCH_SUNXI || COMPILE_TEST 262 default ARCH_SUNXI 263 help 264 Mailbox implementation for the hardware message box present in 265 various Allwinner SoCs. This mailbox is used for communication 266 between the application CPUs and the power management coprocessor. 267 268config SPRD_MBOX 269 tristate "Spreadtrum Mailbox" 270 depends on ARCH_SPRD || COMPILE_TEST 271 help 272 Mailbox driver implementation for the Spreadtrum platform. It is used 273 to send message between application processors and MCU. Say Y here if 274 you want to build the Spreatrum mailbox controller driver. 275 276config QCOM_IPCC 277 tristate "Qualcomm Technologies, Inc. IPCC driver" 278 depends on ARCH_QCOM || COMPILE_TEST 279 help 280 Qualcomm Technologies, Inc. Inter-Processor Communication Controller 281 (IPCC) driver for MSM devices. The driver provides mailbox support for 282 sending interrupts to the clients. On the other hand, the driver also 283 acts as an interrupt controller for receiving interrupts from clients. 284 Say Y here if you want to build this driver. 285 286endif 287