130058677SRob Herringmenuconfig MAILBOX 230058677SRob Herring bool "Mailbox Hardware Support" 330058677SRob Herring help 430058677SRob Herring Mailbox is a framework to control hardware communication between 530058677SRob Herring on-chip processors through queued messages and interrupt driven 630058677SRob Herring signals. Say Y if your platform supports hardware mailboxes. 730058677SRob Herring 830058677SRob Herringif MAILBOX 930058677SRob Herringconfig PL320_MBOX 1030058677SRob Herring bool "ARM PL320 Mailbox" 1130058677SRob Herring depends on ARM_AMBA 1230058677SRob Herring help 1330058677SRob Herring An implementation of the ARM PL320 Interprocessor Communication 1430058677SRob Herring Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to 1530058677SRob Herring send short messages between Highbank's A9 cores and the EnergyCore 1630058677SRob Herring Management Engine, primarily for cpufreq. Say Y here if you want 1730058677SRob Herring to use the PL320 IPCM support. 1830058677SRob Herring 19c869c75cSSuman Annaconfig OMAP2PLUS_MBOX 20c869c75cSSuman Anna tristate "OMAP2+ Mailbox framework support" 21c869c75cSSuman Anna depends on ARCH_OMAP2PLUS 22c869c75cSSuman Anna help 23c869c75cSSuman Anna Mailbox implementation for OMAP family chips with hardware for 24c869c75cSSuman Anna interprocessor communication involving DSP, IVA1.0 and IVA2 in 25c869c75cSSuman Anna OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you 26c869c75cSSuman Anna want to use OMAP2+ Mailbox framework support. 27c869c75cSSuman Anna 28c869c75cSSuman Annaconfig OMAP_MBOX_KFIFO_SIZE 29c869c75cSSuman Anna int "Mailbox kfifo default buffer size (bytes)" 3079859094SSuman Anna depends on OMAP2PLUS_MBOX 31c869c75cSSuman Anna default 256 32c869c75cSSuman Anna help 33c869c75cSSuman Anna Specify the default size of mailbox's kfifo buffers (bytes). 34c869c75cSSuman Anna This can also be changed at runtime (via the mbox_kfifo_size 35c869c75cSSuman Anna module parameter). 36*86c22f8cSAshwin Chaugule 37*86c22f8cSAshwin Chauguleconfig PCC 38*86c22f8cSAshwin Chaugule bool "Platform Communication Channel Driver" 39*86c22f8cSAshwin Chaugule depends on ACPI 40*86c22f8cSAshwin Chaugule help 41*86c22f8cSAshwin Chaugule ACPI 5.0+ spec defines a generic mode of communication 42*86c22f8cSAshwin Chaugule between the OS and a platform such as the BMC. This medium 43*86c22f8cSAshwin Chaugule (PCC) is typically used by CPPC (ACPI CPU Performance management), 44*86c22f8cSAshwin Chaugule RAS (ACPI reliability protocol) and MPST (ACPI Memory power 45*86c22f8cSAshwin Chaugule states). Select this driver if your platform implements the 46*86c22f8cSAshwin Chaugule PCC clients mentioned above. 47*86c22f8cSAshwin Chaugule 4830058677SRob Herringendif 49