1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 18config ARM_GIC_MAX_NR 19 int 20 depends on ARM_GIC 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 38 39config ARM_GIC_V3_ITS 40 bool 41 select GENERIC_MSI_IRQ_DOMAIN 42 default ARM_GIC_V3 43 44config ARM_GIC_V3_ITS_PCI 45 bool 46 depends on ARM_GIC_V3_ITS 47 depends on PCI 48 depends on PCI_MSI 49 default ARM_GIC_V3_ITS 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF || COMPILE_TEST 90 select GENERIC_IRQ_CHIP 91 select IRQ_DOMAIN 92 help 93 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 94 95config ATMEL_AIC_IRQ 96 bool 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 select SPARSE_IRQ 100 101config ATMEL_AIC5_IRQ 102 bool 103 select GENERIC_IRQ_CHIP 104 select IRQ_DOMAIN 105 select SPARSE_IRQ 106 107config I8259 108 bool 109 select IRQ_DOMAIN 110 111config BCM6345_L1_IRQ 112 bool 113 select GENERIC_IRQ_CHIP 114 select IRQ_DOMAIN 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 116 117config BCM7038_L1_IRQ 118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 119 depends on ARCH_BRCMSTB || BMIPS_GENERIC 120 default ARCH_BRCMSTB || BMIPS_GENERIC 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 124 125config BCM7120_L2_IRQ 126 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 127 depends on ARCH_BRCMSTB || BMIPS_GENERIC 128 default ARCH_BRCMSTB || BMIPS_GENERIC 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 132config BRCMSTB_L2_IRQ 133 tristate "Broadcom STB generic L2 interrupt controller driver" 134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 139config DAVINCI_AINTC 140 bool 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 144config DAVINCI_CP_INTC 145 bool 146 select GENERIC_IRQ_CHIP 147 select IRQ_DOMAIN 148 149config DW_APB_ICTL 150 bool 151 select GENERIC_IRQ_CHIP 152 select IRQ_DOMAIN_HIERARCHY 153 154config FARADAY_FTINTC010 155 bool 156 select IRQ_DOMAIN 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select SPARSE_IRQ 173 174config MADERA_IRQ 175 tristate 176 177config IRQ_MIPS_CPU 178 bool 179 select GENERIC_IRQ_CHIP 180 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 181 select IRQ_DOMAIN 182 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 183 184config CLPS711X_IRQCHIP 185 bool 186 depends on ARCH_CLPS711X 187 select IRQ_DOMAIN 188 select SPARSE_IRQ 189 default y 190 191config OMPIC 192 bool 193 194config OR1K_PIC 195 bool 196 select IRQ_DOMAIN 197 198config OMAP_IRQCHIP 199 bool 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 203config ORION_IRQCHIP 204 bool 205 select IRQ_DOMAIN 206 207config PIC32_EVIC 208 bool 209 select GENERIC_IRQ_CHIP 210 select IRQ_DOMAIN 211 212config JCORE_AIC 213 bool "J-Core integrated AIC" if COMPILE_TEST 214 depends on OF 215 select IRQ_DOMAIN 216 help 217 Support for the J-Core integrated AIC. 218 219config RDA_INTC 220 bool 221 select IRQ_DOMAIN 222 223config RENESAS_INTC_IRQPIN 224 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 225 select IRQ_DOMAIN 226 help 227 Enable support for the Renesas Interrupt Controller for external 228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 229 230config RENESAS_IRQC 231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 232 select GENERIC_IRQ_CHIP 233 select IRQ_DOMAIN 234 help 235 Enable support for the Renesas Interrupt Controller for external 236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 237 238config RENESAS_RZA1_IRQC 239 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 240 select IRQ_DOMAIN_HIERARCHY 241 help 242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 243 to 8 external interrupts with configurable sense select. 244 245config SL28CPLD_INTC 246 bool "Kontron sl28cpld IRQ controller" 247 depends on MFD_SL28CPLD=y || COMPILE_TEST 248 select REGMAP_IRQ 249 help 250 Interrupt controller driver for the board management controller 251 found on the Kontron sl28 CPLD. 252 253config ST_IRQCHIP 254 bool 255 select REGMAP 256 select MFD_SYSCON 257 help 258 Enables SysCfg Controlled IRQs on STi based platforms. 259 260config SUN4I_INTC 261 bool 262 263config SUN6I_R_INTC 264 bool 265 select IRQ_DOMAIN_HIERARCHY 266 select IRQ_FASTEOI_HIERARCHY_HANDLERS 267 268config SUNXI_NMI_INTC 269 bool 270 select GENERIC_IRQ_CHIP 271 272config TB10X_IRQC 273 bool 274 select IRQ_DOMAIN 275 select GENERIC_IRQ_CHIP 276 277config TS4800_IRQ 278 tristate "TS-4800 IRQ controller" 279 select IRQ_DOMAIN 280 depends on HAS_IOMEM 281 depends on SOC_IMX51 || COMPILE_TEST 282 help 283 Support for the TS-4800 FPGA IRQ controller 284 285config VERSATILE_FPGA_IRQ 286 bool 287 select IRQ_DOMAIN 288 289config VERSATILE_FPGA_IRQ_NR 290 int 291 default 4 292 depends on VERSATILE_FPGA_IRQ 293 294config XTENSA_MX 295 bool 296 select IRQ_DOMAIN 297 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 298 299config XILINX_INTC 300 bool "Xilinx Interrupt Controller IP" 301 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP 302 select IRQ_DOMAIN 303 help 304 Support for the Xilinx Interrupt Controller IP core. 305 This is used as a primary controller with MicroBlaze and can also 306 be used as a secondary chained controller on other platforms. 307 308config IRQ_CROSSBAR 309 bool 310 help 311 Support for a CROSSBAR ip that precedes the main interrupt controller. 312 The primary irqchip invokes the crossbar's callback which inturn allocates 313 a free irq and configures the IP. Thus the peripheral interrupts are 314 routed to one of the free irqchip interrupt lines. 315 316config KEYSTONE_IRQ 317 tristate "Keystone 2 IRQ controller IP" 318 depends on ARCH_KEYSTONE 319 help 320 Support for Texas Instruments Keystone 2 IRQ controller IP which 321 is part of the Keystone 2 IPC mechanism 322 323config MIPS_GIC 324 bool 325 select GENERIC_IRQ_IPI 326 select MIPS_CM 327 328config INGENIC_IRQ 329 bool 330 depends on MACH_INGENIC 331 default y 332 333config INGENIC_TCU_IRQ 334 bool "Ingenic JZ47xx TCU interrupt controller" 335 default MACH_INGENIC 336 depends on MIPS || COMPILE_TEST 337 select MFD_SYSCON 338 select GENERIC_IRQ_CHIP 339 help 340 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 341 JZ47xx SoCs. 342 343 If unsure, say N. 344 345config RENESAS_H8300H_INTC 346 bool 347 select IRQ_DOMAIN 348 349config RENESAS_H8S_INTC 350 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 351 select IRQ_DOMAIN 352 help 353 Enable support for the Renesas H8/300 Interrupt Controller, as found 354 on Renesas H8S SoCs. 355 356config IMX_GPCV2 357 bool 358 select IRQ_DOMAIN 359 help 360 Enables the wakeup IRQs for IMX platforms with GPCv2 block 361 362config IRQ_MXS 363 def_bool y if MACH_ASM9260 || ARCH_MXS 364 select IRQ_DOMAIN 365 select STMP_DEVICE 366 367config MSCC_OCELOT_IRQ 368 bool 369 select IRQ_DOMAIN 370 select GENERIC_IRQ_CHIP 371 372config MVEBU_GICP 373 bool 374 375config MVEBU_ICU 376 bool 377 378config MVEBU_ODMI 379 bool 380 select GENERIC_MSI_IRQ_DOMAIN 381 382config MVEBU_PIC 383 bool 384 385config MVEBU_SEI 386 bool 387 388config LS_EXTIRQ 389 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 390 select MFD_SYSCON 391 392config LS_SCFG_MSI 393 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 394 depends on PCI && PCI_MSI 395 396config PARTITION_PERCPU 397 bool 398 399config STM32_EXTI 400 bool 401 select IRQ_DOMAIN 402 select GENERIC_IRQ_CHIP 403 404config QCOM_IRQ_COMBINER 405 bool "QCOM IRQ combiner support" 406 depends on ARCH_QCOM && ACPI 407 select IRQ_DOMAIN_HIERARCHY 408 help 409 Say yes here to add support for the IRQ combiner devices embedded 410 in Qualcomm Technologies chips. 411 412config IRQ_UNIPHIER_AIDET 413 bool "UniPhier AIDET support" if COMPILE_TEST 414 depends on ARCH_UNIPHIER || COMPILE_TEST 415 default ARCH_UNIPHIER 416 select IRQ_DOMAIN_HIERARCHY 417 help 418 Support for the UniPhier AIDET (ARM Interrupt Detector). 419 420config MESON_IRQ_GPIO 421 tristate "Meson GPIO Interrupt Multiplexer" 422 depends on ARCH_MESON || COMPILE_TEST 423 default ARCH_MESON 424 select IRQ_DOMAIN_HIERARCHY 425 help 426 Support Meson SoC Family GPIO Interrupt Multiplexer 427 428config GOLDFISH_PIC 429 bool "Goldfish programmable interrupt controller" 430 depends on MIPS && (GOLDFISH || COMPILE_TEST) 431 select GENERIC_IRQ_CHIP 432 select IRQ_DOMAIN 433 help 434 Say yes here to enable Goldfish interrupt controller driver used 435 for Goldfish based virtual platforms. 436 437config QCOM_PDC 438 tristate "QCOM PDC" 439 depends on ARCH_QCOM 440 select IRQ_DOMAIN_HIERARCHY 441 help 442 Power Domain Controller driver to manage and configure wakeup 443 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 444 445config QCOM_MPM 446 tristate "QCOM MPM" 447 depends on ARCH_QCOM 448 depends on MAILBOX 449 select IRQ_DOMAIN_HIERARCHY 450 help 451 MSM Power Manager driver to manage and configure wakeup 452 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 453 454config CSKY_MPINTC 455 bool 456 depends on CSKY 457 help 458 Say yes here to enable C-SKY SMP interrupt controller driver used 459 for C-SKY SMP system. 460 In fact it's not mmio map in hardware and it uses ld/st to visit the 461 controller's register inside CPU. 462 463config CSKY_APB_INTC 464 bool "C-SKY APB Interrupt Controller" 465 depends on CSKY 466 help 467 Say yes here to enable C-SKY APB interrupt controller driver used 468 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 469 the controller's register. 470 471config IMX_IRQSTEER 472 bool "i.MX IRQSTEER support" 473 depends on ARCH_MXC || COMPILE_TEST 474 default ARCH_MXC 475 select IRQ_DOMAIN 476 help 477 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 478 479config IMX_INTMUX 480 bool "i.MX INTMUX support" if COMPILE_TEST 481 default y if ARCH_MXC 482 select IRQ_DOMAIN 483 help 484 Support for the i.MX INTMUX interrupt multiplexer. 485 486config LS1X_IRQ 487 bool "Loongson-1 Interrupt Controller" 488 depends on MACH_LOONGSON32 489 default y 490 select IRQ_DOMAIN 491 select GENERIC_IRQ_CHIP 492 help 493 Support for the Loongson-1 platform Interrupt Controller. 494 495config TI_SCI_INTR_IRQCHIP 496 bool 497 depends on TI_SCI_PROTOCOL 498 select IRQ_DOMAIN_HIERARCHY 499 help 500 This enables the irqchip driver support for K3 Interrupt router 501 over TI System Control Interface available on some new TI's SoCs. 502 If you wish to use interrupt router irq resources managed by the 503 TI System Controller, say Y here. Otherwise, say N. 504 505config TI_SCI_INTA_IRQCHIP 506 bool 507 depends on TI_SCI_PROTOCOL 508 select IRQ_DOMAIN_HIERARCHY 509 select TI_SCI_INTA_MSI_DOMAIN 510 help 511 This enables the irqchip driver support for K3 Interrupt aggregator 512 over TI System Control Interface available on some new TI's SoCs. 513 If you wish to use interrupt aggregator irq resources managed by the 514 TI System Controller, say Y here. Otherwise, say N. 515 516config TI_PRUSS_INTC 517 tristate 518 depends on TI_PRUSS 519 default TI_PRUSS 520 select IRQ_DOMAIN 521 help 522 This enables support for the PRU-ICSS Local Interrupt Controller 523 present within a PRU-ICSS subsystem present on various TI SoCs. 524 The PRUSS INTC enables various interrupts to be routed to multiple 525 different processors within the SoC. 526 527config RISCV_INTC 528 bool "RISC-V Local Interrupt Controller" 529 depends on RISCV 530 default y 531 help 532 This enables support for the per-HART local interrupt controller 533 found in standard RISC-V systems. The per-HART local interrupt 534 controller handles timer interrupts, software interrupts, and 535 hardware interrupts. Without a per-HART local interrupt controller, 536 a RISC-V system will be unable to handle any interrupts. 537 538 If you don't know what to do here, say Y. 539 540config SIFIVE_PLIC 541 bool "SiFive Platform-Level Interrupt Controller" 542 depends on RISCV 543 select IRQ_DOMAIN_HIERARCHY 544 help 545 This enables support for the PLIC chip found in SiFive (and 546 potentially other) RISC-V systems. The PLIC controls devices 547 interrupts and connects them to each core's local interrupt 548 controller. Aside from timer and software interrupts, all other 549 interrupt sources are subordinate to the PLIC. 550 551 If you don't know what to do here, say Y. 552 553config EXYNOS_IRQ_COMBINER 554 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 555 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 556 help 557 Say yes here to add support for the IRQ combiner devices embedded 558 in Samsung Exynos chips. 559 560config LOONGSON_LIOINTC 561 bool "Loongson Local I/O Interrupt Controller" 562 depends on MACH_LOONGSON64 563 default y 564 select IRQ_DOMAIN 565 select GENERIC_IRQ_CHIP 566 help 567 Support for the Loongson Local I/O Interrupt Controller. 568 569config LOONGSON_HTPIC 570 bool "Loongson3 HyperTransport PIC Controller" 571 depends on MACH_LOONGSON64 572 default y 573 select IRQ_DOMAIN 574 select GENERIC_IRQ_CHIP 575 help 576 Support for the Loongson-3 HyperTransport PIC Controller. 577 578config LOONGSON_HTVEC 579 bool "Loongson3 HyperTransport Interrupt Vector Controller" 580 depends on MACH_LOONGSON64 581 default MACH_LOONGSON64 582 select IRQ_DOMAIN_HIERARCHY 583 help 584 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 585 586config LOONGSON_PCH_PIC 587 bool "Loongson PCH PIC Controller" 588 depends on MACH_LOONGSON64 || COMPILE_TEST 589 default MACH_LOONGSON64 590 select IRQ_DOMAIN_HIERARCHY 591 select IRQ_FASTEOI_HIERARCHY_HANDLERS 592 help 593 Support for the Loongson PCH PIC Controller. 594 595config LOONGSON_PCH_MSI 596 bool "Loongson PCH MSI Controller" 597 depends on MACH_LOONGSON64 || COMPILE_TEST 598 depends on PCI 599 default MACH_LOONGSON64 600 select IRQ_DOMAIN_HIERARCHY 601 select PCI_MSI 602 help 603 Support for the Loongson PCH MSI Controller. 604 605config MST_IRQ 606 bool "MStar Interrupt Controller" 607 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 608 default ARCH_MEDIATEK 609 select IRQ_DOMAIN 610 select IRQ_DOMAIN_HIERARCHY 611 help 612 Support MStar Interrupt Controller. 613 614config WPCM450_AIC 615 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 616 depends on ARCH_WPCM450 617 help 618 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 619 620config IRQ_IDT3243X 621 bool 622 select GENERIC_IRQ_CHIP 623 select IRQ_DOMAIN 624 625config APPLE_AIC 626 bool "Apple Interrupt Controller (AIC)" 627 depends on ARM64 628 depends on ARCH_APPLE || COMPILE_TEST 629 help 630 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 631 such as the M1. 632 633config MCHP_EIC 634 bool "Microchip External Interrupt Controller" 635 depends on ARCH_AT91 || COMPILE_TEST 636 select IRQ_DOMAIN 637 select IRQ_DOMAIN_HIERARCHY 638 help 639 Support for Microchip External Interrupt Controller. 640 641endmenu 642