1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select IRQ_DOMAIN_HIERARCHY 37 select PARTITION_PERCPU 38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 39 select HAVE_ARM_SMCCC_DISCOVERY 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 68config ARM_VIC_NR 69 int 70 default 4 if ARCH_S5PV210 71 default 2 72 depends on ARM_VIC 73 help 74 The maximum number of VICs available in the system, for 75 power management. 76 77config ARMADA_370_XP_IRQ 78 bool 79 select GENERIC_IRQ_CHIP 80 select PCI_MSI if PCI 81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 82 83config ALPINE_MSI 84 bool 85 depends on PCI 86 select PCI_MSI 87 select GENERIC_IRQ_CHIP 88 89config AL_FIC 90 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 91 depends on OF 92 depends on HAS_IOMEM 93 select GENERIC_IRQ_CHIP 94 select IRQ_DOMAIN 95 help 96 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 97 98config ATMEL_AIC_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 select SPARSE_IRQ 103 104config ATMEL_AIC5_IRQ 105 bool 106 select GENERIC_IRQ_CHIP 107 select IRQ_DOMAIN 108 select SPARSE_IRQ 109 110config I8259 111 bool 112 select IRQ_DOMAIN 113 114config BCM6345_L1_IRQ 115 bool 116 select GENERIC_IRQ_CHIP 117 select IRQ_DOMAIN 118 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 119 120config BCM7038_L1_IRQ 121 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 122 depends on ARCH_BRCMSTB || BMIPS_GENERIC 123 default ARCH_BRCMSTB || BMIPS_GENERIC 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 127 128config BCM7120_L2_IRQ 129 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 130 depends on ARCH_BRCMSTB || BMIPS_GENERIC 131 default ARCH_BRCMSTB || BMIPS_GENERIC 132 select GENERIC_IRQ_CHIP 133 select IRQ_DOMAIN 134 135config BRCMSTB_L2_IRQ 136 tristate "Broadcom STB generic L2 interrupt controller driver" 137 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 138 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 139 select GENERIC_IRQ_CHIP 140 select IRQ_DOMAIN 141 142config DAVINCI_CP_INTC 143 bool 144 select GENERIC_IRQ_CHIP 145 select IRQ_DOMAIN 146 147config DW_APB_ICTL 148 bool 149 select GENERIC_IRQ_CHIP 150 select IRQ_DOMAIN_HIERARCHY 151 152config FARADAY_FTINTC010 153 bool 154 select IRQ_DOMAIN 155 select SPARSE_IRQ 156 157config HISILICON_IRQ_MBIGEN 158 bool 159 select ARM_GIC_V3 160 select ARM_GIC_V3_ITS 161 162config IMGPDC_IRQ 163 bool 164 select GENERIC_IRQ_CHIP 165 select IRQ_DOMAIN 166 167config IXP4XX_IRQ 168 bool 169 select IRQ_DOMAIN 170 select SPARSE_IRQ 171 172config MADERA_IRQ 173 tristate 174 175config IRQ_MIPS_CPU 176 bool 177 select GENERIC_IRQ_CHIP 178 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 179 select IRQ_DOMAIN 180 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 181 182config CLPS711X_IRQCHIP 183 bool 184 depends on ARCH_CLPS711X 185 select IRQ_DOMAIN 186 select SPARSE_IRQ 187 default y 188 189config OMPIC 190 bool 191 192config OR1K_PIC 193 bool 194 select IRQ_DOMAIN 195 196config OMAP_IRQCHIP 197 bool 198 select GENERIC_IRQ_CHIP 199 select IRQ_DOMAIN 200 201config ORION_IRQCHIP 202 bool 203 select IRQ_DOMAIN 204 205config PIC32_EVIC 206 bool 207 select GENERIC_IRQ_CHIP 208 select IRQ_DOMAIN 209 210config JCORE_AIC 211 bool "J-Core integrated AIC" if COMPILE_TEST 212 depends on OF 213 select IRQ_DOMAIN 214 help 215 Support for the J-Core integrated AIC. 216 217config RDA_INTC 218 bool 219 select IRQ_DOMAIN 220 221config RENESAS_INTC_IRQPIN 222 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 223 select IRQ_DOMAIN 224 help 225 Enable support for the Renesas Interrupt Controller for external 226 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 227 228config RENESAS_IRQC 229 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 230 select GENERIC_IRQ_CHIP 231 select IRQ_DOMAIN 232 help 233 Enable support for the Renesas Interrupt Controller for external 234 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 235 236config RENESAS_RZA1_IRQC 237 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 238 select IRQ_DOMAIN_HIERARCHY 239 help 240 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 241 to 8 external interrupts with configurable sense select. 242 243config RENESAS_RZG2L_IRQC 244 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 245 select GENERIC_IRQ_CHIP 246 select IRQ_DOMAIN_HIERARCHY 247 help 248 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 249 for external devices. 250 251config SL28CPLD_INTC 252 bool "Kontron sl28cpld IRQ controller" 253 depends on MFD_SL28CPLD=y || COMPILE_TEST 254 select REGMAP_IRQ 255 help 256 Interrupt controller driver for the board management controller 257 found on the Kontron sl28 CPLD. 258 259config ST_IRQCHIP 260 bool 261 select REGMAP 262 select MFD_SYSCON 263 help 264 Enables SysCfg Controlled IRQs on STi based platforms. 265 266config SUN4I_INTC 267 bool 268 269config SUN6I_R_INTC 270 bool 271 select IRQ_DOMAIN_HIERARCHY 272 select IRQ_FASTEOI_HIERARCHY_HANDLERS 273 274config SUNXI_NMI_INTC 275 bool 276 select GENERIC_IRQ_CHIP 277 278config TB10X_IRQC 279 bool 280 select IRQ_DOMAIN 281 select GENERIC_IRQ_CHIP 282 283config TS4800_IRQ 284 tristate "TS-4800 IRQ controller" 285 select IRQ_DOMAIN 286 depends on HAS_IOMEM 287 depends on SOC_IMX51 || COMPILE_TEST 288 help 289 Support for the TS-4800 FPGA IRQ controller 290 291config VERSATILE_FPGA_IRQ 292 bool 293 select IRQ_DOMAIN 294 295config VERSATILE_FPGA_IRQ_NR 296 int 297 default 4 298 depends on VERSATILE_FPGA_IRQ 299 300config XTENSA_MX 301 bool 302 select IRQ_DOMAIN 303 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 304 305config XILINX_INTC 306 bool "Xilinx Interrupt Controller IP" 307 depends on OF_ADDRESS 308 select IRQ_DOMAIN 309 help 310 Support for the Xilinx Interrupt Controller IP core. 311 This is used as a primary controller with MicroBlaze and can also 312 be used as a secondary chained controller on other platforms. 313 314config IRQ_CROSSBAR 315 bool 316 help 317 Support for a CROSSBAR ip that precedes the main interrupt controller. 318 The primary irqchip invokes the crossbar's callback which inturn allocates 319 a free irq and configures the IP. Thus the peripheral interrupts are 320 routed to one of the free irqchip interrupt lines. 321 322config KEYSTONE_IRQ 323 tristate "Keystone 2 IRQ controller IP" 324 depends on ARCH_KEYSTONE 325 help 326 Support for Texas Instruments Keystone 2 IRQ controller IP which 327 is part of the Keystone 2 IPC mechanism 328 329config MIPS_GIC 330 bool 331 select GENERIC_IRQ_IPI if SMP 332 select IRQ_DOMAIN_HIERARCHY 333 select MIPS_CM 334 335config INGENIC_IRQ 336 bool 337 depends on MACH_INGENIC 338 default y 339 340config INGENIC_TCU_IRQ 341 bool "Ingenic JZ47xx TCU interrupt controller" 342 default MACH_INGENIC 343 depends on MIPS || COMPILE_TEST 344 select MFD_SYSCON 345 select GENERIC_IRQ_CHIP 346 help 347 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 348 JZ47xx SoCs. 349 350 If unsure, say N. 351 352config IMX_GPCV2 353 bool 354 select IRQ_DOMAIN 355 help 356 Enables the wakeup IRQs for IMX platforms with GPCv2 block 357 358config IRQ_MXS 359 def_bool y if MACH_ASM9260 || ARCH_MXS 360 select IRQ_DOMAIN 361 select STMP_DEVICE 362 363config MSCC_OCELOT_IRQ 364 bool 365 select IRQ_DOMAIN 366 select GENERIC_IRQ_CHIP 367 368config MVEBU_GICP 369 bool 370 371config MVEBU_ICU 372 bool 373 374config MVEBU_ODMI 375 bool 376 select GENERIC_MSI_IRQ 377 378config MVEBU_PIC 379 bool 380 381config MVEBU_SEI 382 bool 383 384config LS_EXTIRQ 385 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 386 select MFD_SYSCON 387 388config LS_SCFG_MSI 389 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 390 depends on PCI_MSI 391 392config PARTITION_PERCPU 393 bool 394 395config STM32_EXTI 396 bool 397 select IRQ_DOMAIN 398 select GENERIC_IRQ_CHIP 399 400config QCOM_IRQ_COMBINER 401 bool "QCOM IRQ combiner support" 402 depends on ARCH_QCOM && ACPI 403 select IRQ_DOMAIN_HIERARCHY 404 help 405 Say yes here to add support for the IRQ combiner devices embedded 406 in Qualcomm Technologies chips. 407 408config IRQ_UNIPHIER_AIDET 409 bool "UniPhier AIDET support" if COMPILE_TEST 410 depends on ARCH_UNIPHIER || COMPILE_TEST 411 default ARCH_UNIPHIER 412 select IRQ_DOMAIN_HIERARCHY 413 help 414 Support for the UniPhier AIDET (ARM Interrupt Detector). 415 416config MESON_IRQ_GPIO 417 tristate "Meson GPIO Interrupt Multiplexer" 418 depends on ARCH_MESON || COMPILE_TEST 419 default ARCH_MESON 420 select IRQ_DOMAIN_HIERARCHY 421 help 422 Support Meson SoC Family GPIO Interrupt Multiplexer 423 424config GOLDFISH_PIC 425 bool "Goldfish programmable interrupt controller" 426 depends on MIPS && (GOLDFISH || COMPILE_TEST) 427 select GENERIC_IRQ_CHIP 428 select IRQ_DOMAIN 429 help 430 Say yes here to enable Goldfish interrupt controller driver used 431 for Goldfish based virtual platforms. 432 433config QCOM_PDC 434 tristate "QCOM PDC" 435 depends on ARCH_QCOM 436 select IRQ_DOMAIN_HIERARCHY 437 help 438 Power Domain Controller driver to manage and configure wakeup 439 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 440 441config QCOM_MPM 442 tristate "QCOM MPM" 443 depends on ARCH_QCOM 444 depends on MAILBOX 445 select IRQ_DOMAIN_HIERARCHY 446 help 447 MSM Power Manager driver to manage and configure wakeup 448 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 449 450config CSKY_MPINTC 451 bool 452 depends on CSKY 453 help 454 Say yes here to enable C-SKY SMP interrupt controller driver used 455 for C-SKY SMP system. 456 In fact it's not mmio map in hardware and it uses ld/st to visit the 457 controller's register inside CPU. 458 459config CSKY_APB_INTC 460 bool "C-SKY APB Interrupt Controller" 461 depends on CSKY 462 help 463 Say yes here to enable C-SKY APB interrupt controller driver used 464 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 465 the controller's register. 466 467config IMX_IRQSTEER 468 bool "i.MX IRQSTEER support" 469 depends on ARCH_MXC || COMPILE_TEST 470 default ARCH_MXC 471 select IRQ_DOMAIN 472 help 473 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 474 475config IMX_INTMUX 476 bool "i.MX INTMUX support" if COMPILE_TEST 477 default y if ARCH_MXC 478 select IRQ_DOMAIN 479 help 480 Support for the i.MX INTMUX interrupt multiplexer. 481 482config IMX_MU_MSI 483 tristate "i.MX MU used as MSI controller" 484 depends on OF && HAS_IOMEM 485 depends on ARCH_MXC || COMPILE_TEST 486 default m if ARCH_MXC 487 select IRQ_DOMAIN 488 select IRQ_DOMAIN_HIERARCHY 489 select GENERIC_MSI_IRQ 490 help 491 Provide a driver for the i.MX Messaging Unit block used as a 492 CPU-to-CPU MSI controller. This requires a specially crafted DT 493 to make use of this driver. 494 495 If unsure, say N 496 497config LS1X_IRQ 498 bool "Loongson-1 Interrupt Controller" 499 depends on MACH_LOONGSON32 500 default y 501 select IRQ_DOMAIN 502 select GENERIC_IRQ_CHIP 503 help 504 Support for the Loongson-1 platform Interrupt Controller. 505 506config TI_SCI_INTR_IRQCHIP 507 bool 508 depends on TI_SCI_PROTOCOL 509 select IRQ_DOMAIN_HIERARCHY 510 help 511 This enables the irqchip driver support for K3 Interrupt router 512 over TI System Control Interface available on some new TI's SoCs. 513 If you wish to use interrupt router irq resources managed by the 514 TI System Controller, say Y here. Otherwise, say N. 515 516config TI_SCI_INTA_IRQCHIP 517 bool 518 depends on TI_SCI_PROTOCOL 519 select IRQ_DOMAIN_HIERARCHY 520 select TI_SCI_INTA_MSI_DOMAIN 521 help 522 This enables the irqchip driver support for K3 Interrupt aggregator 523 over TI System Control Interface available on some new TI's SoCs. 524 If you wish to use interrupt aggregator irq resources managed by the 525 TI System Controller, say Y here. Otherwise, say N. 526 527config TI_PRUSS_INTC 528 tristate 529 depends on TI_PRUSS 530 default TI_PRUSS 531 select IRQ_DOMAIN 532 help 533 This enables support for the PRU-ICSS Local Interrupt Controller 534 present within a PRU-ICSS subsystem present on various TI SoCs. 535 The PRUSS INTC enables various interrupts to be routed to multiple 536 different processors within the SoC. 537 538config RISCV_INTC 539 bool 540 depends on RISCV 541 select IRQ_DOMAIN_HIERARCHY 542 543config RISCV_APLIC 544 bool 545 depends on RISCV 546 select IRQ_DOMAIN_HIERARCHY 547 548config RISCV_APLIC_MSI 549 bool 550 depends on RISCV_APLIC 551 select GENERIC_MSI_IRQ 552 default RISCV_APLIC 553 554config RISCV_IMSIC 555 bool 556 depends on RISCV 557 select IRQ_DOMAIN_HIERARCHY 558 select GENERIC_IRQ_MATRIX_ALLOCATOR 559 select GENERIC_MSI_IRQ 560 561config RISCV_IMSIC_PCI 562 bool 563 depends on RISCV_IMSIC 564 depends on PCI 565 depends on PCI_MSI 566 default RISCV_IMSIC 567 568config SIFIVE_PLIC 569 bool 570 depends on RISCV 571 select IRQ_DOMAIN_HIERARCHY 572 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 573 574config STARFIVE_JH8100_INTC 575 bool "StarFive JH8100 External Interrupt Controller" 576 depends on ARCH_STARFIVE || COMPILE_TEST 577 default ARCH_STARFIVE 578 select IRQ_DOMAIN_HIERARCHY 579 help 580 This enables support for the INTC chip found in StarFive JH8100 581 SoC. 582 583 If you don't know what to do here, say Y. 584 585config EXYNOS_IRQ_COMBINER 586 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 587 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 588 help 589 Say yes here to add support for the IRQ combiner devices embedded 590 in Samsung Exynos chips. 591 592config IRQ_LOONGARCH_CPU 593 bool 594 select GENERIC_IRQ_CHIP 595 select IRQ_DOMAIN 596 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 597 select LOONGSON_HTVEC 598 select LOONGSON_LIOINTC 599 select LOONGSON_EIOINTC 600 select LOONGSON_PCH_PIC 601 select LOONGSON_PCH_MSI 602 select LOONGSON_PCH_LPC 603 help 604 Support for the LoongArch CPU Interrupt Controller. For details of 605 irq chip hierarchy on LoongArch platforms please read the document 606 Documentation/arch/loongarch/irq-chip-model.rst. 607 608config LOONGSON_LIOINTC 609 bool "Loongson Local I/O Interrupt Controller" 610 depends on MACH_LOONGSON64 611 default y 612 select IRQ_DOMAIN 613 select GENERIC_IRQ_CHIP 614 help 615 Support for the Loongson Local I/O Interrupt Controller. 616 617config LOONGSON_EIOINTC 618 bool "Loongson Extend I/O Interrupt Controller" 619 depends on LOONGARCH 620 depends on MACH_LOONGSON64 621 default MACH_LOONGSON64 622 select IRQ_DOMAIN_HIERARCHY 623 select GENERIC_IRQ_CHIP 624 help 625 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 626 627config LOONGSON_HTPIC 628 bool "Loongson3 HyperTransport PIC Controller" 629 depends on MACH_LOONGSON64 && MIPS 630 default y 631 select IRQ_DOMAIN 632 select GENERIC_IRQ_CHIP 633 help 634 Support for the Loongson-3 HyperTransport PIC Controller. 635 636config LOONGSON_HTVEC 637 bool "Loongson HyperTransport Interrupt Vector Controller" 638 depends on MACH_LOONGSON64 639 default MACH_LOONGSON64 640 select IRQ_DOMAIN_HIERARCHY 641 help 642 Support for the Loongson HyperTransport Interrupt Vector Controller. 643 644config LOONGSON_PCH_PIC 645 bool "Loongson PCH PIC Controller" 646 depends on MACH_LOONGSON64 647 default MACH_LOONGSON64 648 select IRQ_DOMAIN_HIERARCHY 649 select IRQ_FASTEOI_HIERARCHY_HANDLERS 650 help 651 Support for the Loongson PCH PIC Controller. 652 653config LOONGSON_PCH_MSI 654 bool "Loongson PCH MSI Controller" 655 depends on MACH_LOONGSON64 656 depends on PCI 657 default MACH_LOONGSON64 658 select IRQ_DOMAIN_HIERARCHY 659 select PCI_MSI 660 help 661 Support for the Loongson PCH MSI Controller. 662 663config LOONGSON_PCH_LPC 664 bool "Loongson PCH LPC Controller" 665 depends on LOONGARCH 666 depends on MACH_LOONGSON64 667 default MACH_LOONGSON64 668 select IRQ_DOMAIN_HIERARCHY 669 help 670 Support for the Loongson PCH LPC Controller. 671 672config MST_IRQ 673 bool "MStar Interrupt Controller" 674 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 675 default ARCH_MEDIATEK 676 select IRQ_DOMAIN 677 select IRQ_DOMAIN_HIERARCHY 678 help 679 Support MStar Interrupt Controller. 680 681config WPCM450_AIC 682 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 683 depends on ARCH_WPCM450 684 help 685 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 686 687config IRQ_IDT3243X 688 bool 689 select GENERIC_IRQ_CHIP 690 select IRQ_DOMAIN 691 692config APPLE_AIC 693 bool "Apple Interrupt Controller (AIC)" 694 depends on ARM64 695 depends on ARCH_APPLE || COMPILE_TEST 696 select GENERIC_IRQ_IPI_MUX 697 help 698 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 699 such as the M1. 700 701config MCHP_EIC 702 bool "Microchip External Interrupt Controller" 703 depends on ARCH_AT91 || COMPILE_TEST 704 select IRQ_DOMAIN 705 select IRQ_DOMAIN_HIERARCHY 706 help 707 Support for Microchip External Interrupt Controller. 708 709config SUNPLUS_SP7021_INTC 710 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 711 default SOC_SP7021 712 help 713 Support for the Sunplus SP7021 Interrupt Controller IP core. 714 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 715 chained controller, routing all interrupt source in P-Chip to 716 the primary controller on C-Chip. 717 718endmenu 719