1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V5 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 58 select GENERIC_MSI_IRQ 59 select IRQ_MSI_LIB 60 select ARM_GIC_ITS_PARENT 61 62config ARM_NVIC 63 bool 64 select IRQ_DOMAIN_HIERARCHY 65 select GENERIC_IRQ_CHIP 66 67config ARM_VIC 68 bool 69 select IRQ_DOMAIN 70 71config ARM_VIC_NR 72 int 73 default 4 if ARCH_S5PV210 74 default 2 75 depends on ARM_VIC 76 help 77 The maximum number of VICs available in the system, for 78 power management. 79 80config IRQ_MSI_LIB 81 bool 82 select GENERIC_MSI_IRQ 83 84config ARMADA_370_XP_IRQ 85 bool 86 select GENERIC_IRQ_CHIP 87 select PCI_MSI if PCI 88 select IRQ_MSI_LIB if PCI 89 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 90 91config ALPINE_MSI 92 bool 93 depends on PCI 94 select PCI_MSI 95 select IRQ_MSI_LIB 96 select GENERIC_IRQ_CHIP 97 98config AL_FIC 99 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 100 depends on OF 101 depends on HAS_IOMEM 102 select GENERIC_IRQ_CHIP 103 select IRQ_DOMAIN 104 help 105 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 106 107config ASPEED_AST2700_INTC 108 bool "ASPEED AST2700 Interrupt Controller support" 109 depends on OF 110 depends on ARCH_ASPEED || COMPILE_TEST 111 select IRQ_DOMAIN_HIERARCHY 112 help 113 Enable support for the ASPEED AST2700 interrupt controller. 114 This driver handles interrupt, routing and merged interrupt 115 sources to upstream parent interrupt controllers. 116 117 If unsure, say N. 118 119config ASPEED_AST2700_INTC_TEST 120 bool "Tests for the ASPEED AST2700 Interrupt Controller" 121 depends on ASPEED_AST2700_INTC && KUNIT=y 122 default KUNIT_ALL_TESTS 123 help 124 Enable KUnit tests for AST2700 INTC route resolution. 125 The tests exercise error handling and route selection paths. 126 This option is intended for test builds. 127 128 If unsure, say N. 129 130config ATMEL_AIC_IRQ 131 bool 132 select GENERIC_IRQ_CHIP 133 select IRQ_DOMAIN 134 select SPARSE_IRQ 135 136config ATMEL_AIC5_IRQ 137 bool 138 select GENERIC_IRQ_CHIP 139 select IRQ_DOMAIN 140 select SPARSE_IRQ 141 142config I8259 143 bool 144 select IRQ_DOMAIN 145 146config BCM2712_MIP 147 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 148 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 149 default m if ARCH_BRCMSTB || ARCH_BCM2835 150 depends on ARM_GIC 151 select GENERIC_IRQ_CHIP 152 select IRQ_DOMAIN_HIERARCHY 153 select GENERIC_MSI_IRQ 154 select IRQ_MSI_LIB 155 help 156 Enable support for the Broadcom BCM2712 MSI-X target peripheral 157 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 158 Raspberry Pi 5. 159 160 If unsure say n. 161 162config BCM6345_L1_IRQ 163 bool 164 select GENERIC_IRQ_CHIP 165 select IRQ_DOMAIN 166 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 167 168config BCM7038_L1_IRQ 169 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 170 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 171 default ARCH_BRCMSTB || BMIPS_GENERIC 172 select GENERIC_IRQ_CHIP 173 select IRQ_DOMAIN 174 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 175 176config BCM7120_L2_IRQ 177 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 178 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 179 default ARCH_BRCMSTB || BMIPS_GENERIC 180 select GENERIC_IRQ_CHIP 181 select IRQ_DOMAIN 182 183config BRCMSTB_L2_IRQ 184 tristate "Broadcom STB generic L2 interrupt controller driver" 185 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 186 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 187 select GENERIC_IRQ_CHIP 188 select IRQ_DOMAIN 189 190config DAVINCI_CP_INTC 191 bool 192 select GENERIC_IRQ_CHIP 193 select IRQ_DOMAIN 194 195config DW_APB_ICTL 196 bool 197 select GENERIC_IRQ_CHIP 198 select IRQ_DOMAIN_HIERARCHY 199 200config ECONET_EN751221_INTC 201 bool 202 select GENERIC_IRQ_CHIP 203 select IRQ_DOMAIN 204 205config FARADAY_FTINTC010 206 bool 207 select IRQ_DOMAIN 208 select SPARSE_IRQ 209 210config HISILICON_IRQ_MBIGEN 211 bool 212 select ARM_GIC_V3 213 select ARM_GIC_V3_ITS 214 215config IMGPDC_IRQ 216 bool 217 select GENERIC_IRQ_CHIP 218 select IRQ_DOMAIN 219 220config IXP4XX_IRQ 221 bool 222 select IRQ_DOMAIN 223 select SPARSE_IRQ 224 225config LAN966X_OIC 226 tristate "Microchip LAN966x OIC Support" 227 depends on MCHP_LAN966X_PCI || COMPILE_TEST 228 select GENERIC_IRQ_CHIP 229 select IRQ_DOMAIN 230 help 231 Enable support for the LAN966x Outbound Interrupt Controller. 232 This controller is present on the Microchip LAN966x PCI device and 233 maps the internal interrupts sources to PCIe interrupt. 234 235 To compile this driver as a module, choose M here: the module 236 will be called irq-lan966x-oic. 237 238config MADERA_IRQ 239 tristate 240 241config IRQ_MIPS_CPU 242 bool 243 select GENERIC_IRQ_CHIP 244 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 245 select IRQ_DOMAIN 246 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 247 248config CLPS711X_IRQCHIP 249 bool 250 depends on ARCH_CLPS711X 251 select IRQ_DOMAIN 252 select SPARSE_IRQ 253 default y 254 255config OMPIC 256 bool 257 258config OR1K_PIC 259 bool 260 select IRQ_DOMAIN 261 262config OMAP_IRQCHIP 263 bool 264 select GENERIC_IRQ_CHIP 265 select IRQ_DOMAIN 266 267config ORION_IRQCHIP 268 bool 269 select IRQ_DOMAIN 270 271config PIC32_EVIC 272 def_bool MACH_PIC32 || COMPILE_TEST 273 select GENERIC_IRQ_CHIP 274 select IRQ_DOMAIN 275 help 276 Enable support for the interrupt controller on the Microchip PIC32 277 family of platforms. 278 279config JCORE_AIC 280 bool "J-Core integrated AIC" if COMPILE_TEST 281 depends on OF 282 select IRQ_DOMAIN 283 help 284 Support for the J-Core integrated AIC. 285 286config RDA_INTC 287 bool 288 select IRQ_DOMAIN 289 290config RENESAS_INTC_IRQPIN 291 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 292 select IRQ_DOMAIN 293 help 294 Enable support for the Renesas Interrupt Controller for external 295 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 296 297config RENESAS_IRQC 298 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 299 select GENERIC_IRQ_CHIP 300 select IRQ_DOMAIN 301 help 302 Enable support for the Renesas Interrupt Controller for external 303 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 304 305config RENESAS_RZA1_IRQC 306 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 307 select IRQ_DOMAIN_HIERARCHY 308 help 309 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 310 to 8 external interrupts with configurable sense select. 311 312config RENESAS_RZG2L_IRQC 313 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 314 select GENERIC_IRQ_CHIP 315 select IRQ_DOMAIN_HIERARCHY 316 help 317 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 318 for external devices. 319 320config RENESAS_RZT2H_ICU 321 bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST 322 select GENERIC_IRQ_CHIP 323 select IRQ_DOMAIN_HIERARCHY 324 help 325 Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller 326 (ICU). 327 328config RENESAS_RZV2H_ICU 329 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 330 select GENERIC_IRQ_CHIP 331 select IRQ_DOMAIN_HIERARCHY 332 help 333 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 334 335config SL28CPLD_INTC 336 bool "Kontron sl28cpld IRQ controller" 337 depends on MFD_SL28CPLD=y || COMPILE_TEST 338 select REGMAP_IRQ 339 help 340 Interrupt controller driver for the board management controller 341 found on the Kontron sl28 CPLD. 342 343config ST_IRQCHIP 344 bool 345 select REGMAP 346 select MFD_SYSCON 347 help 348 Enables SysCfg Controlled IRQs on STi based platforms. 349 350config SUN4I_INTC 351 bool 352 353config SUN6I_R_INTC 354 bool 355 select IRQ_DOMAIN_HIERARCHY 356 select IRQ_FASTEOI_HIERARCHY_HANDLERS 357 358config SUNXI_NMI_INTC 359 bool 360 select GENERIC_IRQ_CHIP 361 362config TB10X_IRQC 363 bool 364 select IRQ_DOMAIN 365 select GENERIC_IRQ_CHIP 366 367config TS4800_IRQ 368 tristate "TS-4800 IRQ controller" 369 select IRQ_DOMAIN 370 depends on HAS_IOMEM 371 depends on SOC_IMX51 || COMPILE_TEST 372 help 373 Support for the TS-4800 FPGA IRQ controller 374 375config VERSATILE_FPGA_IRQ 376 bool 377 select IRQ_DOMAIN 378 379config VERSATILE_FPGA_IRQ_NR 380 int 381 default 4 382 depends on VERSATILE_FPGA_IRQ 383 384config XTENSA_MX 385 bool 386 select IRQ_DOMAIN 387 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 388 389config XILINX_INTC 390 bool "Xilinx Interrupt Controller IP" 391 depends on OF_ADDRESS 392 select IRQ_DOMAIN 393 help 394 Support for the Xilinx Interrupt Controller IP core. 395 This is used as a primary controller with MicroBlaze and can also 396 be used as a secondary chained controller on other platforms. 397 398config IRQ_CROSSBAR 399 bool 400 help 401 Support for a CROSSBAR ip that precedes the main interrupt controller. 402 The primary irqchip invokes the crossbar's callback which inturn allocates 403 a free irq and configures the IP. Thus the peripheral interrupts are 404 routed to one of the free irqchip interrupt lines. 405 406config KEYSTONE_IRQ 407 tristate "Keystone 2 IRQ controller IP" 408 depends on ARCH_KEYSTONE 409 help 410 Support for Texas Instruments Keystone 2 IRQ controller IP which 411 is part of the Keystone 2 IPC mechanism 412 413config MIPS_GIC 414 bool 415 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 416 select GENERIC_IRQ_IPI if SMP 417 select IRQ_DOMAIN_HIERARCHY 418 select MIPS_CM 419 420config INGENIC_IRQ 421 bool 422 depends on MACH_INGENIC 423 default y 424 425config INGENIC_TCU_IRQ 426 bool "Ingenic JZ47xx TCU interrupt controller" 427 default MACH_INGENIC 428 depends on MIPS || COMPILE_TEST 429 select MFD_SYSCON 430 select GENERIC_IRQ_CHIP 431 help 432 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 433 JZ47xx SoCs. 434 435 If unsure, say N. 436 437config IMX_GPCV2 438 bool 439 select IRQ_DOMAIN 440 help 441 Enables the wakeup IRQs for IMX platforms with GPCv2 block 442 443config IRQ_MXS 444 def_bool y if MACH_ASM9260 || ARCH_MXS 445 select IRQ_DOMAIN 446 select STMP_DEVICE 447 448config MSCC_OCELOT_IRQ 449 bool 450 select IRQ_DOMAIN 451 select GENERIC_IRQ_CHIP 452 453config MVEBU_GICP 454 select IRQ_MSI_LIB 455 bool 456 457config MVEBU_ICU 458 bool 459 460config MVEBU_ODMI 461 bool 462 select IRQ_MSI_LIB 463 select GENERIC_MSI_IRQ 464 465config MVEBU_PIC 466 bool 467 468config MVEBU_SEI 469 bool 470 471config LS_EXTIRQ 472 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 473 select MFD_SYSCON 474 475config LS_SCFG_MSI 476 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 477 select IRQ_MSI_IOMMU 478 depends on PCI_MSI 479 select IRQ_MSI_LIB 480 481config STM32MP_EXTI 482 tristate "STM32MP extended interrupts and event controller" 483 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 484 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 485 select IRQ_DOMAIN_HIERARCHY 486 select GENERIC_IRQ_CHIP 487 help 488 Support STM32MP EXTI (extended interrupts and event) controller. 489 490config STM32_EXTI 491 bool 492 select IRQ_DOMAIN 493 select GENERIC_IRQ_CHIP 494 495config QCOM_IRQ_COMBINER 496 bool "Qualcomm IRQ combiner support" 497 depends on ARCH_QCOM && ACPI 498 select IRQ_DOMAIN_HIERARCHY 499 help 500 Say yes here to add support for the IRQ combiner devices embedded 501 in Qualcomm Technologies chips. 502 503config IRQ_UNIPHIER_AIDET 504 bool "UniPhier AIDET support" if COMPILE_TEST 505 depends on ARCH_UNIPHIER || COMPILE_TEST 506 default ARCH_UNIPHIER 507 select IRQ_DOMAIN_HIERARCHY 508 help 509 Support for the UniPhier AIDET (ARM Interrupt Detector). 510 511config MESON_IRQ_GPIO 512 tristate "Meson GPIO Interrupt Multiplexer" 513 depends on ARCH_MESON || COMPILE_TEST 514 default ARCH_MESON 515 select IRQ_DOMAIN_HIERARCHY 516 help 517 Support Meson SoC Family GPIO Interrupt Multiplexer 518 519config GOLDFISH_PIC 520 bool "Goldfish programmable interrupt controller" 521 depends on MIPS && (GOLDFISH || COMPILE_TEST) 522 select GENERIC_IRQ_CHIP 523 select IRQ_DOMAIN 524 help 525 Say yes here to enable Goldfish interrupt controller driver used 526 for Goldfish based virtual platforms. 527 528config QCOM_PDC 529 tristate "Qualcomm PDC" 530 depends on ARCH_QCOM 531 select IRQ_DOMAIN_HIERARCHY 532 help 533 Power Domain Controller driver to manage and configure wakeup 534 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 535 536config QCOM_MPM 537 tristate "Qualcomm MPM" 538 depends on ARCH_QCOM 539 depends on MAILBOX 540 select IRQ_DOMAIN_HIERARCHY 541 help 542 MSM Power Manager driver to manage and configure wakeup 543 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 544 545config CSKY_MPINTC 546 bool 547 depends on CSKY 548 help 549 Say yes here to enable C-SKY SMP interrupt controller driver used 550 for C-SKY SMP system. 551 In fact it's not mmio map in hardware and it uses ld/st to visit the 552 controller's register inside CPU. 553 554config CSKY_APB_INTC 555 bool "C-SKY APB Interrupt Controller" 556 depends on CSKY 557 help 558 Say yes here to enable C-SKY APB interrupt controller driver used 559 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 560 the controller's register. 561 562config IMX_IRQSTEER 563 bool "i.MX IRQSTEER support" 564 depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST 565 default y if ARCH_MXC || ARCH_S32 566 select IRQ_DOMAIN 567 help 568 Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper. 569 570config IMX_INTMUX 571 bool "i.MX INTMUX support" if COMPILE_TEST 572 default y if ARCH_MXC 573 select IRQ_DOMAIN 574 help 575 Support for the i.MX INTMUX interrupt multiplexer. 576 577config IMX_MU_MSI 578 tristate "i.MX MU used as MSI controller" 579 depends on OF && HAS_IOMEM 580 depends on ARCH_MXC || COMPILE_TEST 581 depends on ARM || ARM64 582 default m if ARCH_MXC 583 select IRQ_DOMAIN 584 select IRQ_DOMAIN_HIERARCHY 585 select GENERIC_MSI_IRQ 586 select IRQ_MSI_LIB 587 help 588 Provide a driver for the i.MX Messaging Unit block used as a 589 CPU-to-CPU MSI controller. This requires a specially crafted DT 590 to make use of this driver. 591 592 If unsure, say N 593 594config LS1X_IRQ 595 bool "Loongson-1 Interrupt Controller" 596 depends on MACH_LOONGSON32 597 default y 598 select IRQ_DOMAIN 599 select GENERIC_IRQ_CHIP 600 help 601 Support for the Loongson-1 platform Interrupt Controller. 602 603config TI_SCI_INTR_IRQCHIP 604 tristate "TI SCI INTR Interrupt Controller" 605 depends on TI_SCI_PROTOCOL 606 depends on ARCH_K3 || COMPILE_TEST 607 select IRQ_DOMAIN_HIERARCHY 608 help 609 This enables the irqchip driver support for K3 Interrupt router 610 over TI System Control Interface available on some new TI's SoCs. 611 If you wish to use interrupt router irq resources managed by the 612 TI System Controller, say Y here. Otherwise, say N. 613 614config TI_SCI_INTA_IRQCHIP 615 tristate "TI SCI INTA Interrupt Controller" 616 depends on TI_SCI_PROTOCOL 617 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 618 select IRQ_DOMAIN_HIERARCHY 619 select TI_SCI_INTA_MSI_DOMAIN 620 help 621 This enables the irqchip driver support for K3 Interrupt aggregator 622 over TI System Control Interface available on some new TI's SoCs. 623 If you wish to use interrupt aggregator irq resources managed by the 624 TI System Controller, say Y here. Otherwise, say N. 625 626config TI_PRUSS_INTC 627 tristate 628 depends on TI_PRUSS 629 default TI_PRUSS 630 select IRQ_DOMAIN 631 help 632 This enables support for the PRU-ICSS Local Interrupt Controller 633 present within a PRU-ICSS subsystem present on various TI SoCs. 634 The PRUSS INTC enables various interrupts to be routed to multiple 635 different processors within the SoC. 636 637config RISCV_INTC 638 bool 639 depends on RISCV 640 select IRQ_DOMAIN_HIERARCHY 641 642config RISCV_APLIC 643 bool 644 depends on RISCV 645 select IRQ_DOMAIN_HIERARCHY 646 647config RISCV_APLIC_MSI 648 bool 649 depends on RISCV_APLIC 650 select GENERIC_MSI_IRQ 651 default RISCV_APLIC 652 653config RISCV_IMSIC 654 bool 655 depends on RISCV 656 select IRQ_DOMAIN_HIERARCHY 657 select GENERIC_IRQ_MATRIX_ALLOCATOR 658 select GENERIC_MSI_IRQ 659 select IRQ_MSI_LIB 660 661config RISCV_RPMI_SYSMSI 662 bool 663 depends on RISCV && MAILBOX 664 select IRQ_DOMAIN_HIERARCHY 665 select GENERIC_MSI_IRQ 666 default RISCV 667 668config SIFIVE_PLIC 669 bool 670 depends on RISCV 671 select IRQ_DOMAIN_HIERARCHY 672 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 673 674config STARFIVE_JHB100_INTC 675 bool "StarFive JHB100 External Interrupt Controller" 676 depends on ARCH_STARFIVE || COMPILE_TEST 677 default ARCH_STARFIVE 678 select IRQ_DOMAIN_HIERARCHY 679 help 680 This enables support for the INTC chip found in StarFive JHB100 681 SoC. 682 683 If you don't know what to do here, say Y. 684 685config ACLINT_SSWI 686 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 687 depends on RISCV 688 depends on SMP 689 select IRQ_DOMAIN_HIERARCHY 690 select GENERIC_IRQ_IPI_MUX 691 help 692 This enables support for variants of the RISC-V ACLINT-SSWI device. 693 Supported variants are: 694 - T-HEAD, with compatible "thead,c900-aclint-sswi" 695 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 696 697 If you don't know what to do here, say Y. 698 699# Backwards compatibility so oldconfig does not drop it. 700config THEAD_C900_ACLINT_SSWI 701 bool 702 select ACLINT_SSWI 703 704config EXYNOS_IRQ_COMBINER 705 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 706 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 707 help 708 Say yes here to add support for the IRQ combiner devices embedded 709 in Samsung Exynos chips. 710 711config IRQ_LOONGARCH_CPU 712 bool 713 select GENERIC_IRQ_CHIP 714 select IRQ_DOMAIN 715 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 716 select LOONGSON_HTVEC 717 select LOONGSON_LIOINTC 718 select LOONGSON_EIOINTC 719 select LOONGSON_PCH_PIC 720 select LOONGSON_PCH_MSI 721 select LOONGSON_PCH_LPC 722 help 723 Support for the LoongArch CPU Interrupt Controller. For details of 724 irq chip hierarchy on LoongArch platforms please read the document 725 Documentation/arch/loongarch/irq-chip-model.rst. 726 727config LOONGSON_LIOINTC 728 bool "Loongson Local I/O Interrupt Controller" 729 depends on MACH_LOONGSON64 || LOONGARCH 730 default y 731 select IRQ_DOMAIN 732 select GENERIC_IRQ_CHIP 733 help 734 Support for the Loongson Local I/O Interrupt Controller. 735 736config LOONGSON_EIOINTC 737 bool "Loongson Extend I/O Interrupt Controller" 738 depends on LOONGARCH 739 default MACH_LOONGSON64 740 select IRQ_DOMAIN_HIERARCHY 741 select GENERIC_IRQ_CHIP 742 help 743 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 744 745config LOONGSON_HTPIC 746 bool "Loongson3 HyperTransport PIC Controller" 747 depends on MACH_LOONGSON64 && MIPS 748 default y 749 select IRQ_DOMAIN 750 select GENERIC_IRQ_CHIP 751 help 752 Support for the Loongson-3 HyperTransport PIC Controller. 753 754config LOONGSON_HTVEC 755 bool "Loongson HyperTransport Interrupt Vector Controller" 756 depends on MACH_LOONGSON64 || LOONGARCH 757 default MACH_LOONGSON64 758 select IRQ_DOMAIN_HIERARCHY 759 help 760 Support for the Loongson HyperTransport Interrupt Vector Controller. 761 762config LOONGSON_PCH_PIC 763 bool "Loongson PCH PIC Controller" 764 depends on MACH_LOONGSON64 || LOONGARCH 765 default MACH_LOONGSON64 766 select IRQ_DOMAIN_HIERARCHY 767 select IRQ_FASTEOI_HIERARCHY_HANDLERS 768 help 769 Support for the Loongson PCH PIC Controller. 770 771config LOONGSON_PCH_MSI 772 bool "Loongson PCH MSI Controller" 773 depends on MACH_LOONGSON64 || LOONGARCH 774 depends on PCI 775 default MACH_LOONGSON64 776 select IRQ_DOMAIN_HIERARCHY 777 select IRQ_MSI_LIB 778 select PCI_MSI 779 help 780 Support for the Loongson PCH MSI Controller. 781 782config LOONGSON_PCH_LPC 783 bool "Loongson PCH LPC Controller" 784 depends on MACH_LOONGSON64 || LOONGARCH 785 default MACH_LOONGSON64 786 select IRQ_DOMAIN_HIERARCHY 787 help 788 Support for the Loongson PCH LPC Controller. 789 790config MST_IRQ 791 bool "MStar Interrupt Controller" 792 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 793 default ARCH_MEDIATEK 794 select IRQ_DOMAIN 795 select IRQ_DOMAIN_HIERARCHY 796 help 797 Support MStar Interrupt Controller. 798 799config WPCM450_AIC 800 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 801 depends on ARCH_WPCM450 802 help 803 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 804 805config IRQ_IDT3243X 806 bool 807 select GENERIC_IRQ_CHIP 808 select IRQ_DOMAIN 809 810config APPLE_AIC 811 bool "Apple Interrupt Controller (AIC)" 812 depends on ARM64 813 depends on ARCH_APPLE || COMPILE_TEST 814 select GENERIC_IRQ_IPI_MUX 815 help 816 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 817 such as the M1. 818 819config MCHP_EIC 820 bool "Microchip External Interrupt Controller" 821 depends on ARCH_AT91 || COMPILE_TEST 822 select IRQ_DOMAIN 823 select IRQ_DOMAIN_HIERARCHY 824 help 825 Support for Microchip External Interrupt Controller. 826 827config SOPHGO_SG2042_MSI 828 bool "Sophgo SG2042 MSI Controller" 829 depends on ARCH_SOPHGO || COMPILE_TEST 830 depends on PCI 831 select IRQ_DOMAIN_HIERARCHY 832 select IRQ_MSI_LIB 833 select PCI_MSI 834 help 835 Support for the Sophgo SG2042 MSI Controller. 836 This on-chip interrupt controller enables MSI sources to be 837 routed to the primary PLIC controller on SoC. 838 839config SUNPLUS_SP7021_INTC 840 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 841 default SOC_SP7021 842 help 843 Support for the Sunplus SP7021 Interrupt Controller IP core. 844 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 845 chained controller, routing all interrupt source in P-Chip to 846 the primary controller on C-Chip. 847 848endmenu 849