1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 18config ARM_GIC_MAX_NR 19 int 20 depends on ARM_GIC 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 38 39config ARM_GIC_V3_ITS 40 bool 41 select GENERIC_MSI_IRQ_DOMAIN 42 default ARM_GIC_V3 43 44config ARM_GIC_V3_ITS_PCI 45 bool 46 depends on ARM_GIC_V3_ITS 47 depends on PCI 48 depends on PCI_MSI 49 default ARM_GIC_V3_ITS 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF || COMPILE_TEST 90 select GENERIC_IRQ_CHIP 91 select IRQ_DOMAIN 92 help 93 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 94 95config ATMEL_AIC_IRQ 96 bool 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 select SPARSE_IRQ 100 101config ATMEL_AIC5_IRQ 102 bool 103 select GENERIC_IRQ_CHIP 104 select IRQ_DOMAIN 105 select SPARSE_IRQ 106 107config I8259 108 bool 109 select IRQ_DOMAIN 110 111config BCM6345_L1_IRQ 112 bool 113 select GENERIC_IRQ_CHIP 114 select IRQ_DOMAIN 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 116 117config BCM7038_L1_IRQ 118 bool 119 select GENERIC_IRQ_CHIP 120 select IRQ_DOMAIN 121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 122 123config BCM7120_L2_IRQ 124 bool 125 select GENERIC_IRQ_CHIP 126 select IRQ_DOMAIN 127 128config BRCMSTB_L2_IRQ 129 bool 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config DAVINCI_AINTC 134 bool 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN 137 138config DAVINCI_CP_INTC 139 bool 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DW_APB_ICTL 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN_HIERARCHY 147 148config FARADAY_FTINTC010 149 bool 150 select IRQ_DOMAIN 151 select SPARSE_IRQ 152 153config HISILICON_IRQ_MBIGEN 154 bool 155 select ARM_GIC_V3 156 select ARM_GIC_V3_ITS 157 158config IMGPDC_IRQ 159 bool 160 select GENERIC_IRQ_CHIP 161 select IRQ_DOMAIN 162 163config IXP4XX_IRQ 164 bool 165 select IRQ_DOMAIN 166 select SPARSE_IRQ 167 168config MADERA_IRQ 169 tristate 170 171config IRQ_MIPS_CPU 172 bool 173 select GENERIC_IRQ_CHIP 174 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 175 select IRQ_DOMAIN 176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 177 178config CLPS711X_IRQCHIP 179 bool 180 depends on ARCH_CLPS711X 181 select IRQ_DOMAIN 182 select SPARSE_IRQ 183 default y 184 185config OMPIC 186 bool 187 188config OR1K_PIC 189 bool 190 select IRQ_DOMAIN 191 192config OMAP_IRQCHIP 193 bool 194 select GENERIC_IRQ_CHIP 195 select IRQ_DOMAIN 196 197config ORION_IRQCHIP 198 bool 199 select IRQ_DOMAIN 200 201config PIC32_EVIC 202 bool 203 select GENERIC_IRQ_CHIP 204 select IRQ_DOMAIN 205 206config JCORE_AIC 207 bool "J-Core integrated AIC" if COMPILE_TEST 208 depends on OF 209 select IRQ_DOMAIN 210 help 211 Support for the J-Core integrated AIC. 212 213config RDA_INTC 214 bool 215 select IRQ_DOMAIN 216 217config RENESAS_INTC_IRQPIN 218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 219 select IRQ_DOMAIN 220 help 221 Enable support for the Renesas Interrupt Controller for external 222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 223 224config RENESAS_IRQC 225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 226 select GENERIC_IRQ_CHIP 227 select IRQ_DOMAIN 228 help 229 Enable support for the Renesas Interrupt Controller for external 230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 231 232config RENESAS_RZA1_IRQC 233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 234 select IRQ_DOMAIN_HIERARCHY 235 help 236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 237 to 8 external interrupts with configurable sense select. 238 239config SL28CPLD_INTC 240 bool "Kontron sl28cpld IRQ controller" 241 depends on MFD_SL28CPLD=y || COMPILE_TEST 242 select REGMAP_IRQ 243 help 244 Interrupt controller driver for the board management controller 245 found on the Kontron sl28 CPLD. 246 247config ST_IRQCHIP 248 bool 249 select REGMAP 250 select MFD_SYSCON 251 help 252 Enables SysCfg Controlled IRQs on STi based platforms. 253 254config TB10X_IRQC 255 bool 256 select IRQ_DOMAIN 257 select GENERIC_IRQ_CHIP 258 259config TS4800_IRQ 260 tristate "TS-4800 IRQ controller" 261 select IRQ_DOMAIN 262 depends on HAS_IOMEM 263 depends on SOC_IMX51 || COMPILE_TEST 264 help 265 Support for the TS-4800 FPGA IRQ controller 266 267config VERSATILE_FPGA_IRQ 268 bool 269 select IRQ_DOMAIN 270 271config VERSATILE_FPGA_IRQ_NR 272 int 273 default 4 274 depends on VERSATILE_FPGA_IRQ 275 276config XTENSA_MX 277 bool 278 select IRQ_DOMAIN 279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 280 281config XILINX_INTC 282 bool 283 select IRQ_DOMAIN 284 285config IRQ_CROSSBAR 286 bool 287 help 288 Support for a CROSSBAR ip that precedes the main interrupt controller. 289 The primary irqchip invokes the crossbar's callback which inturn allocates 290 a free irq and configures the IP. Thus the peripheral interrupts are 291 routed to one of the free irqchip interrupt lines. 292 293config KEYSTONE_IRQ 294 tristate "Keystone 2 IRQ controller IP" 295 depends on ARCH_KEYSTONE 296 help 297 Support for Texas Instruments Keystone 2 IRQ controller IP which 298 is part of the Keystone 2 IPC mechanism 299 300config MIPS_GIC 301 bool 302 select GENERIC_IRQ_IPI 303 select MIPS_CM 304 305config INGENIC_IRQ 306 bool 307 depends on MACH_INGENIC 308 default y 309 310config INGENIC_TCU_IRQ 311 bool "Ingenic JZ47xx TCU interrupt controller" 312 default MACH_INGENIC 313 depends on MIPS || COMPILE_TEST 314 select MFD_SYSCON 315 select GENERIC_IRQ_CHIP 316 help 317 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 318 JZ47xx SoCs. 319 320 If unsure, say N. 321 322config RENESAS_H8300H_INTC 323 bool 324 select IRQ_DOMAIN 325 326config RENESAS_H8S_INTC 327 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 328 select IRQ_DOMAIN 329 help 330 Enable support for the Renesas H8/300 Interrupt Controller, as found 331 on Renesas H8S SoCs. 332 333config IMX_GPCV2 334 bool 335 select IRQ_DOMAIN 336 help 337 Enables the wakeup IRQs for IMX platforms with GPCv2 block 338 339config IRQ_MXS 340 def_bool y if MACH_ASM9260 || ARCH_MXS 341 select IRQ_DOMAIN 342 select STMP_DEVICE 343 344config MSCC_OCELOT_IRQ 345 bool 346 select IRQ_DOMAIN 347 select GENERIC_IRQ_CHIP 348 349config MVEBU_GICP 350 bool 351 352config MVEBU_ICU 353 bool 354 355config MVEBU_ODMI 356 bool 357 select GENERIC_MSI_IRQ_DOMAIN 358 359config MVEBU_PIC 360 bool 361 362config MVEBU_SEI 363 bool 364 365config LS_EXTIRQ 366 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 367 select MFD_SYSCON 368 369config LS_SCFG_MSI 370 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 371 depends on PCI && PCI_MSI 372 373config PARTITION_PERCPU 374 bool 375 376config STM32_EXTI 377 bool 378 select IRQ_DOMAIN 379 select GENERIC_IRQ_CHIP 380 381config QCOM_IRQ_COMBINER 382 bool "QCOM IRQ combiner support" 383 depends on ARCH_QCOM && ACPI 384 select IRQ_DOMAIN_HIERARCHY 385 help 386 Say yes here to add support for the IRQ combiner devices embedded 387 in Qualcomm Technologies chips. 388 389config IRQ_UNIPHIER_AIDET 390 bool "UniPhier AIDET support" if COMPILE_TEST 391 depends on ARCH_UNIPHIER || COMPILE_TEST 392 default ARCH_UNIPHIER 393 select IRQ_DOMAIN_HIERARCHY 394 help 395 Support for the UniPhier AIDET (ARM Interrupt Detector). 396 397config MESON_IRQ_GPIO 398 bool "Meson GPIO Interrupt Multiplexer" 399 depends on ARCH_MESON 400 select IRQ_DOMAIN_HIERARCHY 401 help 402 Support Meson SoC Family GPIO Interrupt Multiplexer 403 404config GOLDFISH_PIC 405 bool "Goldfish programmable interrupt controller" 406 depends on MIPS && (GOLDFISH || COMPILE_TEST) 407 select IRQ_DOMAIN 408 help 409 Say yes here to enable Goldfish interrupt controller driver used 410 for Goldfish based virtual platforms. 411 412config QCOM_PDC 413 bool "QCOM PDC" 414 depends on ARCH_QCOM 415 select IRQ_DOMAIN_HIERARCHY 416 help 417 Power Domain Controller driver to manage and configure wakeup 418 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 419 420config CSKY_MPINTC 421 bool 422 depends on CSKY 423 help 424 Say yes here to enable C-SKY SMP interrupt controller driver used 425 for C-SKY SMP system. 426 In fact it's not mmio map in hardware and it uses ld/st to visit the 427 controller's register inside CPU. 428 429config CSKY_APB_INTC 430 bool "C-SKY APB Interrupt Controller" 431 depends on CSKY 432 help 433 Say yes here to enable C-SKY APB interrupt controller driver used 434 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 435 the controller's register. 436 437config IMX_IRQSTEER 438 bool "i.MX IRQSTEER support" 439 depends on ARCH_MXC || COMPILE_TEST 440 default ARCH_MXC 441 select IRQ_DOMAIN 442 help 443 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 444 445config IMX_INTMUX 446 bool "i.MX INTMUX support" if COMPILE_TEST 447 default y if ARCH_MXC 448 select IRQ_DOMAIN 449 help 450 Support for the i.MX INTMUX interrupt multiplexer. 451 452config LS1X_IRQ 453 bool "Loongson-1 Interrupt Controller" 454 depends on MACH_LOONGSON32 455 default y 456 select IRQ_DOMAIN 457 select GENERIC_IRQ_CHIP 458 help 459 Support for the Loongson-1 platform Interrupt Controller. 460 461config TI_SCI_INTR_IRQCHIP 462 bool 463 depends on TI_SCI_PROTOCOL 464 select IRQ_DOMAIN_HIERARCHY 465 help 466 This enables the irqchip driver support for K3 Interrupt router 467 over TI System Control Interface available on some new TI's SoCs. 468 If you wish to use interrupt router irq resources managed by the 469 TI System Controller, say Y here. Otherwise, say N. 470 471config TI_SCI_INTA_IRQCHIP 472 bool 473 depends on TI_SCI_PROTOCOL 474 select IRQ_DOMAIN_HIERARCHY 475 select TI_SCI_INTA_MSI_DOMAIN 476 help 477 This enables the irqchip driver support for K3 Interrupt aggregator 478 over TI System Control Interface available on some new TI's SoCs. 479 If you wish to use interrupt aggregator irq resources managed by the 480 TI System Controller, say Y here. Otherwise, say N. 481 482config TI_PRUSS_INTC 483 tristate 484 depends on TI_PRUSS 485 default TI_PRUSS 486 select IRQ_DOMAIN 487 help 488 This enables support for the PRU-ICSS Local Interrupt Controller 489 present within a PRU-ICSS subsystem present on various TI SoCs. 490 The PRUSS INTC enables various interrupts to be routed to multiple 491 different processors within the SoC. 492 493config RISCV_INTC 494 bool "RISC-V Local Interrupt Controller" 495 depends on RISCV 496 default y 497 help 498 This enables support for the per-HART local interrupt controller 499 found in standard RISC-V systems. The per-HART local interrupt 500 controller handles timer interrupts, software interrupts, and 501 hardware interrupts. Without a per-HART local interrupt controller, 502 a RISC-V system will be unable to handle any interrupts. 503 504 If you don't know what to do here, say Y. 505 506config SIFIVE_PLIC 507 bool "SiFive Platform-Level Interrupt Controller" 508 depends on RISCV 509 select IRQ_DOMAIN_HIERARCHY 510 help 511 This enables support for the PLIC chip found in SiFive (and 512 potentially other) RISC-V systems. The PLIC controls devices 513 interrupts and connects them to each core's local interrupt 514 controller. Aside from timer and software interrupts, all other 515 interrupt sources are subordinate to the PLIC. 516 517 If you don't know what to do here, say Y. 518 519config EXYNOS_IRQ_COMBINER 520 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 521 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 522 help 523 Say yes here to add support for the IRQ combiner devices embedded 524 in Samsung Exynos chips. 525 526config LOONGSON_LIOINTC 527 bool "Loongson Local I/O Interrupt Controller" 528 depends on MACH_LOONGSON64 529 default y 530 select IRQ_DOMAIN 531 select GENERIC_IRQ_CHIP 532 help 533 Support for the Loongson Local I/O Interrupt Controller. 534 535config LOONGSON_HTPIC 536 bool "Loongson3 HyperTransport PIC Controller" 537 depends on MACH_LOONGSON64 538 default y 539 select IRQ_DOMAIN 540 select GENERIC_IRQ_CHIP 541 help 542 Support for the Loongson-3 HyperTransport PIC Controller. 543 544config LOONGSON_HTVEC 545 bool "Loongson3 HyperTransport Interrupt Vector Controller" 546 depends on MACH_LOONGSON64 547 default MACH_LOONGSON64 548 select IRQ_DOMAIN_HIERARCHY 549 help 550 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 551 552config LOONGSON_PCH_PIC 553 bool "Loongson PCH PIC Controller" 554 depends on MACH_LOONGSON64 || COMPILE_TEST 555 default MACH_LOONGSON64 556 select IRQ_DOMAIN_HIERARCHY 557 select IRQ_FASTEOI_HIERARCHY_HANDLERS 558 help 559 Support for the Loongson PCH PIC Controller. 560 561config LOONGSON_PCH_MSI 562 bool "Loongson PCH MSI Controller" 563 depends on MACH_LOONGSON64 || COMPILE_TEST 564 depends on PCI 565 default MACH_LOONGSON64 566 select IRQ_DOMAIN_HIERARCHY 567 select PCI_MSI 568 help 569 Support for the Loongson PCH MSI Controller. 570 571config MST_IRQ 572 bool "MStar Interrupt Controller" 573 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 574 default ARCH_MEDIATEK 575 select IRQ_DOMAIN 576 select IRQ_DOMAIN_HIERARCHY 577 help 578 Support MStar Interrupt Controller. 579 580endmenu 581