1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 32config GIC_NON_BANKED 33 bool 34 35config ARM_GIC_V3 36 bool 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ 45 select IRQ_MSI_LIB 46 default ARM_GIC_V3 47 48config ARM_GIC_V3_ITS_PCI 49 bool 50 depends on ARM_GIC_V3_ITS 51 depends on PCI 52 depends on PCI_MSI 53 default ARM_GIC_V3_ITS 54 55config ARM_GIC_V3_ITS_FSL_MC 56 bool 57 depends on ARM_GIC_V3_ITS 58 depends on FSL_MC_BUS 59 default ARM_GIC_V3_ITS 60 61config ARM_NVIC 62 bool 63 select IRQ_DOMAIN_HIERARCHY 64 select GENERIC_IRQ_CHIP 65 66config ARM_VIC 67 bool 68 select IRQ_DOMAIN 69 70config ARM_VIC_NR 71 int 72 default 4 if ARCH_S5PV210 73 default 2 74 depends on ARM_VIC 75 help 76 The maximum number of VICs available in the system, for 77 power management. 78 79config IRQ_MSI_LIB 80 bool 81 82config ARMADA_370_XP_IRQ 83 bool 84 select GENERIC_IRQ_CHIP 85 select PCI_MSI if PCI 86 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 87 88config ALPINE_MSI 89 bool 90 depends on PCI 91 select PCI_MSI 92 select GENERIC_IRQ_CHIP 93 94config AL_FIC 95 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 96 depends on OF 97 depends on HAS_IOMEM 98 select GENERIC_IRQ_CHIP 99 select IRQ_DOMAIN 100 help 101 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 102 103config ATMEL_AIC_IRQ 104 bool 105 select GENERIC_IRQ_CHIP 106 select IRQ_DOMAIN 107 select SPARSE_IRQ 108 109config ATMEL_AIC5_IRQ 110 bool 111 select GENERIC_IRQ_CHIP 112 select IRQ_DOMAIN 113 select SPARSE_IRQ 114 115config I8259 116 bool 117 select IRQ_DOMAIN 118 119config BCM6345_L1_IRQ 120 bool 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 124 125config BCM7038_L1_IRQ 126 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 127 depends on ARCH_BRCMSTB || BMIPS_GENERIC 128 default ARCH_BRCMSTB || BMIPS_GENERIC 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 132 133config BCM7120_L2_IRQ 134 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 135 depends on ARCH_BRCMSTB || BMIPS_GENERIC 136 default ARCH_BRCMSTB || BMIPS_GENERIC 137 select GENERIC_IRQ_CHIP 138 select IRQ_DOMAIN 139 140config BRCMSTB_L2_IRQ 141 tristate "Broadcom STB generic L2 interrupt controller driver" 142 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 143 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 144 select GENERIC_IRQ_CHIP 145 select IRQ_DOMAIN 146 147config DAVINCI_CP_INTC 148 bool 149 select GENERIC_IRQ_CHIP 150 select IRQ_DOMAIN 151 152config DW_APB_ICTL 153 bool 154 select GENERIC_IRQ_CHIP 155 select IRQ_DOMAIN_HIERARCHY 156 157config FARADAY_FTINTC010 158 bool 159 select IRQ_DOMAIN 160 select SPARSE_IRQ 161 162config HISILICON_IRQ_MBIGEN 163 bool 164 select ARM_GIC_V3 165 select ARM_GIC_V3_ITS 166 167config IMGPDC_IRQ 168 bool 169 select GENERIC_IRQ_CHIP 170 select IRQ_DOMAIN 171 172config IXP4XX_IRQ 173 bool 174 select IRQ_DOMAIN 175 select SPARSE_IRQ 176 177config LAN966X_OIC 178 tristate "Microchip LAN966x OIC Support" 179 select GENERIC_IRQ_CHIP 180 select IRQ_DOMAIN 181 help 182 Enable support for the LAN966x Outbound Interrupt Controller. 183 This controller is present on the Microchip LAN966x PCI device and 184 maps the internal interrupts sources to PCIe interrupt. 185 186 To compile this driver as a module, choose M here: the module 187 will be called irq-lan966x-oic. 188 189config MADERA_IRQ 190 tristate 191 192config IRQ_MIPS_CPU 193 bool 194 select GENERIC_IRQ_CHIP 195 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 196 select IRQ_DOMAIN 197 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 198 199config CLPS711X_IRQCHIP 200 bool 201 depends on ARCH_CLPS711X 202 select IRQ_DOMAIN 203 select SPARSE_IRQ 204 default y 205 206config OMPIC 207 bool 208 209config OR1K_PIC 210 bool 211 select IRQ_DOMAIN 212 213config OMAP_IRQCHIP 214 bool 215 select GENERIC_IRQ_CHIP 216 select IRQ_DOMAIN 217 218config ORION_IRQCHIP 219 bool 220 select IRQ_DOMAIN 221 222config PIC32_EVIC 223 bool 224 select GENERIC_IRQ_CHIP 225 select IRQ_DOMAIN 226 227config JCORE_AIC 228 bool "J-Core integrated AIC" if COMPILE_TEST 229 depends on OF 230 select IRQ_DOMAIN 231 help 232 Support for the J-Core integrated AIC. 233 234config RDA_INTC 235 bool 236 select IRQ_DOMAIN 237 238config RENESAS_INTC_IRQPIN 239 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 240 select IRQ_DOMAIN 241 help 242 Enable support for the Renesas Interrupt Controller for external 243 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 244 245config RENESAS_IRQC 246 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 247 select GENERIC_IRQ_CHIP 248 select IRQ_DOMAIN 249 help 250 Enable support for the Renesas Interrupt Controller for external 251 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 252 253config RENESAS_RZA1_IRQC 254 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 255 select IRQ_DOMAIN_HIERARCHY 256 help 257 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 258 to 8 external interrupts with configurable sense select. 259 260config RENESAS_RZG2L_IRQC 261 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 262 select GENERIC_IRQ_CHIP 263 select IRQ_DOMAIN_HIERARCHY 264 help 265 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 266 for external devices. 267 268config SL28CPLD_INTC 269 bool "Kontron sl28cpld IRQ controller" 270 depends on MFD_SL28CPLD=y || COMPILE_TEST 271 select REGMAP_IRQ 272 help 273 Interrupt controller driver for the board management controller 274 found on the Kontron sl28 CPLD. 275 276config ST_IRQCHIP 277 bool 278 select REGMAP 279 select MFD_SYSCON 280 help 281 Enables SysCfg Controlled IRQs on STi based platforms. 282 283config SUN4I_INTC 284 bool 285 286config SUN6I_R_INTC 287 bool 288 select IRQ_DOMAIN_HIERARCHY 289 select IRQ_FASTEOI_HIERARCHY_HANDLERS 290 291config SUNXI_NMI_INTC 292 bool 293 select GENERIC_IRQ_CHIP 294 295config TB10X_IRQC 296 bool 297 select IRQ_DOMAIN 298 select GENERIC_IRQ_CHIP 299 300config TS4800_IRQ 301 tristate "TS-4800 IRQ controller" 302 select IRQ_DOMAIN 303 depends on HAS_IOMEM 304 depends on SOC_IMX51 || COMPILE_TEST 305 help 306 Support for the TS-4800 FPGA IRQ controller 307 308config VERSATILE_FPGA_IRQ 309 bool 310 select IRQ_DOMAIN 311 312config VERSATILE_FPGA_IRQ_NR 313 int 314 default 4 315 depends on VERSATILE_FPGA_IRQ 316 317config XTENSA_MX 318 bool 319 select IRQ_DOMAIN 320 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 321 322config XILINX_INTC 323 bool "Xilinx Interrupt Controller IP" 324 depends on OF_ADDRESS 325 select IRQ_DOMAIN 326 help 327 Support for the Xilinx Interrupt Controller IP core. 328 This is used as a primary controller with MicroBlaze and can also 329 be used as a secondary chained controller on other platforms. 330 331config IRQ_CROSSBAR 332 bool 333 help 334 Support for a CROSSBAR ip that precedes the main interrupt controller. 335 The primary irqchip invokes the crossbar's callback which inturn allocates 336 a free irq and configures the IP. Thus the peripheral interrupts are 337 routed to one of the free irqchip interrupt lines. 338 339config KEYSTONE_IRQ 340 tristate "Keystone 2 IRQ controller IP" 341 depends on ARCH_KEYSTONE 342 help 343 Support for Texas Instruments Keystone 2 IRQ controller IP which 344 is part of the Keystone 2 IPC mechanism 345 346config MIPS_GIC 347 bool 348 select GENERIC_IRQ_IPI if SMP 349 select IRQ_DOMAIN_HIERARCHY 350 select MIPS_CM 351 352config INGENIC_IRQ 353 bool 354 depends on MACH_INGENIC 355 default y 356 357config INGENIC_TCU_IRQ 358 bool "Ingenic JZ47xx TCU interrupt controller" 359 default MACH_INGENIC 360 depends on MIPS || COMPILE_TEST 361 select MFD_SYSCON 362 select GENERIC_IRQ_CHIP 363 help 364 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 365 JZ47xx SoCs. 366 367 If unsure, say N. 368 369config IMX_GPCV2 370 bool 371 select IRQ_DOMAIN 372 help 373 Enables the wakeup IRQs for IMX platforms with GPCv2 block 374 375config IRQ_MXS 376 def_bool y if MACH_ASM9260 || ARCH_MXS 377 select IRQ_DOMAIN 378 select STMP_DEVICE 379 380config MSCC_OCELOT_IRQ 381 bool 382 select IRQ_DOMAIN 383 select GENERIC_IRQ_CHIP 384 385config MVEBU_GICP 386 select IRQ_MSI_LIB 387 bool 388 389config MVEBU_ICU 390 bool 391 392config MVEBU_ODMI 393 bool 394 select IRQ_MSI_LIB 395 select GENERIC_MSI_IRQ 396 397config MVEBU_PIC 398 bool 399 400config MVEBU_SEI 401 bool 402 403config LS_EXTIRQ 404 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 405 select MFD_SYSCON 406 407config LS_SCFG_MSI 408 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 409 depends on PCI_MSI 410 411config PARTITION_PERCPU 412 bool 413 414config STM32MP_EXTI 415 tristate "STM32MP extended interrupts and event controller" 416 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 417 default y 418 select IRQ_DOMAIN_HIERARCHY 419 select GENERIC_IRQ_CHIP 420 help 421 Support STM32MP EXTI (extended interrupts and event) controller. 422 423config STM32_EXTI 424 bool 425 select IRQ_DOMAIN 426 select GENERIC_IRQ_CHIP 427 428config QCOM_IRQ_COMBINER 429 bool "QCOM IRQ combiner support" 430 depends on ARCH_QCOM && ACPI 431 select IRQ_DOMAIN_HIERARCHY 432 help 433 Say yes here to add support for the IRQ combiner devices embedded 434 in Qualcomm Technologies chips. 435 436config IRQ_UNIPHIER_AIDET 437 bool "UniPhier AIDET support" if COMPILE_TEST 438 depends on ARCH_UNIPHIER || COMPILE_TEST 439 default ARCH_UNIPHIER 440 select IRQ_DOMAIN_HIERARCHY 441 help 442 Support for the UniPhier AIDET (ARM Interrupt Detector). 443 444config MESON_IRQ_GPIO 445 tristate "Meson GPIO Interrupt Multiplexer" 446 depends on ARCH_MESON || COMPILE_TEST 447 default ARCH_MESON 448 select IRQ_DOMAIN_HIERARCHY 449 help 450 Support Meson SoC Family GPIO Interrupt Multiplexer 451 452config GOLDFISH_PIC 453 bool "Goldfish programmable interrupt controller" 454 depends on MIPS && (GOLDFISH || COMPILE_TEST) 455 select GENERIC_IRQ_CHIP 456 select IRQ_DOMAIN 457 help 458 Say yes here to enable Goldfish interrupt controller driver used 459 for Goldfish based virtual platforms. 460 461config QCOM_PDC 462 tristate "QCOM PDC" 463 depends on ARCH_QCOM 464 select IRQ_DOMAIN_HIERARCHY 465 help 466 Power Domain Controller driver to manage and configure wakeup 467 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 468 469config QCOM_MPM 470 tristate "QCOM MPM" 471 depends on ARCH_QCOM 472 depends on MAILBOX 473 select IRQ_DOMAIN_HIERARCHY 474 help 475 MSM Power Manager driver to manage and configure wakeup 476 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 477 478config CSKY_MPINTC 479 bool 480 depends on CSKY 481 help 482 Say yes here to enable C-SKY SMP interrupt controller driver used 483 for C-SKY SMP system. 484 In fact it's not mmio map in hardware and it uses ld/st to visit the 485 controller's register inside CPU. 486 487config CSKY_APB_INTC 488 bool "C-SKY APB Interrupt Controller" 489 depends on CSKY 490 help 491 Say yes here to enable C-SKY APB interrupt controller driver used 492 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 493 the controller's register. 494 495config IMX_IRQSTEER 496 bool "i.MX IRQSTEER support" 497 depends on ARCH_MXC || COMPILE_TEST 498 default ARCH_MXC 499 select IRQ_DOMAIN 500 help 501 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 502 503config IMX_INTMUX 504 bool "i.MX INTMUX support" if COMPILE_TEST 505 default y if ARCH_MXC 506 select IRQ_DOMAIN 507 help 508 Support for the i.MX INTMUX interrupt multiplexer. 509 510config IMX_MU_MSI 511 tristate "i.MX MU used as MSI controller" 512 depends on OF && HAS_IOMEM 513 depends on ARCH_MXC || COMPILE_TEST 514 default m if ARCH_MXC 515 select IRQ_DOMAIN 516 select IRQ_DOMAIN_HIERARCHY 517 select GENERIC_MSI_IRQ 518 select IRQ_MSI_LIB 519 help 520 Provide a driver for the i.MX Messaging Unit block used as a 521 CPU-to-CPU MSI controller. This requires a specially crafted DT 522 to make use of this driver. 523 524 If unsure, say N 525 526config LS1X_IRQ 527 bool "Loongson-1 Interrupt Controller" 528 depends on MACH_LOONGSON32 529 default y 530 select IRQ_DOMAIN 531 select GENERIC_IRQ_CHIP 532 help 533 Support for the Loongson-1 platform Interrupt Controller. 534 535config TI_SCI_INTR_IRQCHIP 536 bool 537 depends on TI_SCI_PROTOCOL 538 select IRQ_DOMAIN_HIERARCHY 539 help 540 This enables the irqchip driver support for K3 Interrupt router 541 over TI System Control Interface available on some new TI's SoCs. 542 If you wish to use interrupt router irq resources managed by the 543 TI System Controller, say Y here. Otherwise, say N. 544 545config TI_SCI_INTA_IRQCHIP 546 bool 547 depends on TI_SCI_PROTOCOL 548 select IRQ_DOMAIN_HIERARCHY 549 select TI_SCI_INTA_MSI_DOMAIN 550 help 551 This enables the irqchip driver support for K3 Interrupt aggregator 552 over TI System Control Interface available on some new TI's SoCs. 553 If you wish to use interrupt aggregator irq resources managed by the 554 TI System Controller, say Y here. Otherwise, say N. 555 556config TI_PRUSS_INTC 557 tristate 558 depends on TI_PRUSS 559 default TI_PRUSS 560 select IRQ_DOMAIN 561 help 562 This enables support for the PRU-ICSS Local Interrupt Controller 563 present within a PRU-ICSS subsystem present on various TI SoCs. 564 The PRUSS INTC enables various interrupts to be routed to multiple 565 different processors within the SoC. 566 567config RISCV_INTC 568 bool 569 depends on RISCV 570 select IRQ_DOMAIN_HIERARCHY 571 572config RISCV_APLIC 573 bool 574 depends on RISCV 575 select IRQ_DOMAIN_HIERARCHY 576 577config RISCV_APLIC_MSI 578 bool 579 depends on RISCV_APLIC 580 select GENERIC_MSI_IRQ 581 default RISCV_APLIC 582 583config RISCV_IMSIC 584 bool 585 depends on RISCV 586 select IRQ_DOMAIN_HIERARCHY 587 select GENERIC_IRQ_MATRIX_ALLOCATOR 588 select GENERIC_MSI_IRQ 589 590config RISCV_IMSIC_PCI 591 bool 592 depends on RISCV_IMSIC 593 depends on PCI 594 depends on PCI_MSI 595 default RISCV_IMSIC 596 597config SIFIVE_PLIC 598 bool 599 depends on RISCV 600 select IRQ_DOMAIN_HIERARCHY 601 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 602 603config STARFIVE_JH8100_INTC 604 bool "StarFive JH8100 External Interrupt Controller" 605 depends on ARCH_STARFIVE || COMPILE_TEST 606 default ARCH_STARFIVE 607 select IRQ_DOMAIN_HIERARCHY 608 help 609 This enables support for the INTC chip found in StarFive JH8100 610 SoC. 611 612 If you don't know what to do here, say Y. 613 614config EXYNOS_IRQ_COMBINER 615 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 616 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 617 help 618 Say yes here to add support for the IRQ combiner devices embedded 619 in Samsung Exynos chips. 620 621config IRQ_LOONGARCH_CPU 622 bool 623 select GENERIC_IRQ_CHIP 624 select IRQ_DOMAIN 625 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 626 select LOONGSON_HTVEC 627 select LOONGSON_LIOINTC 628 select LOONGSON_EIOINTC 629 select LOONGSON_PCH_PIC 630 select LOONGSON_PCH_MSI 631 select LOONGSON_PCH_LPC 632 help 633 Support for the LoongArch CPU Interrupt Controller. For details of 634 irq chip hierarchy on LoongArch platforms please read the document 635 Documentation/arch/loongarch/irq-chip-model.rst. 636 637config LOONGSON_LIOINTC 638 bool "Loongson Local I/O Interrupt Controller" 639 depends on MACH_LOONGSON64 640 default y 641 select IRQ_DOMAIN 642 select GENERIC_IRQ_CHIP 643 help 644 Support for the Loongson Local I/O Interrupt Controller. 645 646config LOONGSON_EIOINTC 647 bool "Loongson Extend I/O Interrupt Controller" 648 depends on LOONGARCH 649 depends on MACH_LOONGSON64 650 default MACH_LOONGSON64 651 select IRQ_DOMAIN_HIERARCHY 652 select GENERIC_IRQ_CHIP 653 help 654 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 655 656config LOONGSON_HTPIC 657 bool "Loongson3 HyperTransport PIC Controller" 658 depends on MACH_LOONGSON64 && MIPS 659 default y 660 select IRQ_DOMAIN 661 select GENERIC_IRQ_CHIP 662 help 663 Support for the Loongson-3 HyperTransport PIC Controller. 664 665config LOONGSON_HTVEC 666 bool "Loongson HyperTransport Interrupt Vector Controller" 667 depends on MACH_LOONGSON64 668 default MACH_LOONGSON64 669 select IRQ_DOMAIN_HIERARCHY 670 help 671 Support for the Loongson HyperTransport Interrupt Vector Controller. 672 673config LOONGSON_PCH_PIC 674 bool "Loongson PCH PIC Controller" 675 depends on MACH_LOONGSON64 676 default MACH_LOONGSON64 677 select IRQ_DOMAIN_HIERARCHY 678 select IRQ_FASTEOI_HIERARCHY_HANDLERS 679 help 680 Support for the Loongson PCH PIC Controller. 681 682config LOONGSON_PCH_MSI 683 bool "Loongson PCH MSI Controller" 684 depends on MACH_LOONGSON64 685 depends on PCI 686 default MACH_LOONGSON64 687 select IRQ_DOMAIN_HIERARCHY 688 select PCI_MSI 689 help 690 Support for the Loongson PCH MSI Controller. 691 692config LOONGSON_PCH_LPC 693 bool "Loongson PCH LPC Controller" 694 depends on LOONGARCH 695 depends on MACH_LOONGSON64 696 default MACH_LOONGSON64 697 select IRQ_DOMAIN_HIERARCHY 698 help 699 Support for the Loongson PCH LPC Controller. 700 701config MST_IRQ 702 bool "MStar Interrupt Controller" 703 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 704 default ARCH_MEDIATEK 705 select IRQ_DOMAIN 706 select IRQ_DOMAIN_HIERARCHY 707 help 708 Support MStar Interrupt Controller. 709 710config WPCM450_AIC 711 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 712 depends on ARCH_WPCM450 713 help 714 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 715 716config IRQ_IDT3243X 717 bool 718 select GENERIC_IRQ_CHIP 719 select IRQ_DOMAIN 720 721config APPLE_AIC 722 bool "Apple Interrupt Controller (AIC)" 723 depends on ARM64 724 depends on ARCH_APPLE || COMPILE_TEST 725 select GENERIC_IRQ_IPI_MUX 726 help 727 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 728 such as the M1. 729 730config MCHP_EIC 731 bool "Microchip External Interrupt Controller" 732 depends on ARCH_AT91 || COMPILE_TEST 733 select IRQ_DOMAIN 734 select IRQ_DOMAIN_HIERARCHY 735 help 736 Support for Microchip External Interrupt Controller. 737 738config SUNPLUS_SP7021_INTC 739 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 740 default SOC_SP7021 741 help 742 Support for the Sunplus SP7021 Interrupt Controller IP core. 743 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 744 chained controller, routing all interrupt source in P-Chip to 745 the primary controller on C-Chip. 746 747endmenu 748