1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V3_ITS_FSL_MC 55 bool 56 depends on ARM_GIC_V3_ITS 57 depends on FSL_MC_BUS 58 default ARM_GIC_V3_ITS 59 60config ARM_GIC_V5 61 bool 62 select IRQ_DOMAIN_HIERARCHY 63 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 64 select GENERIC_MSI_IRQ 65 select IRQ_MSI_LIB 66 select ARM_GIC_ITS_PARENT 67 68config ARM_NVIC 69 bool 70 select IRQ_DOMAIN_HIERARCHY 71 select GENERIC_IRQ_CHIP 72 73config ARM_VIC 74 bool 75 select IRQ_DOMAIN 76 77config ARM_VIC_NR 78 int 79 default 4 if ARCH_S5PV210 80 default 2 81 depends on ARM_VIC 82 help 83 The maximum number of VICs available in the system, for 84 power management. 85 86config IRQ_MSI_LIB 87 bool 88 select GENERIC_MSI_IRQ 89 90config ARMADA_370_XP_IRQ 91 bool 92 select GENERIC_IRQ_CHIP 93 select PCI_MSI if PCI 94 select IRQ_MSI_LIB if PCI 95 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 96 97config ALPINE_MSI 98 bool 99 depends on PCI 100 select PCI_MSI 101 select IRQ_MSI_LIB 102 select GENERIC_IRQ_CHIP 103 104config AL_FIC 105 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 106 depends on OF 107 depends on HAS_IOMEM 108 select GENERIC_IRQ_CHIP 109 select IRQ_DOMAIN 110 help 111 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 112 113config ASPEED_AST2700_INTC 114 bool "ASPEED AST2700 Interrupt Controller support" 115 depends on OF 116 depends on ARCH_ASPEED || COMPILE_TEST 117 select IRQ_DOMAIN_HIERARCHY 118 help 119 Enable support for the ASPEED AST2700 interrupt controller. 120 This driver handles interrupt, routing and merged interrupt 121 sources to upstream parent interrupt controllers. 122 123 If unsure, say N. 124 125config ASPEED_AST2700_INTC_TEST 126 bool "Tests for the ASPEED AST2700 Interrupt Controller" 127 depends on ASPEED_AST2700_INTC && KUNIT=y 128 default KUNIT_ALL_TESTS 129 help 130 Enable KUnit tests for AST2700 INTC route resolution. 131 The tests exercise error handling and route selection paths. 132 This option is intended for test builds. 133 134 If unsure, say N. 135 136config ATMEL_AIC_IRQ 137 bool 138 select GENERIC_IRQ_CHIP 139 select IRQ_DOMAIN 140 select SPARSE_IRQ 141 142config ATMEL_AIC5_IRQ 143 bool 144 select GENERIC_IRQ_CHIP 145 select IRQ_DOMAIN 146 select SPARSE_IRQ 147 148config I8259 149 bool 150 select IRQ_DOMAIN 151 152config BCM2712_MIP 153 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 154 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 155 default m if ARCH_BRCMSTB || ARCH_BCM2835 156 depends on ARM_GIC 157 select GENERIC_IRQ_CHIP 158 select IRQ_DOMAIN_HIERARCHY 159 select GENERIC_MSI_IRQ 160 select IRQ_MSI_LIB 161 help 162 Enable support for the Broadcom BCM2712 MSI-X target peripheral 163 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 164 Raspberry Pi 5. 165 166 If unsure say n. 167 168config BCM6345_L1_IRQ 169 bool 170 select GENERIC_IRQ_CHIP 171 select IRQ_DOMAIN 172 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 173 174config BCM7038_L1_IRQ 175 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 176 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 177 default ARCH_BRCMSTB || BMIPS_GENERIC 178 select GENERIC_IRQ_CHIP 179 select IRQ_DOMAIN 180 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 181 182config BCM7120_L2_IRQ 183 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 184 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 185 default ARCH_BRCMSTB || BMIPS_GENERIC 186 select GENERIC_IRQ_CHIP 187 select IRQ_DOMAIN 188 189config BRCMSTB_L2_IRQ 190 tristate "Broadcom STB generic L2 interrupt controller driver" 191 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 192 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 193 select GENERIC_IRQ_CHIP 194 select IRQ_DOMAIN 195 196config DAVINCI_CP_INTC 197 bool 198 select GENERIC_IRQ_CHIP 199 select IRQ_DOMAIN 200 201config DW_APB_ICTL 202 bool 203 select GENERIC_IRQ_CHIP 204 select IRQ_DOMAIN_HIERARCHY 205 206config ECONET_EN751221_INTC 207 bool 208 select GENERIC_IRQ_CHIP 209 select IRQ_DOMAIN 210 211config FARADAY_FTINTC010 212 bool 213 select IRQ_DOMAIN 214 select SPARSE_IRQ 215 216config HISILICON_IRQ_MBIGEN 217 bool 218 select ARM_GIC_V3 219 select ARM_GIC_V3_ITS 220 221config IMGPDC_IRQ 222 bool 223 select GENERIC_IRQ_CHIP 224 select IRQ_DOMAIN 225 226config IXP4XX_IRQ 227 bool 228 select IRQ_DOMAIN 229 select SPARSE_IRQ 230 231config LAN966X_OIC 232 tristate "Microchip LAN966x OIC Support" 233 depends on MCHP_LAN966X_PCI || COMPILE_TEST 234 select GENERIC_IRQ_CHIP 235 select IRQ_DOMAIN 236 help 237 Enable support for the LAN966x Outbound Interrupt Controller. 238 This controller is present on the Microchip LAN966x PCI device and 239 maps the internal interrupts sources to PCIe interrupt. 240 241 To compile this driver as a module, choose M here: the module 242 will be called irq-lan966x-oic. 243 244config MADERA_IRQ 245 tristate 246 247config IRQ_MIPS_CPU 248 bool 249 select GENERIC_IRQ_CHIP 250 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 251 select IRQ_DOMAIN 252 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 253 254config CLPS711X_IRQCHIP 255 bool 256 depends on ARCH_CLPS711X 257 select IRQ_DOMAIN 258 select SPARSE_IRQ 259 default y 260 261config OMPIC 262 bool 263 264config OR1K_PIC 265 bool 266 select IRQ_DOMAIN 267 268config OMAP_IRQCHIP 269 bool 270 select GENERIC_IRQ_CHIP 271 select IRQ_DOMAIN 272 273config ORION_IRQCHIP 274 bool 275 select IRQ_DOMAIN 276 277config PIC32_EVIC 278 def_bool MACH_PIC32 || COMPILE_TEST 279 select GENERIC_IRQ_CHIP 280 select IRQ_DOMAIN 281 help 282 Enable support for the interrupt controller on the Microchip PIC32 283 family of platforms. 284 285config JCORE_AIC 286 bool "J-Core integrated AIC" if COMPILE_TEST 287 depends on OF 288 select IRQ_DOMAIN 289 help 290 Support for the J-Core integrated AIC. 291 292config RDA_INTC 293 bool 294 select IRQ_DOMAIN 295 296config RENESAS_INTC_IRQPIN 297 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 298 select IRQ_DOMAIN 299 help 300 Enable support for the Renesas Interrupt Controller for external 301 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 302 303config RENESAS_IRQC 304 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 305 select GENERIC_IRQ_CHIP 306 select IRQ_DOMAIN 307 help 308 Enable support for the Renesas Interrupt Controller for external 309 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 310 311config RENESAS_RZA1_IRQC 312 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 313 select IRQ_DOMAIN_HIERARCHY 314 help 315 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 316 to 8 external interrupts with configurable sense select. 317 318config RENESAS_RZG2L_IRQC 319 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 320 select GENERIC_IRQ_CHIP 321 select IRQ_DOMAIN_HIERARCHY 322 help 323 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 324 for external devices. 325 326config RENESAS_RZT2H_ICU 327 bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST 328 select GENERIC_IRQ_CHIP 329 select IRQ_DOMAIN_HIERARCHY 330 help 331 Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller 332 (ICU). 333 334config RENESAS_RZV2H_ICU 335 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 336 select GENERIC_IRQ_CHIP 337 select IRQ_DOMAIN_HIERARCHY 338 help 339 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 340 341config SL28CPLD_INTC 342 bool "Kontron sl28cpld IRQ controller" 343 depends on MFD_SL28CPLD=y || COMPILE_TEST 344 select REGMAP_IRQ 345 help 346 Interrupt controller driver for the board management controller 347 found on the Kontron sl28 CPLD. 348 349config ST_IRQCHIP 350 bool 351 select REGMAP 352 select MFD_SYSCON 353 help 354 Enables SysCfg Controlled IRQs on STi based platforms. 355 356config SUN4I_INTC 357 bool 358 359config SUN6I_R_INTC 360 bool 361 select IRQ_DOMAIN_HIERARCHY 362 select IRQ_FASTEOI_HIERARCHY_HANDLERS 363 364config SUNXI_NMI_INTC 365 bool 366 select GENERIC_IRQ_CHIP 367 368config TB10X_IRQC 369 bool 370 select IRQ_DOMAIN 371 select GENERIC_IRQ_CHIP 372 373config TS4800_IRQ 374 tristate "TS-4800 IRQ controller" 375 select IRQ_DOMAIN 376 depends on HAS_IOMEM 377 depends on SOC_IMX51 || COMPILE_TEST 378 help 379 Support for the TS-4800 FPGA IRQ controller 380 381config VERSATILE_FPGA_IRQ 382 bool 383 select IRQ_DOMAIN 384 385config VERSATILE_FPGA_IRQ_NR 386 int 387 default 4 388 depends on VERSATILE_FPGA_IRQ 389 390config XTENSA_MX 391 bool 392 select IRQ_DOMAIN 393 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 394 395config XILINX_INTC 396 bool "Xilinx Interrupt Controller IP" 397 depends on OF_ADDRESS 398 select IRQ_DOMAIN 399 help 400 Support for the Xilinx Interrupt Controller IP core. 401 This is used as a primary controller with MicroBlaze and can also 402 be used as a secondary chained controller on other platforms. 403 404config IRQ_CROSSBAR 405 bool 406 help 407 Support for a CROSSBAR ip that precedes the main interrupt controller. 408 The primary irqchip invokes the crossbar's callback which inturn allocates 409 a free irq and configures the IP. Thus the peripheral interrupts are 410 routed to one of the free irqchip interrupt lines. 411 412config KEYSTONE_IRQ 413 tristate "Keystone 2 IRQ controller IP" 414 depends on ARCH_KEYSTONE 415 help 416 Support for Texas Instruments Keystone 2 IRQ controller IP which 417 is part of the Keystone 2 IPC mechanism 418 419config MIPS_GIC 420 bool 421 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 422 select GENERIC_IRQ_IPI if SMP 423 select IRQ_DOMAIN_HIERARCHY 424 select MIPS_CM 425 426config INGENIC_IRQ 427 bool 428 depends on MACH_INGENIC 429 default y 430 431config INGENIC_TCU_IRQ 432 bool "Ingenic JZ47xx TCU interrupt controller" 433 default MACH_INGENIC 434 depends on MIPS || COMPILE_TEST 435 select MFD_SYSCON 436 select GENERIC_IRQ_CHIP 437 help 438 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 439 JZ47xx SoCs. 440 441 If unsure, say N. 442 443config IMX_GPCV2 444 bool 445 select IRQ_DOMAIN 446 help 447 Enables the wakeup IRQs for IMX platforms with GPCv2 block 448 449config IRQ_MXS 450 def_bool y if MACH_ASM9260 || ARCH_MXS 451 select IRQ_DOMAIN 452 select STMP_DEVICE 453 454config MSCC_OCELOT_IRQ 455 bool 456 select IRQ_DOMAIN 457 select GENERIC_IRQ_CHIP 458 459config MVEBU_GICP 460 select IRQ_MSI_LIB 461 bool 462 463config MVEBU_ICU 464 bool 465 466config MVEBU_ODMI 467 bool 468 select IRQ_MSI_LIB 469 select GENERIC_MSI_IRQ 470 471config MVEBU_PIC 472 bool 473 474config MVEBU_SEI 475 bool 476 477config LS_EXTIRQ 478 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 479 select MFD_SYSCON 480 481config LS_SCFG_MSI 482 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 483 select IRQ_MSI_IOMMU 484 depends on PCI_MSI 485 select IRQ_MSI_LIB 486 487config STM32MP_EXTI 488 tristate "STM32MP extended interrupts and event controller" 489 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 490 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 491 select IRQ_DOMAIN_HIERARCHY 492 select GENERIC_IRQ_CHIP 493 help 494 Support STM32MP EXTI (extended interrupts and event) controller. 495 496config STM32_EXTI 497 bool 498 select IRQ_DOMAIN 499 select GENERIC_IRQ_CHIP 500 501config QCOM_IRQ_COMBINER 502 bool "Qualcomm IRQ combiner support" 503 depends on ARCH_QCOM && ACPI 504 select IRQ_DOMAIN_HIERARCHY 505 help 506 Say yes here to add support for the IRQ combiner devices embedded 507 in Qualcomm Technologies chips. 508 509config IRQ_UNIPHIER_AIDET 510 bool "UniPhier AIDET support" if COMPILE_TEST 511 depends on ARCH_UNIPHIER || COMPILE_TEST 512 default ARCH_UNIPHIER 513 select IRQ_DOMAIN_HIERARCHY 514 help 515 Support for the UniPhier AIDET (ARM Interrupt Detector). 516 517config MESON_IRQ_GPIO 518 tristate "Meson GPIO Interrupt Multiplexer" 519 depends on ARCH_MESON || COMPILE_TEST 520 default ARCH_MESON 521 select IRQ_DOMAIN_HIERARCHY 522 help 523 Support Meson SoC Family GPIO Interrupt Multiplexer 524 525config GOLDFISH_PIC 526 bool "Goldfish programmable interrupt controller" 527 depends on MIPS && (GOLDFISH || COMPILE_TEST) 528 select GENERIC_IRQ_CHIP 529 select IRQ_DOMAIN 530 help 531 Say yes here to enable Goldfish interrupt controller driver used 532 for Goldfish based virtual platforms. 533 534config QCOM_PDC 535 tristate "Qualcomm PDC" 536 depends on ARCH_QCOM 537 select IRQ_DOMAIN_HIERARCHY 538 help 539 Power Domain Controller driver to manage and configure wakeup 540 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 541 542config QCOM_MPM 543 tristate "Qualcomm MPM" 544 depends on ARCH_QCOM 545 depends on MAILBOX 546 select IRQ_DOMAIN_HIERARCHY 547 help 548 MSM Power Manager driver to manage and configure wakeup 549 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 550 551config CSKY_MPINTC 552 bool 553 depends on CSKY 554 help 555 Say yes here to enable C-SKY SMP interrupt controller driver used 556 for C-SKY SMP system. 557 In fact it's not mmio map in hardware and it uses ld/st to visit the 558 controller's register inside CPU. 559 560config CSKY_APB_INTC 561 bool "C-SKY APB Interrupt Controller" 562 depends on CSKY 563 help 564 Say yes here to enable C-SKY APB interrupt controller driver used 565 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 566 the controller's register. 567 568config IMX_IRQSTEER 569 bool "i.MX IRQSTEER support" 570 depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST 571 default y if ARCH_MXC || ARCH_S32 572 select IRQ_DOMAIN 573 help 574 Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper. 575 576config IMX_INTMUX 577 bool "i.MX INTMUX support" if COMPILE_TEST 578 default y if ARCH_MXC 579 select IRQ_DOMAIN 580 help 581 Support for the i.MX INTMUX interrupt multiplexer. 582 583config IMX_MU_MSI 584 tristate "i.MX MU used as MSI controller" 585 depends on OF && HAS_IOMEM 586 depends on ARCH_MXC || COMPILE_TEST 587 depends on ARM || ARM64 588 default m if ARCH_MXC 589 select IRQ_DOMAIN 590 select IRQ_DOMAIN_HIERARCHY 591 select GENERIC_MSI_IRQ 592 select IRQ_MSI_LIB 593 help 594 Provide a driver for the i.MX Messaging Unit block used as a 595 CPU-to-CPU MSI controller. This requires a specially crafted DT 596 to make use of this driver. 597 598 If unsure, say N 599 600config LS1X_IRQ 601 bool "Loongson-1 Interrupt Controller" 602 depends on MACH_LOONGSON32 603 default y 604 select IRQ_DOMAIN 605 select GENERIC_IRQ_CHIP 606 help 607 Support for the Loongson-1 platform Interrupt Controller. 608 609config TI_SCI_INTR_IRQCHIP 610 tristate "TI SCI INTR Interrupt Controller" 611 depends on TI_SCI_PROTOCOL 612 depends on ARCH_K3 || COMPILE_TEST 613 select IRQ_DOMAIN_HIERARCHY 614 help 615 This enables the irqchip driver support for K3 Interrupt router 616 over TI System Control Interface available on some new TI's SoCs. 617 If you wish to use interrupt router irq resources managed by the 618 TI System Controller, say Y here. Otherwise, say N. 619 620config TI_SCI_INTA_IRQCHIP 621 tristate "TI SCI INTA Interrupt Controller" 622 depends on TI_SCI_PROTOCOL 623 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 624 select IRQ_DOMAIN_HIERARCHY 625 select TI_SCI_INTA_MSI_DOMAIN 626 help 627 This enables the irqchip driver support for K3 Interrupt aggregator 628 over TI System Control Interface available on some new TI's SoCs. 629 If you wish to use interrupt aggregator irq resources managed by the 630 TI System Controller, say Y here. Otherwise, say N. 631 632config TI_PRUSS_INTC 633 tristate 634 depends on TI_PRUSS 635 default TI_PRUSS 636 select IRQ_DOMAIN 637 help 638 This enables support for the PRU-ICSS Local Interrupt Controller 639 present within a PRU-ICSS subsystem present on various TI SoCs. 640 The PRUSS INTC enables various interrupts to be routed to multiple 641 different processors within the SoC. 642 643config RISCV_INTC 644 bool 645 depends on RISCV 646 select IRQ_DOMAIN_HIERARCHY 647 648config RISCV_APLIC 649 bool 650 depends on RISCV 651 select IRQ_DOMAIN_HIERARCHY 652 653config RISCV_APLIC_MSI 654 bool 655 depends on RISCV_APLIC 656 select GENERIC_MSI_IRQ 657 default RISCV_APLIC 658 659config RISCV_IMSIC 660 bool 661 depends on RISCV 662 select IRQ_DOMAIN_HIERARCHY 663 select GENERIC_IRQ_MATRIX_ALLOCATOR 664 select GENERIC_MSI_IRQ 665 select IRQ_MSI_LIB 666 667config RISCV_RPMI_SYSMSI 668 bool 669 depends on RISCV && MAILBOX 670 select IRQ_DOMAIN_HIERARCHY 671 select GENERIC_MSI_IRQ 672 default RISCV 673 674config SIFIVE_PLIC 675 bool 676 depends on RISCV 677 select IRQ_DOMAIN_HIERARCHY 678 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 679 680config STARFIVE_JHB100_INTC 681 bool "StarFive JHB100 External Interrupt Controller" 682 depends on ARCH_STARFIVE || COMPILE_TEST 683 default ARCH_STARFIVE 684 select IRQ_DOMAIN_HIERARCHY 685 help 686 This enables support for the INTC chip found in StarFive JHB100 687 SoC. 688 689 If you don't know what to do here, say Y. 690 691config ACLINT_SSWI 692 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 693 depends on RISCV 694 depends on SMP 695 select IRQ_DOMAIN_HIERARCHY 696 select GENERIC_IRQ_IPI_MUX 697 help 698 This enables support for variants of the RISC-V ACLINT-SSWI device. 699 Supported variants are: 700 - T-HEAD, with compatible "thead,c900-aclint-sswi" 701 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 702 703 If you don't know what to do here, say Y. 704 705# Backwards compatibility so oldconfig does not drop it. 706config THEAD_C900_ACLINT_SSWI 707 bool 708 select ACLINT_SSWI 709 710config EXYNOS_IRQ_COMBINER 711 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 712 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 713 help 714 Say yes here to add support for the IRQ combiner devices embedded 715 in Samsung Exynos chips. 716 717config IRQ_LOONGARCH_CPU 718 bool 719 select GENERIC_IRQ_CHIP 720 select IRQ_DOMAIN 721 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 722 select LOONGSON_HTVEC 723 select LOONGSON_LIOINTC 724 select LOONGSON_EIOINTC 725 select LOONGSON_PCH_PIC 726 select LOONGSON_PCH_MSI 727 select LOONGSON_PCH_LPC 728 help 729 Support for the LoongArch CPU Interrupt Controller. For details of 730 irq chip hierarchy on LoongArch platforms please read the document 731 Documentation/arch/loongarch/irq-chip-model.rst. 732 733config LOONGSON_LIOINTC 734 bool "Loongson Local I/O Interrupt Controller" 735 depends on MACH_LOONGSON64 || LOONGARCH 736 default y 737 select IRQ_DOMAIN 738 select GENERIC_IRQ_CHIP 739 help 740 Support for the Loongson Local I/O Interrupt Controller. 741 742config LOONGSON_EIOINTC 743 bool "Loongson Extend I/O Interrupt Controller" 744 depends on LOONGARCH 745 default MACH_LOONGSON64 746 select IRQ_DOMAIN_HIERARCHY 747 select GENERIC_IRQ_CHIP 748 help 749 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 750 751config LOONGSON_HTPIC 752 bool "Loongson3 HyperTransport PIC Controller" 753 depends on MACH_LOONGSON64 && MIPS 754 default y 755 select IRQ_DOMAIN 756 select GENERIC_IRQ_CHIP 757 help 758 Support for the Loongson-3 HyperTransport PIC Controller. 759 760config LOONGSON_HTVEC 761 bool "Loongson HyperTransport Interrupt Vector Controller" 762 depends on MACH_LOONGSON64 || LOONGARCH 763 default MACH_LOONGSON64 764 select IRQ_DOMAIN_HIERARCHY 765 help 766 Support for the Loongson HyperTransport Interrupt Vector Controller. 767 768config LOONGSON_PCH_PIC 769 bool "Loongson PCH PIC Controller" 770 depends on MACH_LOONGSON64 || LOONGARCH 771 default MACH_LOONGSON64 772 select IRQ_DOMAIN_HIERARCHY 773 select IRQ_FASTEOI_HIERARCHY_HANDLERS 774 help 775 Support for the Loongson PCH PIC Controller. 776 777config LOONGSON_PCH_MSI 778 bool "Loongson PCH MSI Controller" 779 depends on MACH_LOONGSON64 || LOONGARCH 780 depends on PCI 781 default MACH_LOONGSON64 782 select IRQ_DOMAIN_HIERARCHY 783 select IRQ_MSI_LIB 784 select PCI_MSI 785 help 786 Support for the Loongson PCH MSI Controller. 787 788config LOONGSON_PCH_LPC 789 bool "Loongson PCH LPC Controller" 790 depends on MACH_LOONGSON64 || LOONGARCH 791 default MACH_LOONGSON64 792 select IRQ_DOMAIN_HIERARCHY 793 help 794 Support for the Loongson PCH LPC Controller. 795 796config MST_IRQ 797 bool "MStar Interrupt Controller" 798 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 799 default ARCH_MEDIATEK 800 select IRQ_DOMAIN 801 select IRQ_DOMAIN_HIERARCHY 802 help 803 Support MStar Interrupt Controller. 804 805config WPCM450_AIC 806 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 807 depends on ARCH_WPCM450 808 help 809 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 810 811config IRQ_IDT3243X 812 bool 813 select GENERIC_IRQ_CHIP 814 select IRQ_DOMAIN 815 816config APPLE_AIC 817 bool "Apple Interrupt Controller (AIC)" 818 depends on ARM64 819 depends on ARCH_APPLE || COMPILE_TEST 820 select GENERIC_IRQ_IPI_MUX 821 help 822 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 823 such as the M1. 824 825config MCHP_EIC 826 bool "Microchip External Interrupt Controller" 827 depends on ARCH_AT91 || COMPILE_TEST 828 select IRQ_DOMAIN 829 select IRQ_DOMAIN_HIERARCHY 830 help 831 Support for Microchip External Interrupt Controller. 832 833config SOPHGO_SG2042_MSI 834 bool "Sophgo SG2042 MSI Controller" 835 depends on ARCH_SOPHGO || COMPILE_TEST 836 depends on PCI 837 select IRQ_DOMAIN_HIERARCHY 838 select IRQ_MSI_LIB 839 select PCI_MSI 840 help 841 Support for the Sophgo SG2042 MSI Controller. 842 This on-chip interrupt controller enables MSI sources to be 843 routed to the primary PLIC controller on SoC. 844 845config SUNPLUS_SP7021_INTC 846 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 847 default SOC_SP7021 848 help 849 Support for the Sunplus SP7021 Interrupt Controller IP core. 850 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 851 chained controller, routing all interrupt source in P-Chip to 852 the primary controller on C-Chip. 853 854endmenu 855