1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V5 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 58 select GENERIC_MSI_IRQ 59 select IRQ_MSI_LIB 60 select ARM_GIC_ITS_PARENT 61 62config ARM_NVIC 63 bool 64 select IRQ_DOMAIN_HIERARCHY 65 select GENERIC_IRQ_CHIP 66 67config ARM_VIC 68 bool 69 select IRQ_DOMAIN 70 71config ARM_VIC_NR 72 int 73 default 4 if ARCH_S5PV210 74 default 2 75 depends on ARM_VIC 76 help 77 The maximum number of VICs available in the system, for 78 power management. 79 80config IRQ_MSI_LIB 81 bool 82 select GENERIC_MSI_IRQ 83 84config ARMADA_370_XP_IRQ 85 bool 86 select GENERIC_IRQ_CHIP 87 select PCI_MSI if PCI 88 select IRQ_MSI_LIB if PCI 89 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 90 91config ALPINE_MSI 92 bool 93 depends on PCI 94 select PCI_MSI 95 select IRQ_MSI_LIB 96 select GENERIC_IRQ_CHIP 97 98config AL_FIC 99 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 100 depends on OF 101 depends on HAS_IOMEM 102 select GENERIC_IRQ_CHIP 103 select IRQ_DOMAIN 104 help 105 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 106 107config ATMEL_AIC_IRQ 108 bool 109 select GENERIC_IRQ_CHIP 110 select IRQ_DOMAIN 111 select SPARSE_IRQ 112 113config ATMEL_AIC5_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select SPARSE_IRQ 118 119config I8259 120 bool 121 select IRQ_DOMAIN 122 123config BCM2712_MIP 124 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 125 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 126 default m if ARCH_BRCMSTB || ARCH_BCM2835 127 depends on ARM_GIC 128 select GENERIC_IRQ_CHIP 129 select IRQ_DOMAIN_HIERARCHY 130 select GENERIC_MSI_IRQ 131 select IRQ_MSI_LIB 132 help 133 Enable support for the Broadcom BCM2712 MSI-X target peripheral 134 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 135 Raspberry Pi 5. 136 137 If unsure say n. 138 139config BCM6345_L1_IRQ 140 bool 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 144 145config BCM7038_L1_IRQ 146 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 147 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 148 default ARCH_BRCMSTB || BMIPS_GENERIC 149 select GENERIC_IRQ_CHIP 150 select IRQ_DOMAIN 151 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 152 153config BCM7120_L2_IRQ 154 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 155 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 156 default ARCH_BRCMSTB || BMIPS_GENERIC 157 select GENERIC_IRQ_CHIP 158 select IRQ_DOMAIN 159 160config BRCMSTB_L2_IRQ 161 tristate "Broadcom STB generic L2 interrupt controller driver" 162 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 163 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 164 select GENERIC_IRQ_CHIP 165 select IRQ_DOMAIN 166 167config DAVINCI_CP_INTC 168 bool 169 select GENERIC_IRQ_CHIP 170 select IRQ_DOMAIN 171 172config DW_APB_ICTL 173 bool 174 select GENERIC_IRQ_CHIP 175 select IRQ_DOMAIN_HIERARCHY 176 177config ECONET_EN751221_INTC 178 bool 179 select GENERIC_IRQ_CHIP 180 select IRQ_DOMAIN 181 182config FARADAY_FTINTC010 183 bool 184 select IRQ_DOMAIN 185 select SPARSE_IRQ 186 187config HISILICON_IRQ_MBIGEN 188 bool 189 select ARM_GIC_V3 190 select ARM_GIC_V3_ITS 191 192config IMGPDC_IRQ 193 bool 194 select GENERIC_IRQ_CHIP 195 select IRQ_DOMAIN 196 197config IXP4XX_IRQ 198 bool 199 select IRQ_DOMAIN 200 select SPARSE_IRQ 201 202config LAN966X_OIC 203 tristate "Microchip LAN966x OIC Support" 204 depends on MCHP_LAN966X_PCI || COMPILE_TEST 205 select GENERIC_IRQ_CHIP 206 select IRQ_DOMAIN 207 help 208 Enable support for the LAN966x Outbound Interrupt Controller. 209 This controller is present on the Microchip LAN966x PCI device and 210 maps the internal interrupts sources to PCIe interrupt. 211 212 To compile this driver as a module, choose M here: the module 213 will be called irq-lan966x-oic. 214 215config MADERA_IRQ 216 tristate 217 218config IRQ_MIPS_CPU 219 bool 220 select GENERIC_IRQ_CHIP 221 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 222 select IRQ_DOMAIN 223 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 224 225config CLPS711X_IRQCHIP 226 bool 227 depends on ARCH_CLPS711X 228 select IRQ_DOMAIN 229 select SPARSE_IRQ 230 default y 231 232config OMPIC 233 bool 234 235config OR1K_PIC 236 bool 237 select IRQ_DOMAIN 238 239config OMAP_IRQCHIP 240 bool 241 select GENERIC_IRQ_CHIP 242 select IRQ_DOMAIN 243 244config ORION_IRQCHIP 245 bool 246 select IRQ_DOMAIN 247 248config PIC32_EVIC 249 def_bool MACH_PIC32 || COMPILE_TEST 250 select GENERIC_IRQ_CHIP 251 select IRQ_DOMAIN 252 help 253 Enable support for the interrupt controller on the Microchip PIC32 254 family of platforms. 255 256config JCORE_AIC 257 bool "J-Core integrated AIC" if COMPILE_TEST 258 depends on OF 259 select IRQ_DOMAIN 260 help 261 Support for the J-Core integrated AIC. 262 263config RDA_INTC 264 bool 265 select IRQ_DOMAIN 266 267config RENESAS_INTC_IRQPIN 268 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 269 select IRQ_DOMAIN 270 help 271 Enable support for the Renesas Interrupt Controller for external 272 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 273 274config RENESAS_IRQC 275 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 276 select GENERIC_IRQ_CHIP 277 select IRQ_DOMAIN 278 help 279 Enable support for the Renesas Interrupt Controller for external 280 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 281 282config RENESAS_RZA1_IRQC 283 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 284 select IRQ_DOMAIN_HIERARCHY 285 help 286 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 287 to 8 external interrupts with configurable sense select. 288 289config RENESAS_RZG2L_IRQC 290 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 291 select GENERIC_IRQ_CHIP 292 select IRQ_DOMAIN_HIERARCHY 293 help 294 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 295 for external devices. 296 297config RENESAS_RZT2H_ICU 298 bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST 299 select GENERIC_IRQ_CHIP 300 select IRQ_DOMAIN_HIERARCHY 301 help 302 Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller 303 (ICU). 304 305config RENESAS_RZV2H_ICU 306 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 307 select GENERIC_IRQ_CHIP 308 select IRQ_DOMAIN_HIERARCHY 309 help 310 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 311 312config SL28CPLD_INTC 313 bool "Kontron sl28cpld IRQ controller" 314 depends on MFD_SL28CPLD=y || COMPILE_TEST 315 select REGMAP_IRQ 316 help 317 Interrupt controller driver for the board management controller 318 found on the Kontron sl28 CPLD. 319 320config ST_IRQCHIP 321 bool 322 select REGMAP 323 select MFD_SYSCON 324 help 325 Enables SysCfg Controlled IRQs on STi based platforms. 326 327config SUN4I_INTC 328 bool 329 330config SUN6I_R_INTC 331 bool 332 select IRQ_DOMAIN_HIERARCHY 333 select IRQ_FASTEOI_HIERARCHY_HANDLERS 334 335config SUNXI_NMI_INTC 336 bool 337 select GENERIC_IRQ_CHIP 338 339config TB10X_IRQC 340 bool 341 select IRQ_DOMAIN 342 select GENERIC_IRQ_CHIP 343 344config TS4800_IRQ 345 tristate "TS-4800 IRQ controller" 346 select IRQ_DOMAIN 347 depends on HAS_IOMEM 348 depends on SOC_IMX51 || COMPILE_TEST 349 help 350 Support for the TS-4800 FPGA IRQ controller 351 352config VERSATILE_FPGA_IRQ 353 bool 354 select IRQ_DOMAIN 355 356config VERSATILE_FPGA_IRQ_NR 357 int 358 default 4 359 depends on VERSATILE_FPGA_IRQ 360 361config XTENSA_MX 362 bool 363 select IRQ_DOMAIN 364 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 365 366config XILINX_INTC 367 bool "Xilinx Interrupt Controller IP" 368 depends on OF_ADDRESS 369 select IRQ_DOMAIN 370 help 371 Support for the Xilinx Interrupt Controller IP core. 372 This is used as a primary controller with MicroBlaze and can also 373 be used as a secondary chained controller on other platforms. 374 375config IRQ_CROSSBAR 376 bool 377 help 378 Support for a CROSSBAR ip that precedes the main interrupt controller. 379 The primary irqchip invokes the crossbar's callback which inturn allocates 380 a free irq and configures the IP. Thus the peripheral interrupts are 381 routed to one of the free irqchip interrupt lines. 382 383config KEYSTONE_IRQ 384 tristate "Keystone 2 IRQ controller IP" 385 depends on ARCH_KEYSTONE 386 help 387 Support for Texas Instruments Keystone 2 IRQ controller IP which 388 is part of the Keystone 2 IPC mechanism 389 390config MIPS_GIC 391 bool 392 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 393 select GENERIC_IRQ_IPI if SMP 394 select IRQ_DOMAIN_HIERARCHY 395 select MIPS_CM 396 397config INGENIC_IRQ 398 bool 399 depends on MACH_INGENIC 400 default y 401 402config INGENIC_TCU_IRQ 403 bool "Ingenic JZ47xx TCU interrupt controller" 404 default MACH_INGENIC 405 depends on MIPS || COMPILE_TEST 406 select MFD_SYSCON 407 select GENERIC_IRQ_CHIP 408 help 409 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 410 JZ47xx SoCs. 411 412 If unsure, say N. 413 414config IMX_GPCV2 415 bool 416 select IRQ_DOMAIN 417 help 418 Enables the wakeup IRQs for IMX platforms with GPCv2 block 419 420config IRQ_MXS 421 def_bool y if MACH_ASM9260 || ARCH_MXS 422 select IRQ_DOMAIN 423 select STMP_DEVICE 424 425config MSCC_OCELOT_IRQ 426 bool 427 select IRQ_DOMAIN 428 select GENERIC_IRQ_CHIP 429 430config MVEBU_GICP 431 select IRQ_MSI_LIB 432 bool 433 434config MVEBU_ICU 435 bool 436 437config MVEBU_ODMI 438 bool 439 select IRQ_MSI_LIB 440 select GENERIC_MSI_IRQ 441 442config MVEBU_PIC 443 bool 444 445config MVEBU_SEI 446 bool 447 448config LS_EXTIRQ 449 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 450 select MFD_SYSCON 451 452config LS_SCFG_MSI 453 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 454 select IRQ_MSI_IOMMU 455 depends on PCI_MSI 456 select IRQ_MSI_LIB 457 458config STM32MP_EXTI 459 tristate "STM32MP extended interrupts and event controller" 460 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 461 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 462 select IRQ_DOMAIN_HIERARCHY 463 select GENERIC_IRQ_CHIP 464 help 465 Support STM32MP EXTI (extended interrupts and event) controller. 466 467config STM32_EXTI 468 bool 469 select IRQ_DOMAIN 470 select GENERIC_IRQ_CHIP 471 472config QCOM_IRQ_COMBINER 473 bool "QCOM IRQ combiner support" 474 depends on ARCH_QCOM && ACPI 475 select IRQ_DOMAIN_HIERARCHY 476 help 477 Say yes here to add support for the IRQ combiner devices embedded 478 in Qualcomm Technologies chips. 479 480config IRQ_UNIPHIER_AIDET 481 bool "UniPhier AIDET support" if COMPILE_TEST 482 depends on ARCH_UNIPHIER || COMPILE_TEST 483 default ARCH_UNIPHIER 484 select IRQ_DOMAIN_HIERARCHY 485 help 486 Support for the UniPhier AIDET (ARM Interrupt Detector). 487 488config MESON_IRQ_GPIO 489 tristate "Meson GPIO Interrupt Multiplexer" 490 depends on ARCH_MESON || COMPILE_TEST 491 default ARCH_MESON 492 select IRQ_DOMAIN_HIERARCHY 493 help 494 Support Meson SoC Family GPIO Interrupt Multiplexer 495 496config GOLDFISH_PIC 497 bool "Goldfish programmable interrupt controller" 498 depends on MIPS && (GOLDFISH || COMPILE_TEST) 499 select GENERIC_IRQ_CHIP 500 select IRQ_DOMAIN 501 help 502 Say yes here to enable Goldfish interrupt controller driver used 503 for Goldfish based virtual platforms. 504 505config QCOM_PDC 506 tristate "QCOM PDC" 507 depends on ARCH_QCOM 508 select IRQ_DOMAIN_HIERARCHY 509 help 510 Power Domain Controller driver to manage and configure wakeup 511 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 512 513config QCOM_MPM 514 tristate "QCOM MPM" 515 depends on ARCH_QCOM 516 depends on MAILBOX 517 select IRQ_DOMAIN_HIERARCHY 518 help 519 MSM Power Manager driver to manage and configure wakeup 520 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 521 522config CSKY_MPINTC 523 bool 524 depends on CSKY 525 help 526 Say yes here to enable C-SKY SMP interrupt controller driver used 527 for C-SKY SMP system. 528 In fact it's not mmio map in hardware and it uses ld/st to visit the 529 controller's register inside CPU. 530 531config CSKY_APB_INTC 532 bool "C-SKY APB Interrupt Controller" 533 depends on CSKY 534 help 535 Say yes here to enable C-SKY APB interrupt controller driver used 536 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 537 the controller's register. 538 539config IMX_IRQSTEER 540 bool "i.MX IRQSTEER support" 541 depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST 542 default y if ARCH_MXC || ARCH_S32 543 select IRQ_DOMAIN 544 help 545 Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper. 546 547config IMX_INTMUX 548 bool "i.MX INTMUX support" if COMPILE_TEST 549 default y if ARCH_MXC 550 select IRQ_DOMAIN 551 help 552 Support for the i.MX INTMUX interrupt multiplexer. 553 554config IMX_MU_MSI 555 tristate "i.MX MU used as MSI controller" 556 depends on OF && HAS_IOMEM 557 depends on ARCH_MXC || COMPILE_TEST 558 depends on ARM || ARM64 559 default m if ARCH_MXC 560 select IRQ_DOMAIN 561 select IRQ_DOMAIN_HIERARCHY 562 select GENERIC_MSI_IRQ 563 select IRQ_MSI_LIB 564 help 565 Provide a driver for the i.MX Messaging Unit block used as a 566 CPU-to-CPU MSI controller. This requires a specially crafted DT 567 to make use of this driver. 568 569 If unsure, say N 570 571config LS1X_IRQ 572 bool "Loongson-1 Interrupt Controller" 573 depends on MACH_LOONGSON32 574 default y 575 select IRQ_DOMAIN 576 select GENERIC_IRQ_CHIP 577 help 578 Support for the Loongson-1 platform Interrupt Controller. 579 580config TI_SCI_INTR_IRQCHIP 581 tristate "TI SCI INTR Interrupt Controller" 582 depends on TI_SCI_PROTOCOL 583 depends on ARCH_K3 || COMPILE_TEST 584 select IRQ_DOMAIN_HIERARCHY 585 help 586 This enables the irqchip driver support for K3 Interrupt router 587 over TI System Control Interface available on some new TI's SoCs. 588 If you wish to use interrupt router irq resources managed by the 589 TI System Controller, say Y here. Otherwise, say N. 590 591config TI_SCI_INTA_IRQCHIP 592 tristate "TI SCI INTA Interrupt Controller" 593 depends on TI_SCI_PROTOCOL 594 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 595 select IRQ_DOMAIN_HIERARCHY 596 select TI_SCI_INTA_MSI_DOMAIN 597 help 598 This enables the irqchip driver support for K3 Interrupt aggregator 599 over TI System Control Interface available on some new TI's SoCs. 600 If you wish to use interrupt aggregator irq resources managed by the 601 TI System Controller, say Y here. Otherwise, say N. 602 603config TI_PRUSS_INTC 604 tristate 605 depends on TI_PRUSS 606 default TI_PRUSS 607 select IRQ_DOMAIN 608 help 609 This enables support for the PRU-ICSS Local Interrupt Controller 610 present within a PRU-ICSS subsystem present on various TI SoCs. 611 The PRUSS INTC enables various interrupts to be routed to multiple 612 different processors within the SoC. 613 614config RISCV_INTC 615 bool 616 depends on RISCV 617 select IRQ_DOMAIN_HIERARCHY 618 619config RISCV_APLIC 620 bool 621 depends on RISCV 622 select IRQ_DOMAIN_HIERARCHY 623 624config RISCV_APLIC_MSI 625 bool 626 depends on RISCV_APLIC 627 select GENERIC_MSI_IRQ 628 default RISCV_APLIC 629 630config RISCV_IMSIC 631 bool 632 depends on RISCV 633 select IRQ_DOMAIN_HIERARCHY 634 select GENERIC_IRQ_MATRIX_ALLOCATOR 635 select GENERIC_MSI_IRQ 636 select IRQ_MSI_LIB 637 638config RISCV_RPMI_SYSMSI 639 bool 640 depends on RISCV && MAILBOX 641 select IRQ_DOMAIN_HIERARCHY 642 select GENERIC_MSI_IRQ 643 default RISCV 644 645config SIFIVE_PLIC 646 bool 647 depends on RISCV 648 select IRQ_DOMAIN_HIERARCHY 649 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 650 651config STARFIVE_JH8100_INTC 652 bool "StarFive JH8100 External Interrupt Controller" 653 depends on ARCH_STARFIVE || COMPILE_TEST 654 default ARCH_STARFIVE 655 select IRQ_DOMAIN_HIERARCHY 656 help 657 This enables support for the INTC chip found in StarFive JH8100 658 SoC. 659 660 If you don't know what to do here, say Y. 661 662config ACLINT_SSWI 663 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 664 depends on RISCV 665 depends on SMP 666 select IRQ_DOMAIN_HIERARCHY 667 select GENERIC_IRQ_IPI_MUX 668 help 669 This enables support for variants of the RISC-V ACLINT-SSWI device. 670 Supported variants are: 671 - T-HEAD, with compatible "thead,c900-aclint-sswi" 672 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 673 674 If you don't know what to do here, say Y. 675 676# Backwards compatibility so oldconfig does not drop it. 677config THEAD_C900_ACLINT_SSWI 678 bool 679 select ACLINT_SSWI 680 681config EXYNOS_IRQ_COMBINER 682 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 683 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 684 help 685 Say yes here to add support for the IRQ combiner devices embedded 686 in Samsung Exynos chips. 687 688config IRQ_LOONGARCH_CPU 689 bool 690 select GENERIC_IRQ_CHIP 691 select IRQ_DOMAIN 692 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 693 select LOONGSON_HTVEC 694 select LOONGSON_LIOINTC 695 select LOONGSON_EIOINTC 696 select LOONGSON_PCH_PIC 697 select LOONGSON_PCH_MSI 698 select LOONGSON_PCH_LPC 699 help 700 Support for the LoongArch CPU Interrupt Controller. For details of 701 irq chip hierarchy on LoongArch platforms please read the document 702 Documentation/arch/loongarch/irq-chip-model.rst. 703 704config LOONGSON_LIOINTC 705 bool "Loongson Local I/O Interrupt Controller" 706 depends on MACH_LOONGSON64 || LOONGARCH 707 default y 708 select IRQ_DOMAIN 709 select GENERIC_IRQ_CHIP 710 help 711 Support for the Loongson Local I/O Interrupt Controller. 712 713config LOONGSON_EIOINTC 714 bool "Loongson Extend I/O Interrupt Controller" 715 depends on LOONGARCH 716 default MACH_LOONGSON64 717 select IRQ_DOMAIN_HIERARCHY 718 select GENERIC_IRQ_CHIP 719 help 720 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 721 722config LOONGSON_HTPIC 723 bool "Loongson3 HyperTransport PIC Controller" 724 depends on MACH_LOONGSON64 && MIPS 725 default y 726 select IRQ_DOMAIN 727 select GENERIC_IRQ_CHIP 728 help 729 Support for the Loongson-3 HyperTransport PIC Controller. 730 731config LOONGSON_HTVEC 732 bool "Loongson HyperTransport Interrupt Vector Controller" 733 depends on MACH_LOONGSON64 || LOONGARCH 734 default MACH_LOONGSON64 735 select IRQ_DOMAIN_HIERARCHY 736 help 737 Support for the Loongson HyperTransport Interrupt Vector Controller. 738 739config LOONGSON_PCH_PIC 740 bool "Loongson PCH PIC Controller" 741 depends on MACH_LOONGSON64 || LOONGARCH 742 default MACH_LOONGSON64 743 select IRQ_DOMAIN_HIERARCHY 744 select IRQ_FASTEOI_HIERARCHY_HANDLERS 745 help 746 Support for the Loongson PCH PIC Controller. 747 748config LOONGSON_PCH_MSI 749 bool "Loongson PCH MSI Controller" 750 depends on MACH_LOONGSON64 || LOONGARCH 751 depends on PCI 752 default MACH_LOONGSON64 753 select IRQ_DOMAIN_HIERARCHY 754 select IRQ_MSI_LIB 755 select PCI_MSI 756 help 757 Support for the Loongson PCH MSI Controller. 758 759config LOONGSON_PCH_LPC 760 bool "Loongson PCH LPC Controller" 761 depends on MACH_LOONGSON64 || LOONGARCH 762 default MACH_LOONGSON64 763 select IRQ_DOMAIN_HIERARCHY 764 help 765 Support for the Loongson PCH LPC Controller. 766 767config MST_IRQ 768 bool "MStar Interrupt Controller" 769 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 770 default ARCH_MEDIATEK 771 select IRQ_DOMAIN 772 select IRQ_DOMAIN_HIERARCHY 773 help 774 Support MStar Interrupt Controller. 775 776config WPCM450_AIC 777 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 778 depends on ARCH_WPCM450 779 help 780 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 781 782config IRQ_IDT3243X 783 bool 784 select GENERIC_IRQ_CHIP 785 select IRQ_DOMAIN 786 787config APPLE_AIC 788 bool "Apple Interrupt Controller (AIC)" 789 depends on ARM64 790 depends on ARCH_APPLE || COMPILE_TEST 791 select GENERIC_IRQ_IPI_MUX 792 help 793 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 794 such as the M1. 795 796config MCHP_EIC 797 bool "Microchip External Interrupt Controller" 798 depends on ARCH_AT91 || COMPILE_TEST 799 select IRQ_DOMAIN 800 select IRQ_DOMAIN_HIERARCHY 801 help 802 Support for Microchip External Interrupt Controller. 803 804config SOPHGO_SG2042_MSI 805 bool "Sophgo SG2042 MSI Controller" 806 depends on ARCH_SOPHGO || COMPILE_TEST 807 depends on PCI 808 select IRQ_DOMAIN_HIERARCHY 809 select IRQ_MSI_LIB 810 select PCI_MSI 811 help 812 Support for the Sophgo SG2042 MSI Controller. 813 This on-chip interrupt controller enables MSI sources to be 814 routed to the primary PLIC controller on SoC. 815 816config SUNPLUS_SP7021_INTC 817 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 818 default SOC_SP7021 819 help 820 Support for the Sunplus SP7021 Interrupt Controller IP core. 821 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 822 chained controller, routing all interrupt source in P-Chip to 823 the primary controller on C-Chip. 824 825endmenu 826