1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 41 select HAVE_ARM_SMCCC_DISCOVERY 42 select IRQ_MSI_IOMMU 43 44config ARM_GIC_V3_ITS 45 bool 46 select GENERIC_MSI_IRQ 47 select IRQ_MSI_LIB 48 default ARM_GIC_V3 49 select IRQ_MSI_IOMMU 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config IRQ_MSI_LIB 76 bool 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF 93 depends on HAS_IOMEM 94 select GENERIC_IRQ_CHIP 95 select IRQ_DOMAIN 96 help 97 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 98 99config ATMEL_AIC_IRQ 100 bool 101 select GENERIC_IRQ_CHIP 102 select IRQ_DOMAIN 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select SPARSE_IRQ 110 111config I8259 112 bool 113 select IRQ_DOMAIN 114 115config BCM6345_L1_IRQ 116 bool 117 select GENERIC_IRQ_CHIP 118 select IRQ_DOMAIN 119 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 120 121config BCM7038_L1_IRQ 122 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 123 depends on ARCH_BRCMSTB || BMIPS_GENERIC 124 default ARCH_BRCMSTB || BMIPS_GENERIC 125 select GENERIC_IRQ_CHIP 126 select IRQ_DOMAIN 127 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 128 129config BCM7120_L2_IRQ 130 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 131 depends on ARCH_BRCMSTB || BMIPS_GENERIC 132 default ARCH_BRCMSTB || BMIPS_GENERIC 133 select GENERIC_IRQ_CHIP 134 select IRQ_DOMAIN 135 136config BRCMSTB_L2_IRQ 137 tristate "Broadcom STB generic L2 interrupt controller driver" 138 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 139 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DAVINCI_CP_INTC 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN 147 148config DW_APB_ICTL 149 bool 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN_HIERARCHY 152 153config FARADAY_FTINTC010 154 bool 155 select IRQ_DOMAIN 156 select SPARSE_IRQ 157 158config HISILICON_IRQ_MBIGEN 159 bool 160 select ARM_GIC_V3 161 select ARM_GIC_V3_ITS 162 163config IMGPDC_IRQ 164 bool 165 select GENERIC_IRQ_CHIP 166 select IRQ_DOMAIN 167 168config IXP4XX_IRQ 169 bool 170 select IRQ_DOMAIN 171 select SPARSE_IRQ 172 173config LAN966X_OIC 174 tristate "Microchip LAN966x OIC Support" 175 depends on MCHP_LAN966X_PCI || COMPILE_TEST 176 select GENERIC_IRQ_CHIP 177 select IRQ_DOMAIN 178 help 179 Enable support for the LAN966x Outbound Interrupt Controller. 180 This controller is present on the Microchip LAN966x PCI device and 181 maps the internal interrupts sources to PCIe interrupt. 182 183 To compile this driver as a module, choose M here: the module 184 will be called irq-lan966x-oic. 185 186config MADERA_IRQ 187 tristate 188 189config IRQ_MIPS_CPU 190 bool 191 select GENERIC_IRQ_CHIP 192 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 193 select IRQ_DOMAIN 194 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 195 196config CLPS711X_IRQCHIP 197 bool 198 depends on ARCH_CLPS711X 199 select IRQ_DOMAIN 200 select SPARSE_IRQ 201 default y 202 203config OMPIC 204 bool 205 206config OR1K_PIC 207 bool 208 select IRQ_DOMAIN 209 210config OMAP_IRQCHIP 211 bool 212 select GENERIC_IRQ_CHIP 213 select IRQ_DOMAIN 214 215config ORION_IRQCHIP 216 bool 217 select IRQ_DOMAIN 218 219config PIC32_EVIC 220 bool 221 select GENERIC_IRQ_CHIP 222 select IRQ_DOMAIN 223 224config JCORE_AIC 225 bool "J-Core integrated AIC" if COMPILE_TEST 226 depends on OF 227 select IRQ_DOMAIN 228 help 229 Support for the J-Core integrated AIC. 230 231config RDA_INTC 232 bool 233 select IRQ_DOMAIN 234 235config RENESAS_INTC_IRQPIN 236 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 237 select IRQ_DOMAIN 238 help 239 Enable support for the Renesas Interrupt Controller for external 240 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 241 242config RENESAS_IRQC 243 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 244 select GENERIC_IRQ_CHIP 245 select IRQ_DOMAIN 246 help 247 Enable support for the Renesas Interrupt Controller for external 248 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 249 250config RENESAS_RZA1_IRQC 251 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 252 select IRQ_DOMAIN_HIERARCHY 253 help 254 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 255 to 8 external interrupts with configurable sense select. 256 257config RENESAS_RZG2L_IRQC 258 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 259 select GENERIC_IRQ_CHIP 260 select IRQ_DOMAIN_HIERARCHY 261 help 262 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 263 for external devices. 264 265config RENESAS_RZV2H_ICU 266 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 267 select GENERIC_IRQ_CHIP 268 select IRQ_DOMAIN_HIERARCHY 269 help 270 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 271 272config SL28CPLD_INTC 273 bool "Kontron sl28cpld IRQ controller" 274 depends on MFD_SL28CPLD=y || COMPILE_TEST 275 select REGMAP_IRQ 276 help 277 Interrupt controller driver for the board management controller 278 found on the Kontron sl28 CPLD. 279 280config ST_IRQCHIP 281 bool 282 select REGMAP 283 select MFD_SYSCON 284 help 285 Enables SysCfg Controlled IRQs on STi based platforms. 286 287config SUN4I_INTC 288 bool 289 290config SUN6I_R_INTC 291 bool 292 select IRQ_DOMAIN_HIERARCHY 293 select IRQ_FASTEOI_HIERARCHY_HANDLERS 294 295config SUNXI_NMI_INTC 296 bool 297 select GENERIC_IRQ_CHIP 298 299config TB10X_IRQC 300 bool 301 select IRQ_DOMAIN 302 select GENERIC_IRQ_CHIP 303 304config TS4800_IRQ 305 tristate "TS-4800 IRQ controller" 306 select IRQ_DOMAIN 307 depends on HAS_IOMEM 308 depends on SOC_IMX51 || COMPILE_TEST 309 help 310 Support for the TS-4800 FPGA IRQ controller 311 312config VERSATILE_FPGA_IRQ 313 bool 314 select IRQ_DOMAIN 315 316config VERSATILE_FPGA_IRQ_NR 317 int 318 default 4 319 depends on VERSATILE_FPGA_IRQ 320 321config XTENSA_MX 322 bool 323 select IRQ_DOMAIN 324 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 325 326config XILINX_INTC 327 bool "Xilinx Interrupt Controller IP" 328 depends on OF_ADDRESS 329 select IRQ_DOMAIN 330 help 331 Support for the Xilinx Interrupt Controller IP core. 332 This is used as a primary controller with MicroBlaze and can also 333 be used as a secondary chained controller on other platforms. 334 335config IRQ_CROSSBAR 336 bool 337 help 338 Support for a CROSSBAR ip that precedes the main interrupt controller. 339 The primary irqchip invokes the crossbar's callback which inturn allocates 340 a free irq and configures the IP. Thus the peripheral interrupts are 341 routed to one of the free irqchip interrupt lines. 342 343config KEYSTONE_IRQ 344 tristate "Keystone 2 IRQ controller IP" 345 depends on ARCH_KEYSTONE 346 help 347 Support for Texas Instruments Keystone 2 IRQ controller IP which 348 is part of the Keystone 2 IPC mechanism 349 350config MIPS_GIC 351 bool 352 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 353 select GENERIC_IRQ_IPI if SMP 354 select IRQ_DOMAIN_HIERARCHY 355 select MIPS_CM 356 357config INGENIC_IRQ 358 bool 359 depends on MACH_INGENIC 360 default y 361 362config INGENIC_TCU_IRQ 363 bool "Ingenic JZ47xx TCU interrupt controller" 364 default MACH_INGENIC 365 depends on MIPS || COMPILE_TEST 366 select MFD_SYSCON 367 select GENERIC_IRQ_CHIP 368 help 369 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 370 JZ47xx SoCs. 371 372 If unsure, say N. 373 374config IMX_GPCV2 375 bool 376 select IRQ_DOMAIN 377 help 378 Enables the wakeup IRQs for IMX platforms with GPCv2 block 379 380config IRQ_MXS 381 def_bool y if MACH_ASM9260 || ARCH_MXS 382 select IRQ_DOMAIN 383 select STMP_DEVICE 384 385config MSCC_OCELOT_IRQ 386 bool 387 select IRQ_DOMAIN 388 select GENERIC_IRQ_CHIP 389 390config MVEBU_GICP 391 select IRQ_MSI_LIB 392 bool 393 394config MVEBU_ICU 395 bool 396 397config MVEBU_ODMI 398 bool 399 select IRQ_MSI_LIB 400 select GENERIC_MSI_IRQ 401 402config MVEBU_PIC 403 bool 404 405config MVEBU_SEI 406 bool 407 408config LS_EXTIRQ 409 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 410 select MFD_SYSCON 411 412config LS_SCFG_MSI 413 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 414 select IRQ_MSI_IOMMU 415 depends on PCI_MSI 416 417config PARTITION_PERCPU 418 bool 419 420config STM32MP_EXTI 421 tristate "STM32MP extended interrupts and event controller" 422 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 423 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 424 select IRQ_DOMAIN_HIERARCHY 425 select GENERIC_IRQ_CHIP 426 help 427 Support STM32MP EXTI (extended interrupts and event) controller. 428 429config STM32_EXTI 430 bool 431 select IRQ_DOMAIN 432 select GENERIC_IRQ_CHIP 433 434config QCOM_IRQ_COMBINER 435 bool "QCOM IRQ combiner support" 436 depends on ARCH_QCOM && ACPI 437 select IRQ_DOMAIN_HIERARCHY 438 help 439 Say yes here to add support for the IRQ combiner devices embedded 440 in Qualcomm Technologies chips. 441 442config IRQ_UNIPHIER_AIDET 443 bool "UniPhier AIDET support" if COMPILE_TEST 444 depends on ARCH_UNIPHIER || COMPILE_TEST 445 default ARCH_UNIPHIER 446 select IRQ_DOMAIN_HIERARCHY 447 help 448 Support for the UniPhier AIDET (ARM Interrupt Detector). 449 450config MESON_IRQ_GPIO 451 tristate "Meson GPIO Interrupt Multiplexer" 452 depends on ARCH_MESON || COMPILE_TEST 453 default ARCH_MESON 454 select IRQ_DOMAIN_HIERARCHY 455 help 456 Support Meson SoC Family GPIO Interrupt Multiplexer 457 458config GOLDFISH_PIC 459 bool "Goldfish programmable interrupt controller" 460 depends on MIPS && (GOLDFISH || COMPILE_TEST) 461 select GENERIC_IRQ_CHIP 462 select IRQ_DOMAIN 463 help 464 Say yes here to enable Goldfish interrupt controller driver used 465 for Goldfish based virtual platforms. 466 467config QCOM_PDC 468 tristate "QCOM PDC" 469 depends on ARCH_QCOM 470 select IRQ_DOMAIN_HIERARCHY 471 help 472 Power Domain Controller driver to manage and configure wakeup 473 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 474 475config QCOM_MPM 476 tristate "QCOM MPM" 477 depends on ARCH_QCOM 478 depends on MAILBOX 479 select IRQ_DOMAIN_HIERARCHY 480 help 481 MSM Power Manager driver to manage and configure wakeup 482 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 483 484config CSKY_MPINTC 485 bool 486 depends on CSKY 487 help 488 Say yes here to enable C-SKY SMP interrupt controller driver used 489 for C-SKY SMP system. 490 In fact it's not mmio map in hardware and it uses ld/st to visit the 491 controller's register inside CPU. 492 493config CSKY_APB_INTC 494 bool "C-SKY APB Interrupt Controller" 495 depends on CSKY 496 help 497 Say yes here to enable C-SKY APB interrupt controller driver used 498 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 499 the controller's register. 500 501config IMX_IRQSTEER 502 bool "i.MX IRQSTEER support" 503 depends on ARCH_MXC || COMPILE_TEST 504 default ARCH_MXC 505 select IRQ_DOMAIN 506 help 507 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 508 509config IMX_INTMUX 510 bool "i.MX INTMUX support" if COMPILE_TEST 511 default y if ARCH_MXC 512 select IRQ_DOMAIN 513 help 514 Support for the i.MX INTMUX interrupt multiplexer. 515 516config IMX_MU_MSI 517 tristate "i.MX MU used as MSI controller" 518 depends on OF && HAS_IOMEM 519 depends on ARCH_MXC || COMPILE_TEST 520 default m if ARCH_MXC 521 select IRQ_DOMAIN 522 select IRQ_DOMAIN_HIERARCHY 523 select GENERIC_MSI_IRQ 524 select IRQ_MSI_LIB 525 help 526 Provide a driver for the i.MX Messaging Unit block used as a 527 CPU-to-CPU MSI controller. This requires a specially crafted DT 528 to make use of this driver. 529 530 If unsure, say N 531 532config LS1X_IRQ 533 bool "Loongson-1 Interrupt Controller" 534 depends on MACH_LOONGSON32 535 default y 536 select IRQ_DOMAIN 537 select GENERIC_IRQ_CHIP 538 help 539 Support for the Loongson-1 platform Interrupt Controller. 540 541config TI_SCI_INTR_IRQCHIP 542 tristate "TI SCI INTR Interrupt Controller" 543 depends on TI_SCI_PROTOCOL 544 depends on ARCH_K3 || COMPILE_TEST 545 select IRQ_DOMAIN_HIERARCHY 546 help 547 This enables the irqchip driver support for K3 Interrupt router 548 over TI System Control Interface available on some new TI's SoCs. 549 If you wish to use interrupt router irq resources managed by the 550 TI System Controller, say Y here. Otherwise, say N. 551 552config TI_SCI_INTA_IRQCHIP 553 tristate "TI SCI INTA Interrupt Controller" 554 depends on TI_SCI_PROTOCOL 555 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 556 select IRQ_DOMAIN_HIERARCHY 557 select TI_SCI_INTA_MSI_DOMAIN 558 help 559 This enables the irqchip driver support for K3 Interrupt aggregator 560 over TI System Control Interface available on some new TI's SoCs. 561 If you wish to use interrupt aggregator irq resources managed by the 562 TI System Controller, say Y here. Otherwise, say N. 563 564config TI_PRUSS_INTC 565 tristate 566 depends on TI_PRUSS 567 default TI_PRUSS 568 select IRQ_DOMAIN 569 help 570 This enables support for the PRU-ICSS Local Interrupt Controller 571 present within a PRU-ICSS subsystem present on various TI SoCs. 572 The PRUSS INTC enables various interrupts to be routed to multiple 573 different processors within the SoC. 574 575config RISCV_INTC 576 bool 577 depends on RISCV 578 select IRQ_DOMAIN_HIERARCHY 579 580config RISCV_APLIC 581 bool 582 depends on RISCV 583 select IRQ_DOMAIN_HIERARCHY 584 585config RISCV_APLIC_MSI 586 bool 587 depends on RISCV_APLIC 588 select GENERIC_MSI_IRQ 589 default RISCV_APLIC 590 591config RISCV_IMSIC 592 bool 593 depends on RISCV 594 select IRQ_DOMAIN_HIERARCHY 595 select GENERIC_IRQ_MATRIX_ALLOCATOR 596 select GENERIC_MSI_IRQ 597 598config RISCV_IMSIC_PCI 599 bool 600 depends on RISCV_IMSIC 601 depends on PCI 602 depends on PCI_MSI 603 default RISCV_IMSIC 604 605config SIFIVE_PLIC 606 bool 607 depends on RISCV 608 select IRQ_DOMAIN_HIERARCHY 609 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 610 611config STARFIVE_JH8100_INTC 612 bool "StarFive JH8100 External Interrupt Controller" 613 depends on ARCH_STARFIVE || COMPILE_TEST 614 default ARCH_STARFIVE 615 select IRQ_DOMAIN_HIERARCHY 616 help 617 This enables support for the INTC chip found in StarFive JH8100 618 SoC. 619 620 If you don't know what to do here, say Y. 621 622config THEAD_C900_ACLINT_SSWI 623 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 624 depends on RISCV 625 depends on SMP 626 select IRQ_DOMAIN_HIERARCHY 627 select GENERIC_IRQ_IPI_MUX 628 help 629 This enables support for T-HEAD specific ACLINT SSWI device 630 support. 631 632 If you don't know what to do here, say Y. 633 634config EXYNOS_IRQ_COMBINER 635 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 636 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 637 help 638 Say yes here to add support for the IRQ combiner devices embedded 639 in Samsung Exynos chips. 640 641config IRQ_LOONGARCH_CPU 642 bool 643 select GENERIC_IRQ_CHIP 644 select IRQ_DOMAIN 645 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 646 select LOONGSON_HTVEC 647 select LOONGSON_LIOINTC 648 select LOONGSON_EIOINTC 649 select LOONGSON_PCH_PIC 650 select LOONGSON_PCH_MSI 651 select LOONGSON_PCH_LPC 652 help 653 Support for the LoongArch CPU Interrupt Controller. For details of 654 irq chip hierarchy on LoongArch platforms please read the document 655 Documentation/arch/loongarch/irq-chip-model.rst. 656 657config LOONGSON_LIOINTC 658 bool "Loongson Local I/O Interrupt Controller" 659 depends on MACH_LOONGSON64 660 default y 661 select IRQ_DOMAIN 662 select GENERIC_IRQ_CHIP 663 help 664 Support for the Loongson Local I/O Interrupt Controller. 665 666config LOONGSON_EIOINTC 667 bool "Loongson Extend I/O Interrupt Controller" 668 depends on LOONGARCH 669 depends on MACH_LOONGSON64 670 default MACH_LOONGSON64 671 select IRQ_DOMAIN_HIERARCHY 672 select GENERIC_IRQ_CHIP 673 help 674 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 675 676config LOONGSON_HTPIC 677 bool "Loongson3 HyperTransport PIC Controller" 678 depends on MACH_LOONGSON64 && MIPS 679 default y 680 select IRQ_DOMAIN 681 select GENERIC_IRQ_CHIP 682 help 683 Support for the Loongson-3 HyperTransport PIC Controller. 684 685config LOONGSON_HTVEC 686 bool "Loongson HyperTransport Interrupt Vector Controller" 687 depends on MACH_LOONGSON64 688 default MACH_LOONGSON64 689 select IRQ_DOMAIN_HIERARCHY 690 help 691 Support for the Loongson HyperTransport Interrupt Vector Controller. 692 693config LOONGSON_PCH_PIC 694 bool "Loongson PCH PIC Controller" 695 depends on MACH_LOONGSON64 696 default MACH_LOONGSON64 697 select IRQ_DOMAIN_HIERARCHY 698 select IRQ_FASTEOI_HIERARCHY_HANDLERS 699 help 700 Support for the Loongson PCH PIC Controller. 701 702config LOONGSON_PCH_MSI 703 bool "Loongson PCH MSI Controller" 704 depends on MACH_LOONGSON64 705 depends on PCI 706 default MACH_LOONGSON64 707 select IRQ_DOMAIN_HIERARCHY 708 select IRQ_MSI_LIB 709 select PCI_MSI 710 help 711 Support for the Loongson PCH MSI Controller. 712 713config LOONGSON_PCH_LPC 714 bool "Loongson PCH LPC Controller" 715 depends on LOONGARCH 716 depends on MACH_LOONGSON64 717 default MACH_LOONGSON64 718 select IRQ_DOMAIN_HIERARCHY 719 help 720 Support for the Loongson PCH LPC Controller. 721 722config MST_IRQ 723 bool "MStar Interrupt Controller" 724 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 725 default ARCH_MEDIATEK 726 select IRQ_DOMAIN 727 select IRQ_DOMAIN_HIERARCHY 728 help 729 Support MStar Interrupt Controller. 730 731config WPCM450_AIC 732 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 733 depends on ARCH_WPCM450 734 help 735 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 736 737config IRQ_IDT3243X 738 bool 739 select GENERIC_IRQ_CHIP 740 select IRQ_DOMAIN 741 742config APPLE_AIC 743 bool "Apple Interrupt Controller (AIC)" 744 depends on ARM64 745 depends on ARCH_APPLE || COMPILE_TEST 746 select GENERIC_IRQ_IPI_MUX 747 help 748 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 749 such as the M1. 750 751config MCHP_EIC 752 bool "Microchip External Interrupt Controller" 753 depends on ARCH_AT91 || COMPILE_TEST 754 select IRQ_DOMAIN 755 select IRQ_DOMAIN_HIERARCHY 756 help 757 Support for Microchip External Interrupt Controller. 758 759config SUNPLUS_SP7021_INTC 760 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 761 default SOC_SP7021 762 help 763 Support for the Sunplus SP7021 Interrupt Controller IP core. 764 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 765 chained controller, routing all interrupt source in P-Chip to 766 the primary controller on C-Chip. 767 768endmenu 769