1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 41 select HAVE_ARM_SMCCC_DISCOVERY 42 select IRQ_MSI_IOMMU 43 44config ARM_GIC_V3_ITS 45 bool 46 select GENERIC_MSI_IRQ 47 select IRQ_MSI_LIB 48 default ARM_GIC_V3 49 select IRQ_MSI_IOMMU 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config IRQ_MSI_LIB 76 bool 77 select GENERIC_MSI_IRQ 78 79config ARMADA_370_XP_IRQ 80 bool 81 select GENERIC_IRQ_CHIP 82 select PCI_MSI if PCI 83 select IRQ_MSI_LIB if PCI 84 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 85 86config ALPINE_MSI 87 bool 88 depends on PCI 89 select PCI_MSI 90 select IRQ_MSI_LIB 91 select GENERIC_IRQ_CHIP 92 93config AL_FIC 94 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 95 depends on OF 96 depends on HAS_IOMEM 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 help 100 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 101 102config ATMEL_AIC_IRQ 103 bool 104 select GENERIC_IRQ_CHIP 105 select IRQ_DOMAIN 106 select SPARSE_IRQ 107 108config ATMEL_AIC5_IRQ 109 bool 110 select GENERIC_IRQ_CHIP 111 select IRQ_DOMAIN 112 select SPARSE_IRQ 113 114config I8259 115 bool 116 select IRQ_DOMAIN 117 118config BCM2712_MIP 119 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 120 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 121 default m if ARCH_BRCMSTB || ARCH_BCM2835 122 depends on ARM_GIC 123 select GENERIC_IRQ_CHIP 124 select IRQ_DOMAIN_HIERARCHY 125 select GENERIC_MSI_IRQ 126 select IRQ_MSI_LIB 127 help 128 Enable support for the Broadcom BCM2712 MSI-X target peripheral 129 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 130 Raspberry Pi 5. 131 132 If unsure say n. 133 134config BCM6345_L1_IRQ 135 bool 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 139 140config BCM7038_L1_IRQ 141 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 142 depends on ARCH_BRCMSTB || BMIPS_GENERIC 143 default ARCH_BRCMSTB || BMIPS_GENERIC 144 select GENERIC_IRQ_CHIP 145 select IRQ_DOMAIN 146 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 147 148config BCM7120_L2_IRQ 149 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 150 depends on ARCH_BRCMSTB || BMIPS_GENERIC 151 default ARCH_BRCMSTB || BMIPS_GENERIC 152 select GENERIC_IRQ_CHIP 153 select IRQ_DOMAIN 154 155config BRCMSTB_L2_IRQ 156 tristate "Broadcom STB generic L2 interrupt controller driver" 157 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 158 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 159 select GENERIC_IRQ_CHIP 160 select IRQ_DOMAIN 161 162config DAVINCI_CP_INTC 163 bool 164 select GENERIC_IRQ_CHIP 165 select IRQ_DOMAIN 166 167config DW_APB_ICTL 168 bool 169 select GENERIC_IRQ_CHIP 170 select IRQ_DOMAIN_HIERARCHY 171 172config ECONET_EN751221_INTC 173 bool 174 select GENERIC_IRQ_CHIP 175 select IRQ_DOMAIN 176 177config FARADAY_FTINTC010 178 bool 179 select IRQ_DOMAIN 180 select SPARSE_IRQ 181 182config HISILICON_IRQ_MBIGEN 183 bool 184 select ARM_GIC_V3 185 select ARM_GIC_V3_ITS 186 187config IMGPDC_IRQ 188 bool 189 select GENERIC_IRQ_CHIP 190 select IRQ_DOMAIN 191 192config IXP4XX_IRQ 193 bool 194 select IRQ_DOMAIN 195 select SPARSE_IRQ 196 197config LAN966X_OIC 198 tristate "Microchip LAN966x OIC Support" 199 depends on MCHP_LAN966X_PCI || COMPILE_TEST 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 help 203 Enable support for the LAN966x Outbound Interrupt Controller. 204 This controller is present on the Microchip LAN966x PCI device and 205 maps the internal interrupts sources to PCIe interrupt. 206 207 To compile this driver as a module, choose M here: the module 208 will be called irq-lan966x-oic. 209 210config MADERA_IRQ 211 tristate 212 213config IRQ_MIPS_CPU 214 bool 215 select GENERIC_IRQ_CHIP 216 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 217 select IRQ_DOMAIN 218 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 219 220config CLPS711X_IRQCHIP 221 bool 222 depends on ARCH_CLPS711X 223 select IRQ_DOMAIN 224 select SPARSE_IRQ 225 default y 226 227config OMPIC 228 bool 229 230config OR1K_PIC 231 bool 232 select IRQ_DOMAIN 233 234config OMAP_IRQCHIP 235 bool 236 select GENERIC_IRQ_CHIP 237 select IRQ_DOMAIN 238 239config ORION_IRQCHIP 240 bool 241 select IRQ_DOMAIN 242 243config PIC32_EVIC 244 bool 245 select GENERIC_IRQ_CHIP 246 select IRQ_DOMAIN 247 248config JCORE_AIC 249 bool "J-Core integrated AIC" if COMPILE_TEST 250 depends on OF 251 select IRQ_DOMAIN 252 help 253 Support for the J-Core integrated AIC. 254 255config RDA_INTC 256 bool 257 select IRQ_DOMAIN 258 259config RENESAS_INTC_IRQPIN 260 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 261 select IRQ_DOMAIN 262 help 263 Enable support for the Renesas Interrupt Controller for external 264 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 265 266config RENESAS_IRQC 267 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 268 select GENERIC_IRQ_CHIP 269 select IRQ_DOMAIN 270 help 271 Enable support for the Renesas Interrupt Controller for external 272 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 273 274config RENESAS_RZA1_IRQC 275 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 276 select IRQ_DOMAIN_HIERARCHY 277 help 278 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 279 to 8 external interrupts with configurable sense select. 280 281config RENESAS_RZG2L_IRQC 282 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 283 select GENERIC_IRQ_CHIP 284 select IRQ_DOMAIN_HIERARCHY 285 help 286 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 287 for external devices. 288 289config RENESAS_RZV2H_ICU 290 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 291 select GENERIC_IRQ_CHIP 292 select IRQ_DOMAIN_HIERARCHY 293 help 294 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 295 296config SL28CPLD_INTC 297 bool "Kontron sl28cpld IRQ controller" 298 depends on MFD_SL28CPLD=y || COMPILE_TEST 299 select REGMAP_IRQ 300 help 301 Interrupt controller driver for the board management controller 302 found on the Kontron sl28 CPLD. 303 304config ST_IRQCHIP 305 bool 306 select REGMAP 307 select MFD_SYSCON 308 help 309 Enables SysCfg Controlled IRQs on STi based platforms. 310 311config SUN4I_INTC 312 bool 313 314config SUN6I_R_INTC 315 bool 316 select IRQ_DOMAIN_HIERARCHY 317 select IRQ_FASTEOI_HIERARCHY_HANDLERS 318 319config SUNXI_NMI_INTC 320 bool 321 select GENERIC_IRQ_CHIP 322 323config TB10X_IRQC 324 bool 325 select IRQ_DOMAIN 326 select GENERIC_IRQ_CHIP 327 328config TS4800_IRQ 329 tristate "TS-4800 IRQ controller" 330 select IRQ_DOMAIN 331 depends on HAS_IOMEM 332 depends on SOC_IMX51 || COMPILE_TEST 333 help 334 Support for the TS-4800 FPGA IRQ controller 335 336config VERSATILE_FPGA_IRQ 337 bool 338 select IRQ_DOMAIN 339 340config VERSATILE_FPGA_IRQ_NR 341 int 342 default 4 343 depends on VERSATILE_FPGA_IRQ 344 345config XTENSA_MX 346 bool 347 select IRQ_DOMAIN 348 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 349 350config XILINX_INTC 351 bool "Xilinx Interrupt Controller IP" 352 depends on OF_ADDRESS 353 select IRQ_DOMAIN 354 help 355 Support for the Xilinx Interrupt Controller IP core. 356 This is used as a primary controller with MicroBlaze and can also 357 be used as a secondary chained controller on other platforms. 358 359config IRQ_CROSSBAR 360 bool 361 help 362 Support for a CROSSBAR ip that precedes the main interrupt controller. 363 The primary irqchip invokes the crossbar's callback which inturn allocates 364 a free irq and configures the IP. Thus the peripheral interrupts are 365 routed to one of the free irqchip interrupt lines. 366 367config KEYSTONE_IRQ 368 tristate "Keystone 2 IRQ controller IP" 369 depends on ARCH_KEYSTONE 370 help 371 Support for Texas Instruments Keystone 2 IRQ controller IP which 372 is part of the Keystone 2 IPC mechanism 373 374config MIPS_GIC 375 bool 376 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 377 select GENERIC_IRQ_IPI if SMP 378 select IRQ_DOMAIN_HIERARCHY 379 select MIPS_CM 380 381config INGENIC_IRQ 382 bool 383 depends on MACH_INGENIC 384 default y 385 386config INGENIC_TCU_IRQ 387 bool "Ingenic JZ47xx TCU interrupt controller" 388 default MACH_INGENIC 389 depends on MIPS || COMPILE_TEST 390 select MFD_SYSCON 391 select GENERIC_IRQ_CHIP 392 help 393 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 394 JZ47xx SoCs. 395 396 If unsure, say N. 397 398config IMX_GPCV2 399 bool 400 select IRQ_DOMAIN 401 help 402 Enables the wakeup IRQs for IMX platforms with GPCv2 block 403 404config IRQ_MXS 405 def_bool y if MACH_ASM9260 || ARCH_MXS 406 select IRQ_DOMAIN 407 select STMP_DEVICE 408 409config MSCC_OCELOT_IRQ 410 bool 411 select IRQ_DOMAIN 412 select GENERIC_IRQ_CHIP 413 414config MVEBU_GICP 415 select IRQ_MSI_LIB 416 bool 417 418config MVEBU_ICU 419 bool 420 421config MVEBU_ODMI 422 bool 423 select IRQ_MSI_LIB 424 select GENERIC_MSI_IRQ 425 426config MVEBU_PIC 427 bool 428 429config MVEBU_SEI 430 bool 431 432config LS_EXTIRQ 433 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 434 select MFD_SYSCON 435 436config LS_SCFG_MSI 437 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 438 select IRQ_MSI_IOMMU 439 depends on PCI_MSI 440 select IRQ_MSI_LIB 441 442config PARTITION_PERCPU 443 bool 444 445config STM32MP_EXTI 446 tristate "STM32MP extended interrupts and event controller" 447 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 448 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 449 select IRQ_DOMAIN_HIERARCHY 450 select GENERIC_IRQ_CHIP 451 help 452 Support STM32MP EXTI (extended interrupts and event) controller. 453 454config STM32_EXTI 455 bool 456 select IRQ_DOMAIN 457 select GENERIC_IRQ_CHIP 458 459config QCOM_IRQ_COMBINER 460 bool "QCOM IRQ combiner support" 461 depends on ARCH_QCOM && ACPI 462 select IRQ_DOMAIN_HIERARCHY 463 help 464 Say yes here to add support for the IRQ combiner devices embedded 465 in Qualcomm Technologies chips. 466 467config IRQ_UNIPHIER_AIDET 468 bool "UniPhier AIDET support" if COMPILE_TEST 469 depends on ARCH_UNIPHIER || COMPILE_TEST 470 default ARCH_UNIPHIER 471 select IRQ_DOMAIN_HIERARCHY 472 help 473 Support for the UniPhier AIDET (ARM Interrupt Detector). 474 475config MESON_IRQ_GPIO 476 tristate "Meson GPIO Interrupt Multiplexer" 477 depends on ARCH_MESON || COMPILE_TEST 478 default ARCH_MESON 479 select IRQ_DOMAIN_HIERARCHY 480 help 481 Support Meson SoC Family GPIO Interrupt Multiplexer 482 483config GOLDFISH_PIC 484 bool "Goldfish programmable interrupt controller" 485 depends on MIPS && (GOLDFISH || COMPILE_TEST) 486 select GENERIC_IRQ_CHIP 487 select IRQ_DOMAIN 488 help 489 Say yes here to enable Goldfish interrupt controller driver used 490 for Goldfish based virtual platforms. 491 492config QCOM_PDC 493 tristate "QCOM PDC" 494 depends on ARCH_QCOM 495 select IRQ_DOMAIN_HIERARCHY 496 help 497 Power Domain Controller driver to manage and configure wakeup 498 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 499 500config QCOM_MPM 501 tristate "QCOM MPM" 502 depends on ARCH_QCOM 503 depends on MAILBOX 504 select IRQ_DOMAIN_HIERARCHY 505 help 506 MSM Power Manager driver to manage and configure wakeup 507 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 508 509config CSKY_MPINTC 510 bool 511 depends on CSKY 512 help 513 Say yes here to enable C-SKY SMP interrupt controller driver used 514 for C-SKY SMP system. 515 In fact it's not mmio map in hardware and it uses ld/st to visit the 516 controller's register inside CPU. 517 518config CSKY_APB_INTC 519 bool "C-SKY APB Interrupt Controller" 520 depends on CSKY 521 help 522 Say yes here to enable C-SKY APB interrupt controller driver used 523 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 524 the controller's register. 525 526config IMX_IRQSTEER 527 bool "i.MX IRQSTEER support" 528 depends on ARCH_MXC || COMPILE_TEST 529 default ARCH_MXC 530 select IRQ_DOMAIN 531 help 532 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 533 534config IMX_INTMUX 535 bool "i.MX INTMUX support" if COMPILE_TEST 536 default y if ARCH_MXC 537 select IRQ_DOMAIN 538 help 539 Support for the i.MX INTMUX interrupt multiplexer. 540 541config IMX_MU_MSI 542 tristate "i.MX MU used as MSI controller" 543 depends on OF && HAS_IOMEM 544 depends on ARCH_MXC || COMPILE_TEST 545 default m if ARCH_MXC 546 select IRQ_DOMAIN 547 select IRQ_DOMAIN_HIERARCHY 548 select GENERIC_MSI_IRQ 549 select IRQ_MSI_LIB 550 help 551 Provide a driver for the i.MX Messaging Unit block used as a 552 CPU-to-CPU MSI controller. This requires a specially crafted DT 553 to make use of this driver. 554 555 If unsure, say N 556 557config LS1X_IRQ 558 bool "Loongson-1 Interrupt Controller" 559 depends on MACH_LOONGSON32 560 default y 561 select IRQ_DOMAIN 562 select GENERIC_IRQ_CHIP 563 help 564 Support for the Loongson-1 platform Interrupt Controller. 565 566config TI_SCI_INTR_IRQCHIP 567 tristate "TI SCI INTR Interrupt Controller" 568 depends on TI_SCI_PROTOCOL 569 depends on ARCH_K3 || COMPILE_TEST 570 select IRQ_DOMAIN_HIERARCHY 571 help 572 This enables the irqchip driver support for K3 Interrupt router 573 over TI System Control Interface available on some new TI's SoCs. 574 If you wish to use interrupt router irq resources managed by the 575 TI System Controller, say Y here. Otherwise, say N. 576 577config TI_SCI_INTA_IRQCHIP 578 tristate "TI SCI INTA Interrupt Controller" 579 depends on TI_SCI_PROTOCOL 580 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 581 select IRQ_DOMAIN_HIERARCHY 582 select TI_SCI_INTA_MSI_DOMAIN 583 help 584 This enables the irqchip driver support for K3 Interrupt aggregator 585 over TI System Control Interface available on some new TI's SoCs. 586 If you wish to use interrupt aggregator irq resources managed by the 587 TI System Controller, say Y here. Otherwise, say N. 588 589config TI_PRUSS_INTC 590 tristate 591 depends on TI_PRUSS 592 default TI_PRUSS 593 select IRQ_DOMAIN 594 help 595 This enables support for the PRU-ICSS Local Interrupt Controller 596 present within a PRU-ICSS subsystem present on various TI SoCs. 597 The PRUSS INTC enables various interrupts to be routed to multiple 598 different processors within the SoC. 599 600config RISCV_INTC 601 bool 602 depends on RISCV 603 select IRQ_DOMAIN_HIERARCHY 604 605config RISCV_APLIC 606 bool 607 depends on RISCV 608 select IRQ_DOMAIN_HIERARCHY 609 610config RISCV_APLIC_MSI 611 bool 612 depends on RISCV_APLIC 613 select GENERIC_MSI_IRQ 614 default RISCV_APLIC 615 616config RISCV_IMSIC 617 bool 618 depends on RISCV 619 select IRQ_DOMAIN_HIERARCHY 620 select GENERIC_IRQ_MATRIX_ALLOCATOR 621 select GENERIC_MSI_IRQ 622 select IRQ_MSI_LIB 623 624config SIFIVE_PLIC 625 bool 626 depends on RISCV 627 select IRQ_DOMAIN_HIERARCHY 628 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 629 630config STARFIVE_JH8100_INTC 631 bool "StarFive JH8100 External Interrupt Controller" 632 depends on ARCH_STARFIVE || COMPILE_TEST 633 default ARCH_STARFIVE 634 select IRQ_DOMAIN_HIERARCHY 635 help 636 This enables support for the INTC chip found in StarFive JH8100 637 SoC. 638 639 If you don't know what to do here, say Y. 640 641config ACLINT_SSWI 642 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 643 depends on RISCV 644 depends on SMP 645 select IRQ_DOMAIN_HIERARCHY 646 select GENERIC_IRQ_IPI_MUX 647 help 648 This enables support for variants of the RISC-V ACLINT-SSWI device. 649 Supported variants are: 650 - T-HEAD, with compatible "thead,c900-aclint-sswi" 651 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 652 653 If you don't know what to do here, say Y. 654 655# Backwards compatibility so oldconfig does not drop it. 656config THEAD_C900_ACLINT_SSWI 657 bool 658 select ACLINT_SSWI 659 660config EXYNOS_IRQ_COMBINER 661 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 662 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 663 help 664 Say yes here to add support for the IRQ combiner devices embedded 665 in Samsung Exynos chips. 666 667config IRQ_LOONGARCH_CPU 668 bool 669 select GENERIC_IRQ_CHIP 670 select IRQ_DOMAIN 671 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 672 select LOONGSON_HTVEC 673 select LOONGSON_LIOINTC 674 select LOONGSON_EIOINTC 675 select LOONGSON_PCH_PIC 676 select LOONGSON_PCH_MSI 677 select LOONGSON_PCH_LPC 678 help 679 Support for the LoongArch CPU Interrupt Controller. For details of 680 irq chip hierarchy on LoongArch platforms please read the document 681 Documentation/arch/loongarch/irq-chip-model.rst. 682 683config LOONGSON_LIOINTC 684 bool "Loongson Local I/O Interrupt Controller" 685 depends on MACH_LOONGSON64 686 default y 687 select IRQ_DOMAIN 688 select GENERIC_IRQ_CHIP 689 help 690 Support for the Loongson Local I/O Interrupt Controller. 691 692config LOONGSON_EIOINTC 693 bool "Loongson Extend I/O Interrupt Controller" 694 depends on LOONGARCH 695 depends on MACH_LOONGSON64 696 default MACH_LOONGSON64 697 select IRQ_DOMAIN_HIERARCHY 698 select GENERIC_IRQ_CHIP 699 help 700 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 701 702config LOONGSON_HTPIC 703 bool "Loongson3 HyperTransport PIC Controller" 704 depends on MACH_LOONGSON64 && MIPS 705 default y 706 select IRQ_DOMAIN 707 select GENERIC_IRQ_CHIP 708 help 709 Support for the Loongson-3 HyperTransport PIC Controller. 710 711config LOONGSON_HTVEC 712 bool "Loongson HyperTransport Interrupt Vector Controller" 713 depends on MACH_LOONGSON64 714 default MACH_LOONGSON64 715 select IRQ_DOMAIN_HIERARCHY 716 help 717 Support for the Loongson HyperTransport Interrupt Vector Controller. 718 719config LOONGSON_PCH_PIC 720 bool "Loongson PCH PIC Controller" 721 depends on MACH_LOONGSON64 722 default MACH_LOONGSON64 723 select IRQ_DOMAIN_HIERARCHY 724 select IRQ_FASTEOI_HIERARCHY_HANDLERS 725 help 726 Support for the Loongson PCH PIC Controller. 727 728config LOONGSON_PCH_MSI 729 bool "Loongson PCH MSI Controller" 730 depends on MACH_LOONGSON64 731 depends on PCI 732 default MACH_LOONGSON64 733 select IRQ_DOMAIN_HIERARCHY 734 select IRQ_MSI_LIB 735 select PCI_MSI 736 help 737 Support for the Loongson PCH MSI Controller. 738 739config LOONGSON_PCH_LPC 740 bool "Loongson PCH LPC Controller" 741 depends on LOONGARCH 742 depends on MACH_LOONGSON64 743 default MACH_LOONGSON64 744 select IRQ_DOMAIN_HIERARCHY 745 help 746 Support for the Loongson PCH LPC Controller. 747 748config MST_IRQ 749 bool "MStar Interrupt Controller" 750 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 751 default ARCH_MEDIATEK 752 select IRQ_DOMAIN 753 select IRQ_DOMAIN_HIERARCHY 754 help 755 Support MStar Interrupt Controller. 756 757config WPCM450_AIC 758 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 759 depends on ARCH_WPCM450 760 help 761 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 762 763config IRQ_IDT3243X 764 bool 765 select GENERIC_IRQ_CHIP 766 select IRQ_DOMAIN 767 768config APPLE_AIC 769 bool "Apple Interrupt Controller (AIC)" 770 depends on ARM64 771 depends on ARCH_APPLE || COMPILE_TEST 772 select GENERIC_IRQ_IPI_MUX 773 help 774 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 775 such as the M1. 776 777config MCHP_EIC 778 bool "Microchip External Interrupt Controller" 779 depends on ARCH_AT91 || COMPILE_TEST 780 select IRQ_DOMAIN 781 select IRQ_DOMAIN_HIERARCHY 782 help 783 Support for Microchip External Interrupt Controller. 784 785config SOPHGO_SG2042_MSI 786 bool "Sophgo SG2042 MSI Controller" 787 depends on ARCH_SOPHGO || COMPILE_TEST 788 depends on PCI 789 select IRQ_DOMAIN_HIERARCHY 790 select IRQ_MSI_LIB 791 select PCI_MSI 792 help 793 Support for the Sophgo SG2042 MSI Controller. 794 This on-chip interrupt controller enables MSI sources to be 795 routed to the primary PLIC controller on SoC. 796 797config SUNPLUS_SP7021_INTC 798 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 799 default SOC_SP7021 800 help 801 Support for the Sunplus SP7021 Interrupt Controller IP core. 802 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 803 chained controller, routing all interrupt source in P-Chip to 804 the primary controller on C-Chip. 805 806endmenu 807