1menu "IRQ chip support" 2 3config IRQCHIP 4 def_bool y 5 depends on OF_IRQ 6 7config ARM_GIC 8 bool 9 select IRQ_DOMAIN 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 select PM_CLK 19 20config ARM_GIC_MAX_NR 21 int 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select IRQ_DOMAIN 37 select GENERIC_IRQ_MULTI_HANDLER 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ_DOMAIN 45 default ARM_GIC_V3 46 47config ARM_GIC_V3_ITS_PCI 48 bool 49 depends on ARM_GIC_V3_ITS 50 depends on PCI 51 depends on PCI_MSI 52 default ARM_GIC_V3_ITS 53 54config ARM_GIC_V3_ITS_FSL_MC 55 bool 56 depends on ARM_GIC_V3_ITS 57 depends on FSL_MC_BUS 58 default ARM_GIC_V3_ITS 59 60config ARM_NVIC 61 bool 62 select IRQ_DOMAIN 63 select IRQ_DOMAIN_HIERARCHY 64 select GENERIC_IRQ_CHIP 65 66config ARM_VIC 67 bool 68 select IRQ_DOMAIN 69 select GENERIC_IRQ_MULTI_HANDLER 70 71config ARM_VIC_NR 72 int 73 default 4 if ARCH_S5PV210 74 default 2 75 depends on ARM_VIC 76 help 77 The maximum number of VICs available in the system, for 78 power management. 79 80config ARMADA_370_XP_IRQ 81 bool 82 select GENERIC_IRQ_CHIP 83 select PCI_MSI if PCI 84 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 85 86config ALPINE_MSI 87 bool 88 depends on PCI 89 select PCI_MSI 90 select GENERIC_IRQ_CHIP 91 92config ATMEL_AIC_IRQ 93 bool 94 select GENERIC_IRQ_CHIP 95 select IRQ_DOMAIN 96 select GENERIC_IRQ_MULTI_HANDLER 97 select SPARSE_IRQ 98 99config ATMEL_AIC5_IRQ 100 bool 101 select GENERIC_IRQ_CHIP 102 select IRQ_DOMAIN 103 select GENERIC_IRQ_MULTI_HANDLER 104 select SPARSE_IRQ 105 106config I8259 107 bool 108 select IRQ_DOMAIN 109 110config BCM6345_L1_IRQ 111 bool 112 select GENERIC_IRQ_CHIP 113 select IRQ_DOMAIN 114 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 115 116config BCM7038_L1_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121 122config BCM7120_L2_IRQ 123 bool 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 127config BRCMSTB_L2_IRQ 128 bool 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 132config DW_APB_ICTL 133 bool 134 select GENERIC_IRQ_CHIP 135 select IRQ_DOMAIN 136 137config FARADAY_FTINTC010 138 bool 139 select IRQ_DOMAIN 140 select GENERIC_IRQ_MULTI_HANDLER 141 select SPARSE_IRQ 142 143config HISILICON_IRQ_MBIGEN 144 bool 145 select ARM_GIC_V3 146 select ARM_GIC_V3_ITS 147 148config IMGPDC_IRQ 149 bool 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN 152 153config MADERA_IRQ 154 tristate 155 156config IRQ_MIPS_CPU 157 bool 158 select GENERIC_IRQ_CHIP 159 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 160 select IRQ_DOMAIN 161 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 162 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 163 164config CLPS711X_IRQCHIP 165 bool 166 depends on ARCH_CLPS711X 167 select IRQ_DOMAIN 168 select GENERIC_IRQ_MULTI_HANDLER 169 select SPARSE_IRQ 170 default y 171 172config OMPIC 173 bool 174 175config OR1K_PIC 176 bool 177 select IRQ_DOMAIN 178 179config OMAP_IRQCHIP 180 bool 181 select GENERIC_IRQ_CHIP 182 select IRQ_DOMAIN 183 184config ORION_IRQCHIP 185 bool 186 select IRQ_DOMAIN 187 select GENERIC_IRQ_MULTI_HANDLER 188 189config PIC32_EVIC 190 bool 191 select GENERIC_IRQ_CHIP 192 select IRQ_DOMAIN 193 194config JCORE_AIC 195 bool "J-Core integrated AIC" if COMPILE_TEST 196 depends on OF 197 select IRQ_DOMAIN 198 help 199 Support for the J-Core integrated AIC. 200 201config RDA_INTC 202 bool 203 select IRQ_DOMAIN 204 205config RENESAS_INTC_IRQPIN 206 bool 207 select IRQ_DOMAIN 208 209config RENESAS_IRQC 210 bool 211 select GENERIC_IRQ_CHIP 212 select IRQ_DOMAIN 213 214config ST_IRQCHIP 215 bool 216 select REGMAP 217 select MFD_SYSCON 218 help 219 Enables SysCfg Controlled IRQs on STi based platforms. 220 221config TANGO_IRQ 222 bool 223 select IRQ_DOMAIN 224 select GENERIC_IRQ_CHIP 225 226config TB10X_IRQC 227 bool 228 select IRQ_DOMAIN 229 select GENERIC_IRQ_CHIP 230 231config TS4800_IRQ 232 tristate "TS-4800 IRQ controller" 233 select IRQ_DOMAIN 234 depends on HAS_IOMEM 235 depends on SOC_IMX51 || COMPILE_TEST 236 help 237 Support for the TS-4800 FPGA IRQ controller 238 239config VERSATILE_FPGA_IRQ 240 bool 241 select IRQ_DOMAIN 242 243config VERSATILE_FPGA_IRQ_NR 244 int 245 default 4 246 depends on VERSATILE_FPGA_IRQ 247 248config XTENSA_MX 249 bool 250 select IRQ_DOMAIN 251 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 252 253config XILINX_INTC 254 bool 255 select IRQ_DOMAIN 256 257config IRQ_CROSSBAR 258 bool 259 help 260 Support for a CROSSBAR ip that precedes the main interrupt controller. 261 The primary irqchip invokes the crossbar's callback which inturn allocates 262 a free irq and configures the IP. Thus the peripheral interrupts are 263 routed to one of the free irqchip interrupt lines. 264 265config KEYSTONE_IRQ 266 tristate "Keystone 2 IRQ controller IP" 267 depends on ARCH_KEYSTONE 268 help 269 Support for Texas Instruments Keystone 2 IRQ controller IP which 270 is part of the Keystone 2 IPC mechanism 271 272config MIPS_GIC 273 bool 274 select GENERIC_IRQ_IPI 275 select IRQ_DOMAIN_HIERARCHY 276 select MIPS_CM 277 278config INGENIC_IRQ 279 bool 280 depends on MACH_INGENIC 281 default y 282 283config RENESAS_H8300H_INTC 284 bool 285 select IRQ_DOMAIN 286 287config RENESAS_H8S_INTC 288 bool 289 select IRQ_DOMAIN 290 291config IMX_GPCV2 292 bool 293 select IRQ_DOMAIN 294 help 295 Enables the wakeup IRQs for IMX platforms with GPCv2 block 296 297config IRQ_MXS 298 def_bool y if MACH_ASM9260 || ARCH_MXS 299 select IRQ_DOMAIN 300 select STMP_DEVICE 301 302config MSCC_OCELOT_IRQ 303 bool 304 select IRQ_DOMAIN 305 select GENERIC_IRQ_CHIP 306 307config MVEBU_GICP 308 bool 309 310config MVEBU_ICU 311 bool 312 313config MVEBU_ODMI 314 bool 315 select GENERIC_MSI_IRQ_DOMAIN 316 317config MVEBU_PIC 318 bool 319 320config MVEBU_SEI 321 bool 322 323config LS_SCFG_MSI 324 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 325 depends on PCI && PCI_MSI 326 327config PARTITION_PERCPU 328 bool 329 330config EZNPS_GIC 331 bool "NPS400 Global Interrupt Manager (GIM)" 332 depends on ARC || (COMPILE_TEST && !64BIT) 333 select IRQ_DOMAIN 334 help 335 Support the EZchip NPS400 global interrupt controller 336 337config STM32_EXTI 338 bool 339 select IRQ_DOMAIN 340 select GENERIC_IRQ_CHIP 341 342config QCOM_IRQ_COMBINER 343 bool "QCOM IRQ combiner support" 344 depends on ARCH_QCOM && ACPI 345 select IRQ_DOMAIN 346 select IRQ_DOMAIN_HIERARCHY 347 help 348 Say yes here to add support for the IRQ combiner devices embedded 349 in Qualcomm Technologies chips. 350 351config IRQ_UNIPHIER_AIDET 352 bool "UniPhier AIDET support" if COMPILE_TEST 353 depends on ARCH_UNIPHIER || COMPILE_TEST 354 default ARCH_UNIPHIER 355 select IRQ_DOMAIN_HIERARCHY 356 help 357 Support for the UniPhier AIDET (ARM Interrupt Detector). 358 359config MESON_IRQ_GPIO 360 bool "Meson GPIO Interrupt Multiplexer" 361 depends on ARCH_MESON 362 select IRQ_DOMAIN 363 select IRQ_DOMAIN_HIERARCHY 364 help 365 Support Meson SoC Family GPIO Interrupt Multiplexer 366 367config GOLDFISH_PIC 368 bool "Goldfish programmable interrupt controller" 369 depends on MIPS && (GOLDFISH || COMPILE_TEST) 370 select IRQ_DOMAIN 371 help 372 Say yes here to enable Goldfish interrupt controller driver used 373 for Goldfish based virtual platforms. 374 375config QCOM_PDC 376 bool "QCOM PDC" 377 depends on ARCH_QCOM 378 select IRQ_DOMAIN 379 select IRQ_DOMAIN_HIERARCHY 380 help 381 Power Domain Controller driver to manage and configure wakeup 382 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 383 384config CSKY_MPINTC 385 bool "C-SKY Multi Processor Interrupt Controller" 386 depends on CSKY 387 help 388 Say yes here to enable C-SKY SMP interrupt controller driver used 389 for C-SKY SMP system. 390 In fact it's not mmio map in hw and it use ld/st to visit the 391 controller's register inside CPU. 392 393config CSKY_APB_INTC 394 bool "C-SKY APB Interrupt Controller" 395 depends on CSKY 396 help 397 Say yes here to enable C-SKY APB interrupt controller driver used 398 by C-SKY single core SOC system. It use mmio map apb-bus to visit 399 the controller's register. 400 401config IMX_IRQSTEER 402 bool "i.MX IRQSTEER support" 403 depends on ARCH_MXC || COMPILE_TEST 404 default ARCH_MXC 405 select IRQ_DOMAIN 406 help 407 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 408 409endmenu 410 411config SIFIVE_PLIC 412 bool "SiFive Platform-Level Interrupt Controller" 413 depends on RISCV 414 help 415 This enables support for the PLIC chip found in SiFive (and 416 potentially other) RISC-V systems. The PLIC controls devices 417 interrupts and connects them to each core's local interrupt 418 controller. Aside from timer and software interrupts, all other 419 interrupt sources are subordinate to the PLIC. 420 421 If you don't know what to do here, say Y. 422