1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select GENERIC_IRQ_MULTI_HANDLER 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ_DOMAIN 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 select GENERIC_IRQ_MULTI_HANDLER 68 69config ARM_VIC_NR 70 int 71 default 4 if ARCH_S5PV210 72 default 2 73 depends on ARM_VIC 74 help 75 The maximum number of VICs available in the system, for 76 power management. 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF || COMPILE_TEST 93 select GENERIC_IRQ_CHIP 94 select IRQ_DOMAIN 95 help 96 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 97 98config ATMEL_AIC_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 select GENERIC_IRQ_MULTI_HANDLER 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select GENERIC_IRQ_MULTI_HANDLER 110 select SPARSE_IRQ 111 112config I8259 113 bool 114 select IRQ_DOMAIN 115 116config BCM6345_L1_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121 122config BCM7038_L1_IRQ 123 bool 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 127 128config BCM7120_L2_IRQ 129 bool 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 bool 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN 137 138config DAVINCI_AINTC 139 bool 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DAVINCI_CP_INTC 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN 147 148config DW_APB_ICTL 149 bool 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN 152 153config FARADAY_FTINTC010 154 bool 155 select IRQ_DOMAIN 156 select GENERIC_IRQ_MULTI_HANDLER 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select GENERIC_IRQ_MULTI_HANDLER 173 select SPARSE_IRQ 174 175config MADERA_IRQ 176 tristate 177 178config IRQ_MIPS_CPU 179 bool 180 select GENERIC_IRQ_CHIP 181 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 182 select IRQ_DOMAIN 183 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 184 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 185 186config CLPS711X_IRQCHIP 187 bool 188 depends on ARCH_CLPS711X 189 select IRQ_DOMAIN 190 select GENERIC_IRQ_MULTI_HANDLER 191 select SPARSE_IRQ 192 default y 193 194config OMPIC 195 bool 196 197config OR1K_PIC 198 bool 199 select IRQ_DOMAIN 200 201config OMAP_IRQCHIP 202 bool 203 select GENERIC_IRQ_CHIP 204 select IRQ_DOMAIN 205 206config ORION_IRQCHIP 207 bool 208 select IRQ_DOMAIN 209 select GENERIC_IRQ_MULTI_HANDLER 210 211config PIC32_EVIC 212 bool 213 select GENERIC_IRQ_CHIP 214 select IRQ_DOMAIN 215 216config JCORE_AIC 217 bool "J-Core integrated AIC" if COMPILE_TEST 218 depends on OF 219 select IRQ_DOMAIN 220 help 221 Support for the J-Core integrated AIC. 222 223config RDA_INTC 224 bool 225 select IRQ_DOMAIN 226 227config RENESAS_INTC_IRQPIN 228 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 229 select IRQ_DOMAIN 230 help 231 Enable support for the Renesas Interrupt Controller for external 232 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 233 234config RENESAS_IRQC 235 bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST 236 select GENERIC_IRQ_CHIP 237 select IRQ_DOMAIN 238 help 239 Enable support for the Renesas Interrupt Controller for external 240 devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs. 241 242config RENESAS_RZA1_IRQC 243 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 244 select IRQ_DOMAIN_HIERARCHY 245 help 246 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 247 to 8 external interrupts with configurable sense select. 248 249config ST_IRQCHIP 250 bool 251 select REGMAP 252 select MFD_SYSCON 253 help 254 Enables SysCfg Controlled IRQs on STi based platforms. 255 256config TANGO_IRQ 257 bool 258 select IRQ_DOMAIN 259 select GENERIC_IRQ_CHIP 260 261config TB10X_IRQC 262 bool 263 select IRQ_DOMAIN 264 select GENERIC_IRQ_CHIP 265 266config TS4800_IRQ 267 tristate "TS-4800 IRQ controller" 268 select IRQ_DOMAIN 269 depends on HAS_IOMEM 270 depends on SOC_IMX51 || COMPILE_TEST 271 help 272 Support for the TS-4800 FPGA IRQ controller 273 274config VERSATILE_FPGA_IRQ 275 bool 276 select IRQ_DOMAIN 277 278config VERSATILE_FPGA_IRQ_NR 279 int 280 default 4 281 depends on VERSATILE_FPGA_IRQ 282 283config XTENSA_MX 284 bool 285 select IRQ_DOMAIN 286 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 287 288config XILINX_INTC 289 bool 290 select IRQ_DOMAIN 291 292config IRQ_CROSSBAR 293 bool 294 help 295 Support for a CROSSBAR ip that precedes the main interrupt controller. 296 The primary irqchip invokes the crossbar's callback which inturn allocates 297 a free irq and configures the IP. Thus the peripheral interrupts are 298 routed to one of the free irqchip interrupt lines. 299 300config KEYSTONE_IRQ 301 tristate "Keystone 2 IRQ controller IP" 302 depends on ARCH_KEYSTONE 303 help 304 Support for Texas Instruments Keystone 2 IRQ controller IP which 305 is part of the Keystone 2 IPC mechanism 306 307config MIPS_GIC 308 bool 309 select GENERIC_IRQ_IPI 310 select IRQ_DOMAIN_HIERARCHY 311 select MIPS_CM 312 313config INGENIC_IRQ 314 bool 315 depends on MACH_INGENIC 316 default y 317 318config INGENIC_TCU_IRQ 319 bool "Ingenic JZ47xx TCU interrupt controller" 320 default MACH_INGENIC 321 depends on MIPS || COMPILE_TEST 322 select MFD_SYSCON 323 select GENERIC_IRQ_CHIP 324 help 325 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 326 JZ47xx SoCs. 327 328 If unsure, say N. 329 330config RENESAS_H8300H_INTC 331 bool 332 select IRQ_DOMAIN 333 334config RENESAS_H8S_INTC 335 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 336 select IRQ_DOMAIN 337 help 338 Enable support for the Renesas H8/300 Interrupt Controller, as found 339 on Renesas H8S SoCs. 340 341config IMX_GPCV2 342 bool 343 select IRQ_DOMAIN 344 help 345 Enables the wakeup IRQs for IMX platforms with GPCv2 block 346 347config IRQ_MXS 348 def_bool y if MACH_ASM9260 || ARCH_MXS 349 select IRQ_DOMAIN 350 select STMP_DEVICE 351 352config MSCC_OCELOT_IRQ 353 bool 354 select IRQ_DOMAIN 355 select GENERIC_IRQ_CHIP 356 357config MVEBU_GICP 358 bool 359 360config MVEBU_ICU 361 bool 362 363config MVEBU_ODMI 364 bool 365 select GENERIC_MSI_IRQ_DOMAIN 366 367config MVEBU_PIC 368 bool 369 370config MVEBU_SEI 371 bool 372 373config LS_EXTIRQ 374 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 375 select MFD_SYSCON 376 377config LS_SCFG_MSI 378 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 379 depends on PCI && PCI_MSI 380 381config PARTITION_PERCPU 382 bool 383 384config EZNPS_GIC 385 bool "NPS400 Global Interrupt Manager (GIM)" 386 depends on ARC || (COMPILE_TEST && !64BIT) 387 select IRQ_DOMAIN 388 help 389 Support the EZchip NPS400 global interrupt controller 390 391config STM32_EXTI 392 bool 393 select IRQ_DOMAIN 394 select GENERIC_IRQ_CHIP 395 396config QCOM_IRQ_COMBINER 397 bool "QCOM IRQ combiner support" 398 depends on ARCH_QCOM && ACPI 399 select IRQ_DOMAIN_HIERARCHY 400 help 401 Say yes here to add support for the IRQ combiner devices embedded 402 in Qualcomm Technologies chips. 403 404config IRQ_UNIPHIER_AIDET 405 bool "UniPhier AIDET support" if COMPILE_TEST 406 depends on ARCH_UNIPHIER || COMPILE_TEST 407 default ARCH_UNIPHIER 408 select IRQ_DOMAIN_HIERARCHY 409 help 410 Support for the UniPhier AIDET (ARM Interrupt Detector). 411 412config MESON_IRQ_GPIO 413 bool "Meson GPIO Interrupt Multiplexer" 414 depends on ARCH_MESON 415 select IRQ_DOMAIN_HIERARCHY 416 help 417 Support Meson SoC Family GPIO Interrupt Multiplexer 418 419config GOLDFISH_PIC 420 bool "Goldfish programmable interrupt controller" 421 depends on MIPS && (GOLDFISH || COMPILE_TEST) 422 select IRQ_DOMAIN 423 help 424 Say yes here to enable Goldfish interrupt controller driver used 425 for Goldfish based virtual platforms. 426 427config QCOM_PDC 428 bool "QCOM PDC" 429 depends on ARCH_QCOM 430 select IRQ_DOMAIN_HIERARCHY 431 help 432 Power Domain Controller driver to manage and configure wakeup 433 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 434 435config CSKY_MPINTC 436 bool "C-SKY Multi Processor Interrupt Controller" 437 depends on CSKY 438 help 439 Say yes here to enable C-SKY SMP interrupt controller driver used 440 for C-SKY SMP system. 441 In fact it's not mmio map in hardware and it uses ld/st to visit the 442 controller's register inside CPU. 443 444config CSKY_APB_INTC 445 bool "C-SKY APB Interrupt Controller" 446 depends on CSKY 447 help 448 Say yes here to enable C-SKY APB interrupt controller driver used 449 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 450 the controller's register. 451 452config IMX_IRQSTEER 453 bool "i.MX IRQSTEER support" 454 depends on ARCH_MXC || COMPILE_TEST 455 default ARCH_MXC 456 select IRQ_DOMAIN 457 help 458 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 459 460config IMX_INTMUX 461 def_bool y if ARCH_MXC || COMPILE_TEST 462 select IRQ_DOMAIN 463 help 464 Support for the i.MX INTMUX interrupt multiplexer. 465 466config LS1X_IRQ 467 bool "Loongson-1 Interrupt Controller" 468 depends on MACH_LOONGSON32 469 default y 470 select IRQ_DOMAIN 471 select GENERIC_IRQ_CHIP 472 help 473 Support for the Loongson-1 platform Interrupt Controller. 474 475config TI_SCI_INTR_IRQCHIP 476 bool 477 depends on TI_SCI_PROTOCOL 478 select IRQ_DOMAIN_HIERARCHY 479 help 480 This enables the irqchip driver support for K3 Interrupt router 481 over TI System Control Interface available on some new TI's SoCs. 482 If you wish to use interrupt router irq resources managed by the 483 TI System Controller, say Y here. Otherwise, say N. 484 485config TI_SCI_INTA_IRQCHIP 486 bool 487 depends on TI_SCI_PROTOCOL 488 select IRQ_DOMAIN_HIERARCHY 489 select TI_SCI_INTA_MSI_DOMAIN 490 help 491 This enables the irqchip driver support for K3 Interrupt aggregator 492 over TI System Control Interface available on some new TI's SoCs. 493 If you wish to use interrupt aggregator irq resources managed by the 494 TI System Controller, say Y here. Otherwise, say N. 495 496config RISCV_INTC 497 bool "RISC-V Local Interrupt Controller" 498 depends on RISCV 499 default y 500 help 501 This enables support for the per-HART local interrupt controller 502 found in standard RISC-V systems. The per-HART local interrupt 503 controller handles timer interrupts, software interrupts, and 504 hardware interrupts. Without a per-HART local interrupt controller, 505 a RISC-V system will be unable to handle any interrupts. 506 507 If you don't know what to do here, say Y. 508 509config SIFIVE_PLIC 510 bool "SiFive Platform-Level Interrupt Controller" 511 depends on RISCV 512 select IRQ_DOMAIN_HIERARCHY 513 help 514 This enables support for the PLIC chip found in SiFive (and 515 potentially other) RISC-V systems. The PLIC controls devices 516 interrupts and connects them to each core's local interrupt 517 controller. Aside from timer and software interrupts, all other 518 interrupt sources are subordinate to the PLIC. 519 520 If you don't know what to do here, say Y. 521 522config EXYNOS_IRQ_COMBINER 523 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 524 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 525 help 526 Say yes here to add support for the IRQ combiner devices embedded 527 in Samsung Exynos chips. 528 529config LOONGSON_LIOINTC 530 bool "Loongson Local I/O Interrupt Controller" 531 depends on MACH_LOONGSON64 532 default y 533 select IRQ_DOMAIN 534 select GENERIC_IRQ_CHIP 535 help 536 Support for the Loongson Local I/O Interrupt Controller. 537 538config LOONGSON_HTPIC 539 bool "Loongson3 HyperTransport PIC Controller" 540 depends on MACH_LOONGSON64 541 default y 542 select IRQ_DOMAIN 543 select GENERIC_IRQ_CHIP 544 select I8259 545 help 546 Support for the Loongson-3 HyperTransport PIC Controller. 547 548config LOONGSON_HTVEC 549 bool "Loongson3 HyperTransport Interrupt Vector Controller" 550 depends on MACH_LOONGSON64 551 default MACH_LOONGSON64 552 select IRQ_DOMAIN_HIERARCHY 553 help 554 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 555 556config LOONGSON_PCH_PIC 557 bool "Loongson PCH PIC Controller" 558 depends on MACH_LOONGSON64 || COMPILE_TEST 559 default MACH_LOONGSON64 560 select IRQ_DOMAIN_HIERARCHY 561 select IRQ_FASTEOI_HIERARCHY_HANDLERS 562 help 563 Support for the Loongson PCH PIC Controller. 564 565config LOONGSON_PCH_MSI 566 bool "Loongson PCH PIC Controller" 567 depends on MACH_LOONGSON64 || COMPILE_TEST 568 depends on PCI 569 default MACH_LOONGSON64 570 select IRQ_DOMAIN_HIERARCHY 571 select PCI_MSI 572 help 573 Support for the Loongson PCH MSI Controller. 574 575endmenu 576