1f6e916b8SThomas Petazzoniconfig IRQCHIP 2f6e916b8SThomas Petazzoni def_bool y 3f6e916b8SThomas Petazzoni depends on OF_IRQ 4f6e916b8SThomas Petazzoni 581243e44SRob Herringconfig ARM_GIC 681243e44SRob Herring bool 781243e44SRob Herring select IRQ_DOMAIN 881243e44SRob Herring select MULTI_IRQ_HANDLER 981243e44SRob Herring 1081243e44SRob Herringconfig GIC_NON_BANKED 1181243e44SRob Herring bool 1281243e44SRob Herring 13021f6537SMarc Zyngierconfig ARM_GIC_V3 14021f6537SMarc Zyngier bool 15021f6537SMarc Zyngier select IRQ_DOMAIN 16021f6537SMarc Zyngier select MULTI_IRQ_HANDLER 17021f6537SMarc Zyngier 18292ec080SUwe Kleine-Königconfig ARM_NVIC 19292ec080SUwe Kleine-König bool 20292ec080SUwe Kleine-König select IRQ_DOMAIN 21292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 22292ec080SUwe Kleine-König 2344430ec0SRob Herringconfig ARM_VIC 2444430ec0SRob Herring bool 2544430ec0SRob Herring select IRQ_DOMAIN 2644430ec0SRob Herring select MULTI_IRQ_HANDLER 2744430ec0SRob Herring 2844430ec0SRob Herringconfig ARM_VIC_NR 2944430ec0SRob Herring int 3044430ec0SRob Herring default 4 if ARCH_S5PV210 3144430ec0SRob Herring default 3 if ARCH_S5PC100 3244430ec0SRob Herring default 2 3344430ec0SRob Herring depends on ARM_VIC 3444430ec0SRob Herring help 3544430ec0SRob Herring The maximum number of VICs available in the system, for 3644430ec0SRob Herring power management. 3744430ec0SRob Herring 38b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 39b1479ebbSBoris BREZILLON bool 40b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 41b1479ebbSBoris BREZILLON select IRQ_DOMAIN 42b1479ebbSBoris BREZILLON select MULTI_IRQ_HANDLER 43b1479ebbSBoris BREZILLON select SPARSE_IRQ 44b1479ebbSBoris BREZILLON 45b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 46b1479ebbSBoris BREZILLON bool 47b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 48b1479ebbSBoris BREZILLON select IRQ_DOMAIN 49b1479ebbSBoris BREZILLON select MULTI_IRQ_HANDLER 50b1479ebbSBoris BREZILLON select SPARSE_IRQ 51b1479ebbSBoris BREZILLON 527f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 537f646e92SFlorian Fainelli bool 547f646e92SFlorian Fainelli depends on ARM 557f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 567f646e92SFlorian Fainelli select IRQ_DOMAIN 577f646e92SFlorian Fainelli 58350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 59350d71b9SSebastian Hesselbarth bool 60350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 61350d71b9SSebastian Hesselbarth 62b6ef9161SJames Hoganconfig IMGPDC_IRQ 63b6ef9161SJames Hogan bool 64b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 65b6ef9161SJames Hogan select IRQ_DOMAIN 66b6ef9161SJames Hogan 67afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 68afc98d90SAlexander Shiyan bool 69afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 70afc98d90SAlexander Shiyan select IRQ_DOMAIN 71afc98d90SAlexander Shiyan select MULTI_IRQ_HANDLER 72afc98d90SAlexander Shiyan select SPARSE_IRQ 73afc98d90SAlexander Shiyan default y 74afc98d90SAlexander Shiyan 754db8e6d2SStefan Kristianssonconfig OR1K_PIC 764db8e6d2SStefan Kristiansson bool 774db8e6d2SStefan Kristiansson select IRQ_DOMAIN 784db8e6d2SStefan Kristiansson 799dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 809dbd90f1SSebastian Hesselbarth bool 819dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 829dbd90f1SSebastian Hesselbarth select MULTI_IRQ_HANDLER 839dbd90f1SSebastian Hesselbarth 8444358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 8544358048SMagnus Damm bool 8644358048SMagnus Damm select IRQ_DOMAIN 8744358048SMagnus Damm 88fbc83b7fSMagnus Dammconfig RENESAS_IRQC 89fbc83b7fSMagnus Damm bool 90fbc83b7fSMagnus Damm select IRQ_DOMAIN 91fbc83b7fSMagnus Damm 92b06eb017SChristian Ruppertconfig TB10X_IRQC 93b06eb017SChristian Ruppert bool 94b06eb017SChristian Ruppert select IRQ_DOMAIN 95b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 96b06eb017SChristian Ruppert 972389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 982389d501SLinus Walleij bool 992389d501SLinus Walleij select IRQ_DOMAIN 1002389d501SLinus Walleij 1012389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 1022389d501SLinus Walleij int 1032389d501SLinus Walleij default 4 1042389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 10526a8e96aSMax Filippov 10626a8e96aSMax Filippovconfig XTENSA_MX 10726a8e96aSMax Filippov bool 10826a8e96aSMax Filippov select IRQ_DOMAIN 10996ca848eSSricharan R 11096ca848eSSricharan Rconfig IRQ_CROSSBAR 11196ca848eSSricharan R bool 11296ca848eSSricharan R help 113*f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 11496ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 11596ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 11696ca848eSSricharan R routed to one of the free irqchip interrupt lines. 117