1f6e916b8SThomas Petazzoniconfig IRQCHIP 2f6e916b8SThomas Petazzoni def_bool y 3f6e916b8SThomas Petazzoni depends on OF_IRQ 4f6e916b8SThomas Petazzoni 581243e44SRob Herringconfig ARM_GIC 681243e44SRob Herring bool 781243e44SRob Herring select IRQ_DOMAIN 881243e44SRob Herring select MULTI_IRQ_HANDLER 981243e44SRob Herring 1081243e44SRob Herringconfig GIC_NON_BANKED 1181243e44SRob Herring bool 1281243e44SRob Herring 13021f6537SMarc Zyngierconfig ARM_GIC_V3 14021f6537SMarc Zyngier bool 15021f6537SMarc Zyngier select IRQ_DOMAIN 16021f6537SMarc Zyngier select MULTI_IRQ_HANDLER 17021f6537SMarc Zyngier 18292ec080SUwe Kleine-Königconfig ARM_NVIC 19292ec080SUwe Kleine-König bool 20292ec080SUwe Kleine-König select IRQ_DOMAIN 21292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 22292ec080SUwe Kleine-König 2344430ec0SRob Herringconfig ARM_VIC 2444430ec0SRob Herring bool 2544430ec0SRob Herring select IRQ_DOMAIN 2644430ec0SRob Herring select MULTI_IRQ_HANDLER 2744430ec0SRob Herring 2844430ec0SRob Herringconfig ARM_VIC_NR 2944430ec0SRob Herring int 3044430ec0SRob Herring default 4 if ARCH_S5PV210 3144430ec0SRob Herring default 2 3244430ec0SRob Herring depends on ARM_VIC 3344430ec0SRob Herring help 3444430ec0SRob Herring The maximum number of VICs available in the system, for 3544430ec0SRob Herring power management. 3644430ec0SRob Herring 37b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 38b1479ebbSBoris BREZILLON bool 39b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 40b1479ebbSBoris BREZILLON select IRQ_DOMAIN 41b1479ebbSBoris BREZILLON select MULTI_IRQ_HANDLER 42b1479ebbSBoris BREZILLON select SPARSE_IRQ 43b1479ebbSBoris BREZILLON 44b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 45b1479ebbSBoris BREZILLON bool 46b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 47b1479ebbSBoris BREZILLON select IRQ_DOMAIN 48b1479ebbSBoris BREZILLON select MULTI_IRQ_HANDLER 49b1479ebbSBoris BREZILLON select SPARSE_IRQ 50b1479ebbSBoris BREZILLON 517f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 527f646e92SFlorian Fainelli bool 537f646e92SFlorian Fainelli depends on ARM 547f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 557f646e92SFlorian Fainelli select IRQ_DOMAIN 567f646e92SFlorian Fainelli 57350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 58350d71b9SSebastian Hesselbarth bool 59*e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 60350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 61350d71b9SSebastian Hesselbarth 62b6ef9161SJames Hoganconfig IMGPDC_IRQ 63b6ef9161SJames Hogan bool 64b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 65b6ef9161SJames Hogan select IRQ_DOMAIN 66b6ef9161SJames Hogan 67afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 68afc98d90SAlexander Shiyan bool 69afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 70afc98d90SAlexander Shiyan select IRQ_DOMAIN 71afc98d90SAlexander Shiyan select MULTI_IRQ_HANDLER 72afc98d90SAlexander Shiyan select SPARSE_IRQ 73afc98d90SAlexander Shiyan default y 74afc98d90SAlexander Shiyan 754db8e6d2SStefan Kristianssonconfig OR1K_PIC 764db8e6d2SStefan Kristiansson bool 774db8e6d2SStefan Kristiansson select IRQ_DOMAIN 784db8e6d2SStefan Kristiansson 798598066cSFelipe Balbiconfig OMAP_IRQCHIP 808598066cSFelipe Balbi bool 818598066cSFelipe Balbi select GENERIC_IRQ_CHIP 828598066cSFelipe Balbi select IRQ_DOMAIN 838598066cSFelipe Balbi 849dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 859dbd90f1SSebastian Hesselbarth bool 869dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 879dbd90f1SSebastian Hesselbarth select MULTI_IRQ_HANDLER 889dbd90f1SSebastian Hesselbarth 8944358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 9044358048SMagnus Damm bool 9144358048SMagnus Damm select IRQ_DOMAIN 9244358048SMagnus Damm 93fbc83b7fSMagnus Dammconfig RENESAS_IRQC 94fbc83b7fSMagnus Damm bool 95fbc83b7fSMagnus Damm select IRQ_DOMAIN 96fbc83b7fSMagnus Damm 97b06eb017SChristian Ruppertconfig TB10X_IRQC 98b06eb017SChristian Ruppert bool 99b06eb017SChristian Ruppert select IRQ_DOMAIN 100b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 101b06eb017SChristian Ruppert 1022389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 1032389d501SLinus Walleij bool 1042389d501SLinus Walleij select IRQ_DOMAIN 1052389d501SLinus Walleij 1062389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 1072389d501SLinus Walleij int 1082389d501SLinus Walleij default 4 1092389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 11026a8e96aSMax Filippov 11126a8e96aSMax Filippovconfig XTENSA_MX 11226a8e96aSMax Filippov bool 11326a8e96aSMax Filippov select IRQ_DOMAIN 11496ca848eSSricharan R 11596ca848eSSricharan Rconfig IRQ_CROSSBAR 11696ca848eSSricharan R bool 11796ca848eSSricharan R help 118f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 11996ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 12096ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 12196ca848eSSricharan R routed to one of the free irqchip interrupt lines. 12289323f8cSGrygorii Strashko 12389323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 12489323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 12589323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 12689323f8cSGrygorii Strashko help 12789323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 12889323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 129