1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 31853a33ceSSuravee Suthikulpanit 3281243e44SRob Herringconfig GIC_NON_BANKED 3381243e44SRob Herring bool 3481243e44SRob Herring 35021f6537SMarc Zyngierconfig ARM_GIC_V3 36021f6537SMarc Zyngier bool 37443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 38e3825ba1SMarc Zyngier select PARTITION_PERCPU 390e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4035727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 41021f6537SMarc Zyngier 4219812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4319812729SMarc Zyngier bool 4413e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4548f71d56SThomas Gleixner select IRQ_MSI_LIB 4629f41139SMarc Zyngier default ARM_GIC_V3 4729f41139SMarc Zyngier 4829f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4929f41139SMarc Zyngier bool 5029f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 513ee80364SArnd Bergmann depends on PCI 523ee80364SArnd Bergmann depends on PCI_MSI 5329f41139SMarc Zyngier default ARM_GIC_V3_ITS 54292ec080SUwe Kleine-König 557afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 567afe031cSBogdan Purcareata bool 577afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata depends on FSL_MC_BUS 597afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 607afe031cSBogdan Purcareata 6144430ec0SRob Herringconfig ARM_NVIC 6244430ec0SRob Herring bool 632d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6444430ec0SRob Herring select GENERIC_IRQ_CHIP 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC 6744430ec0SRob Herring bool 6844430ec0SRob Herring select IRQ_DOMAIN 6944430ec0SRob Herring 7044430ec0SRob Herringconfig ARM_VIC_NR 7144430ec0SRob Herring int 7244430ec0SRob Herring default 4 if ARCH_S5PV210 7344430ec0SRob Herring default 2 7444430ec0SRob Herring depends on ARM_VIC 7544430ec0SRob Herring help 7644430ec0SRob Herring The maximum number of VICs available in the system, for 7744430ec0SRob Herring power management. 7844430ec0SRob Herring 7972e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 8072e257c6SThomas Gleixner bool 8172e257c6SThomas Gleixner 82fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 83fed6d336SThomas Petazzoni bool 84fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 853ee80364SArnd Bergmann select PCI_MSI if PCI 860e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 87fed6d336SThomas Petazzoni 88e6b78f2cSAntoine Tenartconfig ALPINE_MSI 89e6b78f2cSAntoine Tenart bool 903ee80364SArnd Bergmann depends on PCI 913ee80364SArnd Bergmann select PCI_MSI 92e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 93e6b78f2cSAntoine Tenart 941eb77c3bSTalel Shenharconfig AL_FIC 951eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 969869f37aSJean Delvare depends on OF 9735e0cd77SBaoquan He depends on HAS_IOMEM 981eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 991eb77c3bSTalel Shenhar select IRQ_DOMAIN 1001eb77c3bSTalel Shenhar help 1011eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1021eb77c3bSTalel Shenhar 103b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 104b1479ebbSBoris BREZILLON bool 105b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 106b1479ebbSBoris BREZILLON select IRQ_DOMAIN 107b1479ebbSBoris BREZILLON select SPARSE_IRQ 108b1479ebbSBoris BREZILLON 109b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 110b1479ebbSBoris BREZILLON bool 111b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 112b1479ebbSBoris BREZILLON select IRQ_DOMAIN 113b1479ebbSBoris BREZILLON select SPARSE_IRQ 114b1479ebbSBoris BREZILLON 1150509cfdeSRalf Baechleconfig I8259 1160509cfdeSRalf Baechle bool 1170509cfdeSRalf Baechle select IRQ_DOMAIN 1180509cfdeSRalf Baechle 119c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 120c7c42ec2SSimon Arlott bool 121c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 122c7c42ec2SSimon Arlott select IRQ_DOMAIN 1230e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 124c7c42ec2SSimon Arlott 1255f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 126c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 127c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 128c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1295f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1305f7f0317SKevin Cernekee select IRQ_DOMAIN 1310e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1325f7f0317SKevin Cernekee 133a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1343ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1353ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1363ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 137a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 138a4fcbb86SKevin Cernekee select IRQ_DOMAIN 139a4fcbb86SKevin Cernekee 1407f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 14151d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 14251d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 14351d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1447f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1457f646e92SFlorian Fainelli select IRQ_DOMAIN 1467f646e92SFlorian Fainelli 1470fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1480fc3d74cSBartosz Golaszewski bool 1490fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1500fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1510fc3d74cSBartosz Golaszewski 152350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 153350d71b9SSebastian Hesselbarth bool 154e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15554a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 156350d71b9SSebastian Hesselbarth 1576ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1586ee532e2SLinus Walleij bool 1596ee532e2SLinus Walleij select IRQ_DOMAIN 1606ee532e2SLinus Walleij select SPARSE_IRQ 1616ee532e2SLinus Walleij 1629a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1639a7c4abdSMaJun bool 1649a7c4abdSMaJun select ARM_GIC_V3 1659a7c4abdSMaJun select ARM_GIC_V3_ITS 1669a7c4abdSMaJun 167b6ef9161SJames Hoganconfig IMGPDC_IRQ 168b6ef9161SJames Hogan bool 169b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 170b6ef9161SJames Hogan select IRQ_DOMAIN 171b6ef9161SJames Hogan 1725b978c10SLinus Walleijconfig IXP4XX_IRQ 1735b978c10SLinus Walleij bool 1745b978c10SLinus Walleij select IRQ_DOMAIN 1755b978c10SLinus Walleij select SPARSE_IRQ 1765b978c10SLinus Walleij 177da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 178da0abe1aSRichard Fitzgerald tristate 179da0abe1aSRichard Fitzgerald 18067e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 18167e38cf2SRalf Baechle bool 18267e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1830f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 18467e38cf2SRalf Baechle select IRQ_DOMAIN 1850e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 18667e38cf2SRalf Baechle 187afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 188afc98d90SAlexander Shiyan bool 189afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 190afc98d90SAlexander Shiyan select IRQ_DOMAIN 191afc98d90SAlexander Shiyan select SPARSE_IRQ 192afc98d90SAlexander Shiyan default y 193afc98d90SAlexander Shiyan 1949b54470aSStafford Horneconfig OMPIC 1959b54470aSStafford Horne bool 1969b54470aSStafford Horne 1974db8e6d2SStefan Kristianssonconfig OR1K_PIC 1984db8e6d2SStefan Kristiansson bool 1994db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2004db8e6d2SStefan Kristiansson 2018598066cSFelipe Balbiconfig OMAP_IRQCHIP 2028598066cSFelipe Balbi bool 2038598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2048598066cSFelipe Balbi select IRQ_DOMAIN 2058598066cSFelipe Balbi 2069dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2079dbd90f1SSebastian Hesselbarth bool 2089dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2099dbd90f1SSebastian Hesselbarth 210aaa8666aSCristian Birsanconfig PIC32_EVIC 211aaa8666aSCristian Birsan bool 212aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 213aaa8666aSCristian Birsan select IRQ_DOMAIN 214aaa8666aSCristian Birsan 215981b58f6SRich Felkerconfig JCORE_AIC 2163602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2173602ffdeSRich Felker depends on OF 218981b58f6SRich Felker select IRQ_DOMAIN 219981b58f6SRich Felker help 220981b58f6SRich Felker Support for the J-Core integrated AIC. 221981b58f6SRich Felker 222d852e62aSManivannan Sadhasivamconfig RDA_INTC 223d852e62aSManivannan Sadhasivam bool 224d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 225d852e62aSManivannan Sadhasivam 22644358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 22702d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 22844358048SMagnus Damm select IRQ_DOMAIN 22902d7e041SGeert Uytterhoeven help 23002d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23102d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 23244358048SMagnus Damm 233fbc83b7fSMagnus Dammconfig RENESAS_IRQC 23472d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 23599c221dfSMagnus Damm select GENERIC_IRQ_CHIP 236fbc83b7fSMagnus Damm select IRQ_DOMAIN 23702d7e041SGeert Uytterhoeven help 23802d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23972d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 240fbc83b7fSMagnus Damm 241a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 24202d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 243a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 24402d7e041SGeert Uytterhoeven help 24502d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 24602d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 247a644ccb8SGeert Uytterhoeven 2483fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2493fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2503fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2513fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2523fed0955SLad Prabhakar help 2533fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2543fed0955SLad Prabhakar for external devices. 2553fed0955SLad Prabhakar 25603ac990eSMichael Walleconfig SL28CPLD_INTC 25703ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 25803ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 25903ac990eSMichael Walle select REGMAP_IRQ 26003ac990eSMichael Walle help 26103ac990eSMichael Walle Interrupt controller driver for the board management controller 26203ac990eSMichael Walle found on the Kontron sl28 CPLD. 26303ac990eSMichael Walle 26407088484SLee Jonesconfig ST_IRQCHIP 26507088484SLee Jones bool 26607088484SLee Jones select REGMAP 26707088484SLee Jones select MFD_SYSCON 26807088484SLee Jones help 26907088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 27007088484SLee Jones 271d421fd6dSSamuel Hollandconfig SUN4I_INTC 272d421fd6dSSamuel Holland bool 273d421fd6dSSamuel Holland 274d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 275d421fd6dSSamuel Holland bool 276d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 277d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 278d421fd6dSSamuel Holland 279d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 280d421fd6dSSamuel Holland bool 281d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 282d421fd6dSSamuel Holland 283b06eb017SChristian Ruppertconfig TB10X_IRQC 284b06eb017SChristian Ruppert bool 285b06eb017SChristian Ruppert select IRQ_DOMAIN 286b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 287b06eb017SChristian Ruppert 288d01f8633SDamien Riegelconfig TS4800_IRQ 289d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 290d01f8633SDamien Riegel select IRQ_DOMAIN 2910df337cfSRichard Weinberger depends on HAS_IOMEM 292d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 293d01f8633SDamien Riegel help 294d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 295d01f8633SDamien Riegel 2962389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2972389d501SLinus Walleij bool 2982389d501SLinus Walleij select IRQ_DOMAIN 2992389d501SLinus Walleij 3002389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3012389d501SLinus Walleij int 3022389d501SLinus Walleij default 4 3032389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 30426a8e96aSMax Filippov 30526a8e96aSMax Filippovconfig XTENSA_MX 30626a8e96aSMax Filippov bool 30726a8e96aSMax Filippov select IRQ_DOMAIN 3080e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 30996ca848eSSricharan R 3100547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 311debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 312fd31000dSJamie Iles depends on OF_ADDRESS 3130547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 314debf69cfSRobert Hancock help 315debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 316debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 317debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3180547dc78SZubair Lutfullah Kakakhel 31996ca848eSSricharan Rconfig IRQ_CROSSBAR 32096ca848eSSricharan R bool 32196ca848eSSricharan R help 322f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 32396ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 32496ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 32596ca848eSSricharan R routed to one of the free irqchip interrupt lines. 32689323f8cSGrygorii Strashko 32789323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 32889323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 32989323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 33089323f8cSGrygorii Strashko help 33189323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 33289323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3338a19b8f1SAndrew Bresticker 3348a19b8f1SAndrew Brestickerconfig MIPS_GIC 3358a19b8f1SAndrew Bresticker bool 3368190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3378190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3388a19b8f1SAndrew Bresticker select MIPS_CM 3398a764482SYoshinori Sato 34044e08e70SPaul Burtonconfig INGENIC_IRQ 34144e08e70SPaul Burton bool 34244e08e70SPaul Burton depends on MACH_INGENIC 34344e08e70SPaul Burton default y 34478c10e55SLinus Torvalds 3459536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3469536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3479536eba0SPaul Cercueil default MACH_INGENIC 3489536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3499536eba0SPaul Cercueil select MFD_SYSCON 3508084499bSYueHaibing select GENERIC_IRQ_CHIP 3519536eba0SPaul Cercueil help 3529536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3539536eba0SPaul Cercueil JZ47xx SoCs. 3549536eba0SPaul Cercueil 3559536eba0SPaul Cercueil If unsure, say N. 3569536eba0SPaul Cercueil 357e324c4dcSShenwei Wangconfig IMX_GPCV2 358e324c4dcSShenwei Wang bool 359e324c4dcSShenwei Wang select IRQ_DOMAIN 360e324c4dcSShenwei Wang help 361e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3627e4ac676SOleksij Rempel 3637e4ac676SOleksij Rempelconfig IRQ_MXS 3647e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3657e4ac676SOleksij Rempel select IRQ_DOMAIN 3667e4ac676SOleksij Rempel select STMP_DEVICE 367c27f29bbSThomas Petazzoni 36819d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 36919d99164SAlexandre Belloni bool 37019d99164SAlexandre Belloni select IRQ_DOMAIN 37119d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 37219d99164SAlexandre Belloni 373a68a63cbSThomas Petazzoniconfig MVEBU_GICP 374cdb23872SThomas Gleixner select IRQ_MSI_LIB 375a68a63cbSThomas Petazzoni bool 376a68a63cbSThomas Petazzoni 377e0de91a9SThomas Petazzoniconfig MVEBU_ICU 378e0de91a9SThomas Petazzoni bool 379e0de91a9SThomas Petazzoni 380c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 381c27f29bbSThomas Petazzoni bool 382*e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 38313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 3849e2c986cSMarc Zyngier 385a109893bSThomas Petazzoniconfig MVEBU_PIC 386a109893bSThomas Petazzoni bool 387a109893bSThomas Petazzoni 38861ce8d8dSMiquel Raynalconfig MVEBU_SEI 38961ce8d8dSMiquel Raynal bool 39061ce8d8dSMiquel Raynal 3910dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3920dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3930dcd9f87SRasmus Villemoes select MFD_SYSCON 3940dcd9f87SRasmus Villemoes 395b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 396b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3979c1a7bfcSLukas Bulwahn depends on PCI_MSI 398b8f3ebe6SMinghuan Lian 3999e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4009e2c986cSMarc Zyngier bool 4010efacbbaSLinus Torvalds 402e0720416SAlexandre TORGUEconfig STM32_EXTI 403e0720416SAlexandre TORGUE bool 404e0720416SAlexandre TORGUE select IRQ_DOMAIN 4050e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 406f20cc9b0SAgustin Vega-Frias 407f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 408f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 409f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 410f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 411f20cc9b0SAgustin Vega-Frias help 412f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 413f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4145ed34d3aSMasahiro Yamada 4155ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4165ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4175ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4185ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4195ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4205ed34d3aSMasahiro Yamada help 4215ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 422c94fb639SRandy Dunlap 423215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 424a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 425a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 426a947aa00SNeil Armstrong default ARCH_MESON 427215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 428215f4cc0SJerome Brunet help 429215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 430215f4cc0SJerome Brunet 4314235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4324235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4334235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 434969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4354235ff50SMiodrag Dinic select IRQ_DOMAIN 4364235ff50SMiodrag Dinic help 4374235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4384235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4394235ff50SMiodrag Dinic 440f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4414acd8a4bSSaravana Kannan tristate "QCOM PDC" 442f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 443f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 444f55c73aeSArchana Sathyakumar help 445f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 446f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 447f55c73aeSArchana Sathyakumar 448a6199bb5SShawn Guoconfig QCOM_MPM 449a6199bb5SShawn Guo tristate "QCOM MPM" 450a6199bb5SShawn Guo depends on ARCH_QCOM 451fa4dcc88SYueHaibing depends on MAILBOX 452a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 453a6199bb5SShawn Guo help 454a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 455a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 456a6199bb5SShawn Guo 457d8a5f5f7SGuo Renconfig CSKY_MPINTC 458be1abc5bSGuo Ren bool 459d8a5f5f7SGuo Ren depends on CSKY 460d8a5f5f7SGuo Ren help 461d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 462d8a5f5f7SGuo Ren for C-SKY SMP system. 463656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 464d8a5f5f7SGuo Ren controller's register inside CPU. 465d8a5f5f7SGuo Ren 466edff1b48SGuo Renconfig CSKY_APB_INTC 467edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 468edff1b48SGuo Ren depends on CSKY 469edff1b48SGuo Ren help 470edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 471656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 472edff1b48SGuo Ren the controller's register. 473edff1b48SGuo Ren 4740136afa0SLucas Stachconfig IMX_IRQSTEER 4750136afa0SLucas Stach bool "i.MX IRQSTEER support" 4760136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4770136afa0SLucas Stach default ARCH_MXC 4780136afa0SLucas Stach select IRQ_DOMAIN 4790136afa0SLucas Stach help 4800136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4810136afa0SLucas Stach 4822fbb1396SJoakim Zhangconfig IMX_INTMUX 483a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 484a890caebSGeert Uytterhoeven default y if ARCH_MXC 4852fbb1396SJoakim Zhang select IRQ_DOMAIN 4862fbb1396SJoakim Zhang help 4872fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4882fbb1396SJoakim Zhang 48970afdab9SFrank Liconfig IMX_MU_MSI 49070afdab9SFrank Li tristate "i.MX MU used as MSI controller" 49170afdab9SFrank Li depends on OF && HAS_IOMEM 4926c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 49370afdab9SFrank Li default m if ARCH_MXC 49470afdab9SFrank Li select IRQ_DOMAIN 49570afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 49613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4977b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 49870afdab9SFrank Li help 4996c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5006c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5016c9f7434SGeert Uytterhoeven to make use of this driver. 50270afdab9SFrank Li 50370afdab9SFrank Li If unsure, say N 50470afdab9SFrank Li 5059e543e22SJiaxun Yangconfig LS1X_IRQ 5069e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5079e543e22SJiaxun Yang depends on MACH_LOONGSON32 5089e543e22SJiaxun Yang default y 5099e543e22SJiaxun Yang select IRQ_DOMAIN 5109e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5119e543e22SJiaxun Yang help 5129e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5139e543e22SJiaxun Yang 514cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 515cd844b07SLokesh Vutla bool 516cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 517cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 518cd844b07SLokesh Vutla help 519cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 520cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 521cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 522cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 523cd844b07SLokesh Vutla 5249f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5259f1463b8SLokesh Vutla bool 5269f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5279f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 528f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5299f1463b8SLokesh Vutla help 5309f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5319f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5329f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5339f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5349f1463b8SLokesh Vutla 53504e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 536b8e594faSSuman Anna tristate 537b8e594faSSuman Anna depends on TI_PRUSS 538b8e594faSSuman Anna default TI_PRUSS 53904e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 54004e2d1e0SGrzegorz Jaszczyk help 54104e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 54204e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 54304e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 54404e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 54504e2d1e0SGrzegorz Jaszczyk 5466b7ce892SAnup Patelconfig RISCV_INTC 547d8fb1307SConor Dooley bool 5486b7ce892SAnup Patel depends on RISCV 549832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5506b7ce892SAnup Patel 5512333df5aSAnup Patelconfig RISCV_APLIC 5522333df5aSAnup Patel bool 5532333df5aSAnup Patel depends on RISCV 5542333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 5552333df5aSAnup Patel 556ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 557ca8df97fSAnup Patel bool 558ca8df97fSAnup Patel depends on RISCV_APLIC 559ca8df97fSAnup Patel select GENERIC_MSI_IRQ 560ca8df97fSAnup Patel default RISCV_APLIC 561ca8df97fSAnup Patel 56221a8f8a0SAnup Patelconfig RISCV_IMSIC 56321a8f8a0SAnup Patel bool 56421a8f8a0SAnup Patel depends on RISCV 56521a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 56621a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 56721a8f8a0SAnup Patel select GENERIC_MSI_IRQ 56821a8f8a0SAnup Patel 5695c5a71d0SAnup Patelconfig RISCV_IMSIC_PCI 5705c5a71d0SAnup Patel bool 5715c5a71d0SAnup Patel depends on RISCV_IMSIC 5725c5a71d0SAnup Patel depends on PCI 5735c5a71d0SAnup Patel depends on PCI_MSI 5745c5a71d0SAnup Patel default RISCV_IMSIC 5755c5a71d0SAnup Patel 5768237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 577fdb1742aSConor Dooley bool 5788237f8bcSChristoph Hellwig depends on RISCV 579466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 580de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 58101493855SJonathan Neuschäfer 582e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 583e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 584e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 585e4e53503SChanghuang Liang default ARCH_STARFIVE 586e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 587e4e53503SChanghuang Liang help 588e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 589e4e53503SChanghuang Liang SoC. 590e4e53503SChanghuang Liang 591e4e53503SChanghuang Liang If you don't know what to do here, say Y. 592e4e53503SChanghuang Liang 593b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 594b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 595b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 596b74416dbSHyunki Koo help 597b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 598b74416dbSHyunki Koo in Samsung Exynos chips. 599b74416dbSHyunki Koo 600b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 601b2d3e335SHuacai Chen bool 602b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 603b2d3e335SHuacai Chen select IRQ_DOMAIN 60442a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 60570f7b6c0SHuacai Chen select LOONGSON_HTVEC 6068d5356f9SHuacai Chen select LOONGSON_LIOINTC 6078d5356f9SHuacai Chen select LOONGSON_EIOINTC 6088d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6098d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6108d5356f9SHuacai Chen select LOONGSON_PCH_LPC 611b2d3e335SHuacai Chen help 612b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 613b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 61451712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 615b2d3e335SHuacai Chen 616dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 617dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 618dbb15226SJiaxun Yang depends on MACH_LOONGSON64 619dbb15226SJiaxun Yang default y 620dbb15226SJiaxun Yang select IRQ_DOMAIN 621dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 622dbb15226SJiaxun Yang help 623dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 624dbb15226SJiaxun Yang 625dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 626dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 627dd281e1aSHuacai Chen depends on LOONGARCH 628dd281e1aSHuacai Chen depends on MACH_LOONGSON64 629dd281e1aSHuacai Chen default MACH_LOONGSON64 630dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 631dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 632dd281e1aSHuacai Chen help 633dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 634dd281e1aSHuacai Chen 635a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 636a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 637987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 638a93f1d90SJiaxun Yang default y 639a93f1d90SJiaxun Yang select IRQ_DOMAIN 640a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 641a93f1d90SJiaxun Yang help 642a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 643a93f1d90SJiaxun Yang 644818e915fSJiaxun Yangconfig LOONGSON_HTVEC 645987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 646d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 647818e915fSJiaxun Yang default MACH_LOONGSON64 648818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 649818e915fSJiaxun Yang help 650987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 651818e915fSJiaxun Yang 652ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 653ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 654bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 655ef8c01ebSJiaxun Yang default MACH_LOONGSON64 656ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 657ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 658ef8c01ebSJiaxun Yang help 659ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 660ef8c01ebSJiaxun Yang 661632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 662a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 66302308732SHuacai Chen depends on MACH_LOONGSON64 664632dcc2cSJiaxun Yang depends on PCI 665632dcc2cSJiaxun Yang default MACH_LOONGSON64 666632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 667632dcc2cSJiaxun Yang select PCI_MSI 668632dcc2cSJiaxun Yang help 669632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 670632dcc2cSJiaxun Yang 671ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 672ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 673e7ccba77SJianmin Lv depends on LOONGARCH 674ee73f14eSHuacai Chen depends on MACH_LOONGSON64 675e7ccba77SJianmin Lv default MACH_LOONGSON64 676ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 677ee73f14eSHuacai Chen help 678ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 679ee73f14eSHuacai Chen 680ad4c938cSMark-PK Tsaiconfig MST_IRQ 681ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 68261b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 683ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 684ad4c938cSMark-PK Tsai select IRQ_DOMAIN 685ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 686ad4c938cSMark-PK Tsai help 687ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 688ad4c938cSMark-PK Tsai 689fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 690fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 69194bc9420SMarc Zyngier depends on ARCH_WPCM450 692fead4dd4SJonathan Neuschäfer help 693fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 694fead4dd4SJonathan Neuschäfer 695529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 696529ea368SThomas Bogendoerfer bool 697529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 698529ea368SThomas Bogendoerfer select IRQ_DOMAIN 699529ea368SThomas Bogendoerfer 70076cde263SHector Martinconfig APPLE_AIC 70176cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 70276cde263SHector Martin depends on ARM64 7035b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 704c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 70576cde263SHector Martin help 70676cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 70776cde263SHector Martin such as the M1. 70876cde263SHector Martin 70900fa3461SClaudiu Bezneaconfig MCHP_EIC 71000fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 71100fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 71200fa3461SClaudiu Beznea select IRQ_DOMAIN 71300fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 71400fa3461SClaudiu Beznea help 71500fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 71600fa3461SClaudiu Beznea 717f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 718f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 719f7189d93SQin Jian default SOC_SP7021 720f7189d93SQin Jian help 721f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 722f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 723f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 724f7189d93SQin Jian the primary controller on C-Chip. 725f7189d93SQin Jian 72601493855SJonathan Neuschäferendmenu 727