1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10*dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 293ee80364SArnd Bergmann select PCI_MSI 30853a33ceSSuravee Suthikulpanit 3181243e44SRob Herringconfig GIC_NON_BANKED 3281243e44SRob Herring bool 3381243e44SRob Herring 34021f6537SMarc Zyngierconfig ARM_GIC_V3 35021f6537SMarc Zyngier bool 36443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 37e3825ba1SMarc Zyngier select PARTITION_PERCPU 380e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 39021f6537SMarc Zyngier 4019812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4119812729SMarc Zyngier bool 4213e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4329f41139SMarc Zyngier default ARM_GIC_V3 4429f41139SMarc Zyngier 4529f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4629f41139SMarc Zyngier bool 4729f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 483ee80364SArnd Bergmann depends on PCI 493ee80364SArnd Bergmann depends on PCI_MSI 5029f41139SMarc Zyngier default ARM_GIC_V3_ITS 51292ec080SUwe Kleine-König 527afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 537afe031cSBogdan Purcareata bool 547afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 557afe031cSBogdan Purcareata depends on FSL_MC_BUS 567afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 577afe031cSBogdan Purcareata 5844430ec0SRob Herringconfig ARM_NVIC 5944430ec0SRob Herring bool 602d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6144430ec0SRob Herring select GENERIC_IRQ_CHIP 6244430ec0SRob Herring 6344430ec0SRob Herringconfig ARM_VIC 6444430ec0SRob Herring bool 6544430ec0SRob Herring select IRQ_DOMAIN 6644430ec0SRob Herring 6744430ec0SRob Herringconfig ARM_VIC_NR 6844430ec0SRob Herring int 6944430ec0SRob Herring default 4 if ARCH_S5PV210 7044430ec0SRob Herring default 2 7144430ec0SRob Herring depends on ARM_VIC 7244430ec0SRob Herring help 7344430ec0SRob Herring The maximum number of VICs available in the system, for 7444430ec0SRob Herring power management. 7544430ec0SRob Herring 76fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 77fed6d336SThomas Petazzoni bool 78fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 793ee80364SArnd Bergmann select PCI_MSI if PCI 800e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 81fed6d336SThomas Petazzoni 82e6b78f2cSAntoine Tenartconfig ALPINE_MSI 83e6b78f2cSAntoine Tenart bool 843ee80364SArnd Bergmann depends on PCI 853ee80364SArnd Bergmann select PCI_MSI 86e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 87e6b78f2cSAntoine Tenart 881eb77c3bSTalel Shenharconfig AL_FIC 891eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 909869f37aSJean Delvare depends on OF 911eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 921eb77c3bSTalel Shenhar select IRQ_DOMAIN 931eb77c3bSTalel Shenhar help 941eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 951eb77c3bSTalel Shenhar 96b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 97b1479ebbSBoris BREZILLON bool 98b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 99b1479ebbSBoris BREZILLON select IRQ_DOMAIN 100b1479ebbSBoris BREZILLON select SPARSE_IRQ 101b1479ebbSBoris BREZILLON 102b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 103b1479ebbSBoris BREZILLON bool 104b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 105b1479ebbSBoris BREZILLON select IRQ_DOMAIN 106b1479ebbSBoris BREZILLON select SPARSE_IRQ 107b1479ebbSBoris BREZILLON 1080509cfdeSRalf Baechleconfig I8259 1090509cfdeSRalf Baechle bool 1100509cfdeSRalf Baechle select IRQ_DOMAIN 1110509cfdeSRalf Baechle 112c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 113c7c42ec2SSimon Arlott bool 114c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 115c7c42ec2SSimon Arlott select IRQ_DOMAIN 1160e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 117c7c42ec2SSimon Arlott 1185f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 119c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 120c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 121c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1225f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1235f7f0317SKevin Cernekee select IRQ_DOMAIN 1240e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1255f7f0317SKevin Cernekee 126a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1273ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1283ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1293ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 130a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 131a4fcbb86SKevin Cernekee select IRQ_DOMAIN 132a4fcbb86SKevin Cernekee 1337f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 13451d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 13551d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 13651d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1377f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1387f646e92SFlorian Fainelli select IRQ_DOMAIN 1397f646e92SFlorian Fainelli 1400fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1410fc3d74cSBartosz Golaszewski bool 1420fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1430fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1440fc3d74cSBartosz Golaszewski 145350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 146350d71b9SSebastian Hesselbarth bool 147e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 14854a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 149350d71b9SSebastian Hesselbarth 1506ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1516ee532e2SLinus Walleij bool 1526ee532e2SLinus Walleij select IRQ_DOMAIN 1536ee532e2SLinus Walleij select SPARSE_IRQ 1546ee532e2SLinus Walleij 1559a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1569a7c4abdSMaJun bool 1579a7c4abdSMaJun select ARM_GIC_V3 1589a7c4abdSMaJun select ARM_GIC_V3_ITS 1599a7c4abdSMaJun 160b6ef9161SJames Hoganconfig IMGPDC_IRQ 161b6ef9161SJames Hogan bool 162b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 163b6ef9161SJames Hogan select IRQ_DOMAIN 164b6ef9161SJames Hogan 1655b978c10SLinus Walleijconfig IXP4XX_IRQ 1665b978c10SLinus Walleij bool 1675b978c10SLinus Walleij select IRQ_DOMAIN 1685b978c10SLinus Walleij select SPARSE_IRQ 1695b978c10SLinus Walleij 170da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 171da0abe1aSRichard Fitzgerald tristate 172da0abe1aSRichard Fitzgerald 17367e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 17467e38cf2SRalf Baechle bool 17567e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1760f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 17767e38cf2SRalf Baechle select IRQ_DOMAIN 1780e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 17967e38cf2SRalf Baechle 180afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 181afc98d90SAlexander Shiyan bool 182afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 183afc98d90SAlexander Shiyan select IRQ_DOMAIN 184afc98d90SAlexander Shiyan select SPARSE_IRQ 185afc98d90SAlexander Shiyan default y 186afc98d90SAlexander Shiyan 1879b54470aSStafford Horneconfig OMPIC 1889b54470aSStafford Horne bool 1899b54470aSStafford Horne 1904db8e6d2SStefan Kristianssonconfig OR1K_PIC 1914db8e6d2SStefan Kristiansson bool 1924db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1934db8e6d2SStefan Kristiansson 1948598066cSFelipe Balbiconfig OMAP_IRQCHIP 1958598066cSFelipe Balbi bool 1968598066cSFelipe Balbi select GENERIC_IRQ_CHIP 1978598066cSFelipe Balbi select IRQ_DOMAIN 1988598066cSFelipe Balbi 1999dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2009dbd90f1SSebastian Hesselbarth bool 2019dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2029dbd90f1SSebastian Hesselbarth 203aaa8666aSCristian Birsanconfig PIC32_EVIC 204aaa8666aSCristian Birsan bool 205aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 206aaa8666aSCristian Birsan select IRQ_DOMAIN 207aaa8666aSCristian Birsan 208981b58f6SRich Felkerconfig JCORE_AIC 2093602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2103602ffdeSRich Felker depends on OF 211981b58f6SRich Felker select IRQ_DOMAIN 212981b58f6SRich Felker help 213981b58f6SRich Felker Support for the J-Core integrated AIC. 214981b58f6SRich Felker 215d852e62aSManivannan Sadhasivamconfig RDA_INTC 216d852e62aSManivannan Sadhasivam bool 217d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 218d852e62aSManivannan Sadhasivam 21944358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 22002d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 22144358048SMagnus Damm select IRQ_DOMAIN 22202d7e041SGeert Uytterhoeven help 22302d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 22402d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 22544358048SMagnus Damm 226fbc83b7fSMagnus Dammconfig RENESAS_IRQC 22772d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 22899c221dfSMagnus Damm select GENERIC_IRQ_CHIP 229fbc83b7fSMagnus Damm select IRQ_DOMAIN 23002d7e041SGeert Uytterhoeven help 23102d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23272d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 233fbc83b7fSMagnus Damm 234a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 23502d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 236a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 23702d7e041SGeert Uytterhoeven help 23802d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 23902d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 240a644ccb8SGeert Uytterhoeven 2413fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2423fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2433fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2443fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2453fed0955SLad Prabhakar help 2463fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2473fed0955SLad Prabhakar for external devices. 2483fed0955SLad Prabhakar 24903ac990eSMichael Walleconfig SL28CPLD_INTC 25003ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 25103ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 25203ac990eSMichael Walle select REGMAP_IRQ 25303ac990eSMichael Walle help 25403ac990eSMichael Walle Interrupt controller driver for the board management controller 25503ac990eSMichael Walle found on the Kontron sl28 CPLD. 25603ac990eSMichael Walle 25707088484SLee Jonesconfig ST_IRQCHIP 25807088484SLee Jones bool 25907088484SLee Jones select REGMAP 26007088484SLee Jones select MFD_SYSCON 26107088484SLee Jones help 26207088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 26307088484SLee Jones 264d421fd6dSSamuel Hollandconfig SUN4I_INTC 265d421fd6dSSamuel Holland bool 266d421fd6dSSamuel Holland 267d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 268d421fd6dSSamuel Holland bool 269d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 270d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 271d421fd6dSSamuel Holland 272d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 273d421fd6dSSamuel Holland bool 274d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 275d421fd6dSSamuel Holland 276b06eb017SChristian Ruppertconfig TB10X_IRQC 277b06eb017SChristian Ruppert bool 278b06eb017SChristian Ruppert select IRQ_DOMAIN 279b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 280b06eb017SChristian Ruppert 281d01f8633SDamien Riegelconfig TS4800_IRQ 282d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 283d01f8633SDamien Riegel select IRQ_DOMAIN 2840df337cfSRichard Weinberger depends on HAS_IOMEM 285d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 286d01f8633SDamien Riegel help 287d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 288d01f8633SDamien Riegel 2892389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2902389d501SLinus Walleij bool 2912389d501SLinus Walleij select IRQ_DOMAIN 2922389d501SLinus Walleij 2932389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2942389d501SLinus Walleij int 2952389d501SLinus Walleij default 4 2962389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 29726a8e96aSMax Filippov 29826a8e96aSMax Filippovconfig XTENSA_MX 29926a8e96aSMax Filippov bool 30026a8e96aSMax Filippov select IRQ_DOMAIN 3010e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 30296ca848eSSricharan R 3030547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 304debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 305fd31000dSJamie Iles depends on OF_ADDRESS 3060547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 307debf69cfSRobert Hancock help 308debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 309debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 310debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3110547dc78SZubair Lutfullah Kakakhel 31296ca848eSSricharan Rconfig IRQ_CROSSBAR 31396ca848eSSricharan R bool 31496ca848eSSricharan R help 315f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 31696ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 31796ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 31896ca848eSSricharan R routed to one of the free irqchip interrupt lines. 31989323f8cSGrygorii Strashko 32089323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 32189323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 32289323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 32389323f8cSGrygorii Strashko help 32489323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 32589323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3268a19b8f1SAndrew Bresticker 3278a19b8f1SAndrew Brestickerconfig MIPS_GIC 3288a19b8f1SAndrew Bresticker bool 3298190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3308190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3318a19b8f1SAndrew Bresticker select MIPS_CM 3328a764482SYoshinori Sato 33344e08e70SPaul Burtonconfig INGENIC_IRQ 33444e08e70SPaul Burton bool 33544e08e70SPaul Burton depends on MACH_INGENIC 33644e08e70SPaul Burton default y 33778c10e55SLinus Torvalds 3389536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3399536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3409536eba0SPaul Cercueil default MACH_INGENIC 3419536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3429536eba0SPaul Cercueil select MFD_SYSCON 3438084499bSYueHaibing select GENERIC_IRQ_CHIP 3449536eba0SPaul Cercueil help 3459536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3469536eba0SPaul Cercueil JZ47xx SoCs. 3479536eba0SPaul Cercueil 3489536eba0SPaul Cercueil If unsure, say N. 3499536eba0SPaul Cercueil 350e324c4dcSShenwei Wangconfig IMX_GPCV2 351e324c4dcSShenwei Wang bool 352e324c4dcSShenwei Wang select IRQ_DOMAIN 353e324c4dcSShenwei Wang help 354e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3557e4ac676SOleksij Rempel 3567e4ac676SOleksij Rempelconfig IRQ_MXS 3577e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3587e4ac676SOleksij Rempel select IRQ_DOMAIN 3597e4ac676SOleksij Rempel select STMP_DEVICE 360c27f29bbSThomas Petazzoni 36119d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 36219d99164SAlexandre Belloni bool 36319d99164SAlexandre Belloni select IRQ_DOMAIN 36419d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 36519d99164SAlexandre Belloni 366a68a63cbSThomas Petazzoniconfig MVEBU_GICP 367a68a63cbSThomas Petazzoni bool 368a68a63cbSThomas Petazzoni 369e0de91a9SThomas Petazzoniconfig MVEBU_ICU 370e0de91a9SThomas Petazzoni bool 371e0de91a9SThomas Petazzoni 372c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 373c27f29bbSThomas Petazzoni bool 37413e7accbSThomas Gleixner select GENERIC_MSI_IRQ 3759e2c986cSMarc Zyngier 376a109893bSThomas Petazzoniconfig MVEBU_PIC 377a109893bSThomas Petazzoni bool 378a109893bSThomas Petazzoni 37961ce8d8dSMiquel Raynalconfig MVEBU_SEI 38061ce8d8dSMiquel Raynal bool 38161ce8d8dSMiquel Raynal 3820dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3830dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3840dcd9f87SRasmus Villemoes select MFD_SYSCON 3850dcd9f87SRasmus Villemoes 386b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 387b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3889c1a7bfcSLukas Bulwahn depends on PCI_MSI 389b8f3ebe6SMinghuan Lian 3909e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3919e2c986cSMarc Zyngier bool 3920efacbbaSLinus Torvalds 393e0720416SAlexandre TORGUEconfig STM32_EXTI 394e0720416SAlexandre TORGUE bool 395e0720416SAlexandre TORGUE select IRQ_DOMAIN 3960e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 397f20cc9b0SAgustin Vega-Frias 398f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 399f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 400f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 401f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 402f20cc9b0SAgustin Vega-Frias help 403f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 404f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4055ed34d3aSMasahiro Yamada 4065ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4075ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4085ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4095ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4105ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4115ed34d3aSMasahiro Yamada help 4125ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 413c94fb639SRandy Dunlap 414215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 415a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 416a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 417a947aa00SNeil Armstrong default ARCH_MESON 418215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 419215f4cc0SJerome Brunet help 420215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 421215f4cc0SJerome Brunet 4224235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4234235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4244235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 425969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4264235ff50SMiodrag Dinic select IRQ_DOMAIN 4274235ff50SMiodrag Dinic help 4284235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4294235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4304235ff50SMiodrag Dinic 431f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4324acd8a4bSSaravana Kannan tristate "QCOM PDC" 433f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 434f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 435f55c73aeSArchana Sathyakumar help 436f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 437f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 438f55c73aeSArchana Sathyakumar 439a6199bb5SShawn Guoconfig QCOM_MPM 440a6199bb5SShawn Guo tristate "QCOM MPM" 441a6199bb5SShawn Guo depends on ARCH_QCOM 442fa4dcc88SYueHaibing depends on MAILBOX 443a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 444a6199bb5SShawn Guo help 445a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 446a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 447a6199bb5SShawn Guo 448d8a5f5f7SGuo Renconfig CSKY_MPINTC 449be1abc5bSGuo Ren bool 450d8a5f5f7SGuo Ren depends on CSKY 451d8a5f5f7SGuo Ren help 452d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 453d8a5f5f7SGuo Ren for C-SKY SMP system. 454656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 455d8a5f5f7SGuo Ren controller's register inside CPU. 456d8a5f5f7SGuo Ren 457edff1b48SGuo Renconfig CSKY_APB_INTC 458edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 459edff1b48SGuo Ren depends on CSKY 460edff1b48SGuo Ren help 461edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 462656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 463edff1b48SGuo Ren the controller's register. 464edff1b48SGuo Ren 4650136afa0SLucas Stachconfig IMX_IRQSTEER 4660136afa0SLucas Stach bool "i.MX IRQSTEER support" 4670136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4680136afa0SLucas Stach default ARCH_MXC 4690136afa0SLucas Stach select IRQ_DOMAIN 4700136afa0SLucas Stach help 4710136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4720136afa0SLucas Stach 4732fbb1396SJoakim Zhangconfig IMX_INTMUX 474a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 475a890caebSGeert Uytterhoeven default y if ARCH_MXC 4762fbb1396SJoakim Zhang select IRQ_DOMAIN 4772fbb1396SJoakim Zhang help 4782fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4792fbb1396SJoakim Zhang 48070afdab9SFrank Liconfig IMX_MU_MSI 48170afdab9SFrank Li tristate "i.MX MU used as MSI controller" 48270afdab9SFrank Li depends on OF && HAS_IOMEM 4836c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 48470afdab9SFrank Li default m if ARCH_MXC 48570afdab9SFrank Li select IRQ_DOMAIN 48670afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 48713e7accbSThomas Gleixner select GENERIC_MSI_IRQ 48870afdab9SFrank Li help 4896c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 4906c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 4916c9f7434SGeert Uytterhoeven to make use of this driver. 49270afdab9SFrank Li 49370afdab9SFrank Li If unsure, say N 49470afdab9SFrank Li 4959e543e22SJiaxun Yangconfig LS1X_IRQ 4969e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 4979e543e22SJiaxun Yang depends on MACH_LOONGSON32 4989e543e22SJiaxun Yang default y 4999e543e22SJiaxun Yang select IRQ_DOMAIN 5009e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5019e543e22SJiaxun Yang help 5029e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5039e543e22SJiaxun Yang 504cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 505cd844b07SLokesh Vutla bool 506cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 507cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 508cd844b07SLokesh Vutla help 509cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 510cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 511cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 512cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 513cd844b07SLokesh Vutla 5149f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5159f1463b8SLokesh Vutla bool 5169f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5179f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 518f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5199f1463b8SLokesh Vutla help 5209f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5219f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5229f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5239f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5249f1463b8SLokesh Vutla 52504e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 526b8e594faSSuman Anna tristate 527b8e594faSSuman Anna depends on TI_PRUSS 528b8e594faSSuman Anna default TI_PRUSS 52904e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 53004e2d1e0SGrzegorz Jaszczyk help 53104e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 53204e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 53304e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 53404e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 53504e2d1e0SGrzegorz Jaszczyk 5366b7ce892SAnup Patelconfig RISCV_INTC 537d8fb1307SConor Dooley bool 5386b7ce892SAnup Patel depends on RISCV 5396b7ce892SAnup Patel 5408237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 541fdb1742aSConor Dooley bool 5428237f8bcSChristoph Hellwig depends on RISCV 543466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 544de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 54501493855SJonathan Neuschäfer 546b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 547b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 548b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 549b74416dbSHyunki Koo help 550b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 551b74416dbSHyunki Koo in Samsung Exynos chips. 552b74416dbSHyunki Koo 553b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 554b2d3e335SHuacai Chen bool 555b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 556b2d3e335SHuacai Chen select IRQ_DOMAIN 557b2d3e335SHuacai Chen select GENERIC_IRQ_EFFECTIVE_AFF_MASK 55870f7b6c0SHuacai Chen select LOONGSON_HTVEC 5598d5356f9SHuacai Chen select LOONGSON_LIOINTC 5608d5356f9SHuacai Chen select LOONGSON_EIOINTC 5618d5356f9SHuacai Chen select LOONGSON_PCH_PIC 5628d5356f9SHuacai Chen select LOONGSON_PCH_MSI 5638d5356f9SHuacai Chen select LOONGSON_PCH_LPC 564b2d3e335SHuacai Chen help 565b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 566b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 567b2d3e335SHuacai Chen Documentation/loongarch/irq-chip-model.rst. 568b2d3e335SHuacai Chen 569dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 570dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 571dbb15226SJiaxun Yang depends on MACH_LOONGSON64 572dbb15226SJiaxun Yang default y 573dbb15226SJiaxun Yang select IRQ_DOMAIN 574dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 575dbb15226SJiaxun Yang help 576dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 577dbb15226SJiaxun Yang 578dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 579dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 580dd281e1aSHuacai Chen depends on LOONGARCH 581dd281e1aSHuacai Chen depends on MACH_LOONGSON64 582dd281e1aSHuacai Chen default MACH_LOONGSON64 583dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 584dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 585dd281e1aSHuacai Chen help 586dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 587dd281e1aSHuacai Chen 588a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 589a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 590987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 591a93f1d90SJiaxun Yang default y 592a93f1d90SJiaxun Yang select IRQ_DOMAIN 593a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 594a93f1d90SJiaxun Yang help 595a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 596a93f1d90SJiaxun Yang 597818e915fSJiaxun Yangconfig LOONGSON_HTVEC 598987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 599d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 600818e915fSJiaxun Yang default MACH_LOONGSON64 601818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 602818e915fSJiaxun Yang help 603987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 604818e915fSJiaxun Yang 605ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 606ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 607bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 608ef8c01ebSJiaxun Yang default MACH_LOONGSON64 609ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 610ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 611ef8c01ebSJiaxun Yang help 612ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 613ef8c01ebSJiaxun Yang 614632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 615a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 61602308732SHuacai Chen depends on MACH_LOONGSON64 617632dcc2cSJiaxun Yang depends on PCI 618632dcc2cSJiaxun Yang default MACH_LOONGSON64 619632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 620632dcc2cSJiaxun Yang select PCI_MSI 621632dcc2cSJiaxun Yang help 622632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 623632dcc2cSJiaxun Yang 624ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 625ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 626e7ccba77SJianmin Lv depends on LOONGARCH 627ee73f14eSHuacai Chen depends on MACH_LOONGSON64 628e7ccba77SJianmin Lv default MACH_LOONGSON64 629ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 630ee73f14eSHuacai Chen help 631ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 632ee73f14eSHuacai Chen 633ad4c938cSMark-PK Tsaiconfig MST_IRQ 634ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 63561b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 636ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 637ad4c938cSMark-PK Tsai select IRQ_DOMAIN 638ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 639ad4c938cSMark-PK Tsai help 640ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 641ad4c938cSMark-PK Tsai 642fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 643fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 64494bc9420SMarc Zyngier depends on ARCH_WPCM450 645fead4dd4SJonathan Neuschäfer help 646fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 647fead4dd4SJonathan Neuschäfer 648529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 649529ea368SThomas Bogendoerfer bool 650529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 651529ea368SThomas Bogendoerfer select IRQ_DOMAIN 652529ea368SThomas Bogendoerfer 65376cde263SHector Martinconfig APPLE_AIC 65476cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 65576cde263SHector Martin depends on ARM64 6565b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 657c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 65876cde263SHector Martin help 65976cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 66076cde263SHector Martin such as the M1. 66176cde263SHector Martin 66200fa3461SClaudiu Bezneaconfig MCHP_EIC 66300fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 66400fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 66500fa3461SClaudiu Beznea select IRQ_DOMAIN 66600fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 66700fa3461SClaudiu Beznea help 66800fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 66900fa3461SClaudiu Beznea 670f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 671f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 672f7189d93SQin Jian default SOC_SP7021 673f7189d93SQin Jian help 674f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 675f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 676f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 677f7189d93SQin Jian the primary controller on C-Chip. 678f7189d93SQin Jian 67901493855SJonathan Neuschäferendmenu 680