1c94fb639SRandy Dunlapmenu "IRQ chip support" 2c94fb639SRandy Dunlap 3f6e916b8SThomas Petazzoniconfig IRQCHIP 4f6e916b8SThomas Petazzoni def_bool y 5f6e916b8SThomas Petazzoni depends on OF_IRQ 6f6e916b8SThomas Petazzoni 781243e44SRob Herringconfig ARM_GIC 881243e44SRob Herring bool 99a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 104f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 110c9e4982SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1281243e44SRob Herring 139c8edddfSJon Hunterconfig ARM_GIC_PM 149c8edddfSJon Hunter bool 159c8edddfSJon Hunter depends on PM 169c8edddfSJon Hunter select ARM_GIC 179c8edddfSJon Hunter select PM_CLK 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 21a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 22a27d21e0SLinus Walleij default 1 23a27d21e0SLinus Walleij 24853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 25853a33ceSSuravee Suthikulpanit bool 263ee80364SArnd Bergmann depends on PCI 273ee80364SArnd Bergmann select ARM_GIC 283ee80364SArnd Bergmann select PCI_MSI 29853a33ceSSuravee Suthikulpanit 3081243e44SRob Herringconfig GIC_NON_BANKED 3181243e44SRob Herring bool 3281243e44SRob Herring 33021f6537SMarc Zyngierconfig ARM_GIC_V3 34021f6537SMarc Zyngier bool 354f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 36443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 37e3825ba1SMarc Zyngier select PARTITION_PERCPU 38956ae91aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 39021f6537SMarc Zyngier 4019812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4119812729SMarc Zyngier bool 4229f41139SMarc Zyngier select GENERIC_MSI_IRQ_DOMAIN 4329f41139SMarc Zyngier default ARM_GIC_V3 4429f41139SMarc Zyngier 4529f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4629f41139SMarc Zyngier bool 4729f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 483ee80364SArnd Bergmann depends on PCI 493ee80364SArnd Bergmann depends on PCI_MSI 5029f41139SMarc Zyngier default ARM_GIC_V3_ITS 51292ec080SUwe Kleine-König 527afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 537afe031cSBogdan Purcareata bool 547afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 557afe031cSBogdan Purcareata depends on FSL_MC_BUS 567afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 577afe031cSBogdan Purcareata 5844430ec0SRob Herringconfig ARM_NVIC 5944430ec0SRob Herring bool 602d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6144430ec0SRob Herring select GENERIC_IRQ_CHIP 6244430ec0SRob Herring 6344430ec0SRob Herringconfig ARM_VIC 6444430ec0SRob Herring bool 6544430ec0SRob Herring select IRQ_DOMAIN 664f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 6744430ec0SRob Herring 6844430ec0SRob Herringconfig ARM_VIC_NR 6944430ec0SRob Herring int 7044430ec0SRob Herring default 4 if ARCH_S5PV210 7144430ec0SRob Herring default 2 7244430ec0SRob Herring depends on ARM_VIC 7344430ec0SRob Herring help 7444430ec0SRob Herring The maximum number of VICs available in the system, for 7544430ec0SRob Herring power management. 7644430ec0SRob Herring 77fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 78fed6d336SThomas Petazzoni bool 79fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 803ee80364SArnd Bergmann select PCI_MSI if PCI 81e31793a3SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 82fed6d336SThomas Petazzoni 83e6b78f2cSAntoine Tenartconfig ALPINE_MSI 84e6b78f2cSAntoine Tenart bool 853ee80364SArnd Bergmann depends on PCI 863ee80364SArnd Bergmann select PCI_MSI 87e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 88e6b78f2cSAntoine Tenart 89b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 90b1479ebbSBoris BREZILLON bool 91b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 92b1479ebbSBoris BREZILLON select IRQ_DOMAIN 934f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 94b1479ebbSBoris BREZILLON select SPARSE_IRQ 95b1479ebbSBoris BREZILLON 96b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 97b1479ebbSBoris BREZILLON bool 98b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 99b1479ebbSBoris BREZILLON select IRQ_DOMAIN 1004f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 101b1479ebbSBoris BREZILLON select SPARSE_IRQ 102b1479ebbSBoris BREZILLON 1030509cfdeSRalf Baechleconfig I8259 1040509cfdeSRalf Baechle bool 1050509cfdeSRalf Baechle select IRQ_DOMAIN 1060509cfdeSRalf Baechle 107c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 108c7c42ec2SSimon Arlott bool 109c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 110c7c42ec2SSimon Arlott select IRQ_DOMAIN 111d0ed5e8eSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 112c7c42ec2SSimon Arlott 1135f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 1145f7f0317SKevin Cernekee bool 1155f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1165f7f0317SKevin Cernekee select IRQ_DOMAIN 117b8d9884aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1185f7f0317SKevin Cernekee 119a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 120a4fcbb86SKevin Cernekee bool 121a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 122a4fcbb86SKevin Cernekee select IRQ_DOMAIN 123a4fcbb86SKevin Cernekee 1247f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 1257f646e92SFlorian Fainelli bool 1267f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1277f646e92SFlorian Fainelli select IRQ_DOMAIN 1287f646e92SFlorian Fainelli 1290145beedSBartosz Golaszewskiconfig DAVINCI_AINTC 1300145beedSBartosz Golaszewski bool 1310145beedSBartosz Golaszewski select GENERIC_IRQ_CHIP 1320145beedSBartosz Golaszewski select IRQ_DOMAIN 1330145beedSBartosz Golaszewski 1340fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1350fc3d74cSBartosz Golaszewski bool 1360fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1370fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1380fc3d74cSBartosz Golaszewski 139350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 140350d71b9SSebastian Hesselbarth bool 141e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 142350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 143350d71b9SSebastian Hesselbarth 1446ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1456ee532e2SLinus Walleij bool 1466ee532e2SLinus Walleij select IRQ_DOMAIN 1474f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1486ee532e2SLinus Walleij select SPARSE_IRQ 1496ee532e2SLinus Walleij 1509a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1519a7c4abdSMaJun bool 1529a7c4abdSMaJun select ARM_GIC_V3 1539a7c4abdSMaJun select ARM_GIC_V3_ITS 1549a7c4abdSMaJun 155b6ef9161SJames Hoganconfig IMGPDC_IRQ 156b6ef9161SJames Hogan bool 157b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 158b6ef9161SJames Hogan select IRQ_DOMAIN 159b6ef9161SJames Hogan 160da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 161da0abe1aSRichard Fitzgerald tristate 162da0abe1aSRichard Fitzgerald 16367e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 16467e38cf2SRalf Baechle bool 16567e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1663838a547SPaul Burton select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 16767e38cf2SRalf Baechle select IRQ_DOMAIN 1683838a547SPaul Burton select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 16918416e45SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 17067e38cf2SRalf Baechle 171afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 172afc98d90SAlexander Shiyan bool 173afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 174afc98d90SAlexander Shiyan select IRQ_DOMAIN 1754f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 176afc98d90SAlexander Shiyan select SPARSE_IRQ 177afc98d90SAlexander Shiyan default y 178afc98d90SAlexander Shiyan 1799b54470aSStafford Horneconfig OMPIC 1809b54470aSStafford Horne bool 1819b54470aSStafford Horne 1824db8e6d2SStefan Kristianssonconfig OR1K_PIC 1834db8e6d2SStefan Kristiansson bool 1844db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1854db8e6d2SStefan Kristiansson 1868598066cSFelipe Balbiconfig OMAP_IRQCHIP 1878598066cSFelipe Balbi bool 1888598066cSFelipe Balbi select GENERIC_IRQ_CHIP 1898598066cSFelipe Balbi select IRQ_DOMAIN 1908598066cSFelipe Balbi 1919dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 1929dbd90f1SSebastian Hesselbarth bool 1939dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 1944f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1959dbd90f1SSebastian Hesselbarth 196aaa8666aSCristian Birsanconfig PIC32_EVIC 197aaa8666aSCristian Birsan bool 198aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 199aaa8666aSCristian Birsan select IRQ_DOMAIN 200aaa8666aSCristian Birsan 201981b58f6SRich Felkerconfig JCORE_AIC 2023602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2033602ffdeSRich Felker depends on OF 204981b58f6SRich Felker select IRQ_DOMAIN 205981b58f6SRich Felker help 206981b58f6SRich Felker Support for the J-Core integrated AIC. 207981b58f6SRich Felker 208d852e62aSManivannan Sadhasivamconfig RDA_INTC 209d852e62aSManivannan Sadhasivam bool 210d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 211d852e62aSManivannan Sadhasivam 21244358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 21344358048SMagnus Damm bool 21444358048SMagnus Damm select IRQ_DOMAIN 21544358048SMagnus Damm 216fbc83b7fSMagnus Dammconfig RENESAS_IRQC 217fbc83b7fSMagnus Damm bool 21899c221dfSMagnus Damm select GENERIC_IRQ_CHIP 219fbc83b7fSMagnus Damm select IRQ_DOMAIN 220fbc83b7fSMagnus Damm 22107088484SLee Jonesconfig ST_IRQCHIP 22207088484SLee Jones bool 22307088484SLee Jones select REGMAP 22407088484SLee Jones select MFD_SYSCON 22507088484SLee Jones help 22607088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 22707088484SLee Jones 2284bba6689SMans Rullgardconfig TANGO_IRQ 2294bba6689SMans Rullgard bool 2304bba6689SMans Rullgard select IRQ_DOMAIN 2314bba6689SMans Rullgard select GENERIC_IRQ_CHIP 2324bba6689SMans Rullgard 233b06eb017SChristian Ruppertconfig TB10X_IRQC 234b06eb017SChristian Ruppert bool 235b06eb017SChristian Ruppert select IRQ_DOMAIN 236b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 237b06eb017SChristian Ruppert 238d01f8633SDamien Riegelconfig TS4800_IRQ 239d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 240d01f8633SDamien Riegel select IRQ_DOMAIN 2410df337cfSRichard Weinberger depends on HAS_IOMEM 242d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 243d01f8633SDamien Riegel help 244d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 245d01f8633SDamien Riegel 2462389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2472389d501SLinus Walleij bool 2482389d501SLinus Walleij select IRQ_DOMAIN 2492389d501SLinus Walleij 2502389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2512389d501SLinus Walleij int 2522389d501SLinus Walleij default 4 2532389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 25426a8e96aSMax Filippov 25526a8e96aSMax Filippovconfig XTENSA_MX 25626a8e96aSMax Filippov bool 25726a8e96aSMax Filippov select IRQ_DOMAIN 25850091212SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 25996ca848eSSricharan R 2600547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 2610547dc78SZubair Lutfullah Kakakhel bool 2620547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 2630547dc78SZubair Lutfullah Kakakhel 26496ca848eSSricharan Rconfig IRQ_CROSSBAR 26596ca848eSSricharan R bool 26696ca848eSSricharan R help 267f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 26896ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 26996ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 27096ca848eSSricharan R routed to one of the free irqchip interrupt lines. 27189323f8cSGrygorii Strashko 27289323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 27389323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 27489323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 27589323f8cSGrygorii Strashko help 27689323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 27789323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 2788a19b8f1SAndrew Bresticker 2798a19b8f1SAndrew Brestickerconfig MIPS_GIC 2808a19b8f1SAndrew Bresticker bool 281bb11cff3SQais Yousef select GENERIC_IRQ_IPI 2822af70a96SQais Yousef select IRQ_DOMAIN_HIERARCHY 2838a19b8f1SAndrew Bresticker select MIPS_CM 2848a764482SYoshinori Sato 28544e08e70SPaul Burtonconfig INGENIC_IRQ 28644e08e70SPaul Burton bool 28744e08e70SPaul Burton depends on MACH_INGENIC 28844e08e70SPaul Burton default y 28978c10e55SLinus Torvalds 2908a764482SYoshinori Satoconfig RENESAS_H8300H_INTC 2918a764482SYoshinori Sato bool 2928a764482SYoshinori Sato select IRQ_DOMAIN 2938a764482SYoshinori Sato 2948a764482SYoshinori Satoconfig RENESAS_H8S_INTC 2958a764482SYoshinori Sato bool 2968a764482SYoshinori Sato select IRQ_DOMAIN 297e324c4dcSShenwei Wang 298e324c4dcSShenwei Wangconfig IMX_GPCV2 299e324c4dcSShenwei Wang bool 300e324c4dcSShenwei Wang select IRQ_DOMAIN 301e324c4dcSShenwei Wang help 302e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3037e4ac676SOleksij Rempel 3047e4ac676SOleksij Rempelconfig IRQ_MXS 3057e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3067e4ac676SOleksij Rempel select IRQ_DOMAIN 3077e4ac676SOleksij Rempel select STMP_DEVICE 308c27f29bbSThomas Petazzoni 30919d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 31019d99164SAlexandre Belloni bool 31119d99164SAlexandre Belloni select IRQ_DOMAIN 31219d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 31319d99164SAlexandre Belloni 314a68a63cbSThomas Petazzoniconfig MVEBU_GICP 315a68a63cbSThomas Petazzoni bool 316a68a63cbSThomas Petazzoni 317e0de91a9SThomas Petazzoniconfig MVEBU_ICU 318e0de91a9SThomas Petazzoni bool 319e0de91a9SThomas Petazzoni 320c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 321c27f29bbSThomas Petazzoni bool 322fa23b9d1SArnd Bergmann select GENERIC_MSI_IRQ_DOMAIN 3239e2c986cSMarc Zyngier 324a109893bSThomas Petazzoniconfig MVEBU_PIC 325a109893bSThomas Petazzoni bool 326a109893bSThomas Petazzoni 32761ce8d8dSMiquel Raynalconfig MVEBU_SEI 32861ce8d8dSMiquel Raynal bool 32961ce8d8dSMiquel Raynal 330b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 331b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 332b8f3ebe6SMinghuan Lian depends on PCI && PCI_MSI 333b8f3ebe6SMinghuan Lian 3349e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3359e2c986cSMarc Zyngier bool 3360efacbbaSLinus Torvalds 33744df427cSNoam Camusconfig EZNPS_GIC 33844df427cSNoam Camus bool "NPS400 Global Interrupt Manager (GIM)" 339ffd565e3SArnd Bergmann depends on ARC || (COMPILE_TEST && !64BIT) 34044df427cSNoam Camus select IRQ_DOMAIN 34144df427cSNoam Camus help 34244df427cSNoam Camus Support the EZchip NPS400 global interrupt controller 343e0720416SAlexandre TORGUE 344e0720416SAlexandre TORGUEconfig STM32_EXTI 345e0720416SAlexandre TORGUE bool 346e0720416SAlexandre TORGUE select IRQ_DOMAIN 3470e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 348f20cc9b0SAgustin Vega-Frias 349f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 350f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 351f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 352f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 353f20cc9b0SAgustin Vega-Frias help 354f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 355f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 3565ed34d3aSMasahiro Yamada 3575ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 3585ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 3595ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 3605ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 3615ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 3625ed34d3aSMasahiro Yamada help 3635ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 364c94fb639SRandy Dunlap 365215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 366215f4cc0SJerome Brunet bool "Meson GPIO Interrupt Multiplexer" 367d9ee91c1SThomas Gleixner depends on ARCH_MESON 368215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 369215f4cc0SJerome Brunet help 370215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 371215f4cc0SJerome Brunet 3724235ff50SMiodrag Dinicconfig GOLDFISH_PIC 3734235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 3744235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 3754235ff50SMiodrag Dinic select IRQ_DOMAIN 3764235ff50SMiodrag Dinic help 3774235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 3784235ff50SMiodrag Dinic for Goldfish based virtual platforms. 3794235ff50SMiodrag Dinic 380f55c73aeSArchana Sathyakumarconfig QCOM_PDC 381f55c73aeSArchana Sathyakumar bool "QCOM PDC" 382f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 383f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 384f55c73aeSArchana Sathyakumar help 385f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 386f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 387f55c73aeSArchana Sathyakumar 388d8a5f5f7SGuo Renconfig CSKY_MPINTC 389d8a5f5f7SGuo Ren bool "C-SKY Multi Processor Interrupt Controller" 390d8a5f5f7SGuo Ren depends on CSKY 391d8a5f5f7SGuo Ren help 392d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 393d8a5f5f7SGuo Ren for C-SKY SMP system. 394d8a5f5f7SGuo Ren In fact it's not mmio map in hw and it use ld/st to visit the 395d8a5f5f7SGuo Ren controller's register inside CPU. 396d8a5f5f7SGuo Ren 397edff1b48SGuo Renconfig CSKY_APB_INTC 398edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 399edff1b48SGuo Ren depends on CSKY 400edff1b48SGuo Ren help 401edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 402edff1b48SGuo Ren by C-SKY single core SOC system. It use mmio map apb-bus to visit 403edff1b48SGuo Ren the controller's register. 404edff1b48SGuo Ren 4050136afa0SLucas Stachconfig IMX_IRQSTEER 4060136afa0SLucas Stach bool "i.MX IRQSTEER support" 4070136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4080136afa0SLucas Stach default ARCH_MXC 4090136afa0SLucas Stach select IRQ_DOMAIN 4100136afa0SLucas Stach help 4110136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4120136afa0SLucas Stach 4139e543e22SJiaxun Yangconfig LS1X_IRQ 4149e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 4159e543e22SJiaxun Yang depends on MACH_LOONGSON32 4169e543e22SJiaxun Yang default y 4179e543e22SJiaxun Yang select IRQ_DOMAIN 4189e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 4199e543e22SJiaxun Yang help 4209e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 4219e543e22SJiaxun Yang 422*cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 423*cd844b07SLokesh Vutla bool 424*cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 425*cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 426*cd844b07SLokesh Vutla help 427*cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 428*cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 429*cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 430*cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 431*cd844b07SLokesh Vutla 432c94fb639SRandy Dunlapendmenu 4338237f8bcSChristoph Hellwig 4348237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 4358237f8bcSChristoph Hellwig bool "SiFive Platform-Level Interrupt Controller" 4368237f8bcSChristoph Hellwig depends on RISCV 4378237f8bcSChristoph Hellwig help 4388237f8bcSChristoph Hellwig This enables support for the PLIC chip found in SiFive (and 4398237f8bcSChristoph Hellwig potentially other) RISC-V systems. The PLIC controls devices 4408237f8bcSChristoph Hellwig interrupts and connects them to each core's local interrupt 4418237f8bcSChristoph Hellwig controller. Aside from timer and software interrupts, all other 4428237f8bcSChristoph Hellwig interrupt sources are subordinate to the PLIC. 4438237f8bcSChristoph Hellwig 4448237f8bcSChristoph Hellwig If you don't know what to do here, say Y. 445