1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 3196093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 4296093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 44*b4ead12dSLorenzo Pieralisiconfig ARM_GIC_ITS_PARENT 45*b4ead12dSLorenzo Pieralisi bool 46*b4ead12dSLorenzo Pieralisi 4719812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4819812729SMarc Zyngier bool 4913e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5048f71d56SThomas Gleixner select IRQ_MSI_LIB 51*b4ead12dSLorenzo Pieralisi select ARM_GIC_ITS_PARENT 5229f41139SMarc Zyngier default ARM_GIC_V3 5396093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5429f41139SMarc Zyngier 557afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 567afe031cSBogdan Purcareata bool 577afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata depends on FSL_MC_BUS 597afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 607afe031cSBogdan Purcareata 617ec80fb3SLorenzo Pieralisiconfig ARM_GIC_V5 627ec80fb3SLorenzo Pieralisi bool 637ec80fb3SLorenzo Pieralisi select IRQ_DOMAIN_HIERARCHY 647ec80fb3SLorenzo Pieralisi select GENERIC_IRQ_EFFECTIVE_AFF_MASK 657ec80fb3SLorenzo Pieralisi 66292ec080SUwe Kleine-Königconfig ARM_NVIC 67292ec080SUwe Kleine-König bool 682d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 69292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 70292ec080SUwe Kleine-König 7144430ec0SRob Herringconfig ARM_VIC 7244430ec0SRob Herring bool 7344430ec0SRob Herring select IRQ_DOMAIN 7444430ec0SRob Herring 7544430ec0SRob Herringconfig ARM_VIC_NR 7644430ec0SRob Herring int 7744430ec0SRob Herring default 4 if ARCH_S5PV210 7844430ec0SRob Herring default 2 7944430ec0SRob Herring depends on ARM_VIC 8044430ec0SRob Herring help 8144430ec0SRob Herring The maximum number of VICs available in the system, for 8244430ec0SRob Herring power management. 8344430ec0SRob Herring 8472e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 8572e257c6SThomas Gleixner bool 8672e257c6SThomas Gleixner 87fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 88fed6d336SThomas Petazzoni bool 89fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 903ee80364SArnd Bergmann select PCI_MSI if PCI 910e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 92fed6d336SThomas Petazzoni 93e6b78f2cSAntoine Tenartconfig ALPINE_MSI 94e6b78f2cSAntoine Tenart bool 953ee80364SArnd Bergmann depends on PCI 963ee80364SArnd Bergmann select PCI_MSI 97e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 98e6b78f2cSAntoine Tenart 991eb77c3bSTalel Shenharconfig AL_FIC 1001eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 1019869f37aSJean Delvare depends on OF 10235e0cd77SBaoquan He depends on HAS_IOMEM 1031eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 1041eb77c3bSTalel Shenhar select IRQ_DOMAIN 1051eb77c3bSTalel Shenhar help 1061eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1071eb77c3bSTalel Shenhar 108b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 109b1479ebbSBoris BREZILLON bool 110b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 111b1479ebbSBoris BREZILLON select IRQ_DOMAIN 112b1479ebbSBoris BREZILLON select SPARSE_IRQ 113b1479ebbSBoris BREZILLON 114b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 115b1479ebbSBoris BREZILLON bool 116b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 117b1479ebbSBoris BREZILLON select IRQ_DOMAIN 118b1479ebbSBoris BREZILLON select SPARSE_IRQ 119b1479ebbSBoris BREZILLON 1200509cfdeSRalf Baechleconfig I8259 1210509cfdeSRalf Baechle bool 1220509cfdeSRalf Baechle select IRQ_DOMAIN 1230509cfdeSRalf Baechle 12432c6c054SStanimir Varbanovconfig BCM2712_MIP 12532c6c054SStanimir Varbanov tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 1269b3ae50cSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 1279b3ae50cSPeter Robinson default m if ARCH_BRCMSTB || ARCH_BCM2835 12832c6c054SStanimir Varbanov depends on ARM_GIC 12932c6c054SStanimir Varbanov select GENERIC_IRQ_CHIP 13032c6c054SStanimir Varbanov select IRQ_DOMAIN_HIERARCHY 13132c6c054SStanimir Varbanov select GENERIC_MSI_IRQ 13232c6c054SStanimir Varbanov select IRQ_MSI_LIB 13332c6c054SStanimir Varbanov help 13432c6c054SStanimir Varbanov Enable support for the Broadcom BCM2712 MSI-X target peripheral 13532c6c054SStanimir Varbanov (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 13632c6c054SStanimir Varbanov Raspberry Pi 5. 13732c6c054SStanimir Varbanov 13832c6c054SStanimir Varbanov If unsure say n. 13932c6c054SStanimir Varbanov 140c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 141c7c42ec2SSimon Arlott bool 142c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 143c7c42ec2SSimon Arlott select IRQ_DOMAIN 1440e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 145c7c42ec2SSimon Arlott 1465f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 147c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 148c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 149c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1505f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1515f7f0317SKevin Cernekee select IRQ_DOMAIN 1520e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1535f7f0317SKevin Cernekee 154a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1553ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1563ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1573ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 158a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 159a4fcbb86SKevin Cernekee select IRQ_DOMAIN 160a4fcbb86SKevin Cernekee 1617f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 16251d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 16351d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 16451d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1657f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1667f646e92SFlorian Fainelli select IRQ_DOMAIN 1677f646e92SFlorian Fainelli 1680fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1690fc3d74cSBartosz Golaszewski bool 1700fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1710fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1720fc3d74cSBartosz Golaszewski 173350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 174be5e5f3aSThomas Gleixner bool 175e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 17654a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 177350d71b9SSebastian Hesselbarth 1781902a59cSCaleb James DeLisleconfig ECONET_EN751221_INTC 1791902a59cSCaleb James DeLisle bool 1801902a59cSCaleb James DeLisle select GENERIC_IRQ_CHIP 1811902a59cSCaleb James DeLisle select IRQ_DOMAIN 1821902a59cSCaleb James DeLisle 1836ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1846ee532e2SLinus Walleij bool 1856ee532e2SLinus Walleij select IRQ_DOMAIN 1866ee532e2SLinus Walleij select SPARSE_IRQ 1876ee532e2SLinus Walleij 1889a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1899a7c4abdSMaJun bool 1909a7c4abdSMaJun select ARM_GIC_V3 1919a7c4abdSMaJun select ARM_GIC_V3_ITS 1929a7c4abdSMaJun 193b6ef9161SJames Hoganconfig IMGPDC_IRQ 194b6ef9161SJames Hogan bool 195b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 196b6ef9161SJames Hogan select IRQ_DOMAIN 197b6ef9161SJames Hogan 1985b978c10SLinus Walleijconfig IXP4XX_IRQ 1995b978c10SLinus Walleij bool 2005b978c10SLinus Walleij select IRQ_DOMAIN 2015b978c10SLinus Walleij select SPARSE_IRQ 2025b978c10SLinus Walleij 2033e3a7b35SHerve Codinaconfig LAN966X_OIC 2043e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 205e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 2063e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 2073e3a7b35SHerve Codina select IRQ_DOMAIN 2083e3a7b35SHerve Codina help 2093e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 2103e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 2113e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 2123e3a7b35SHerve Codina 2133e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 2143e3a7b35SHerve Codina will be called irq-lan966x-oic. 2153e3a7b35SHerve Codina 216da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 217da0abe1aSRichard Fitzgerald tristate 218da0abe1aSRichard Fitzgerald 21967e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 22067e38cf2SRalf Baechle bool 22167e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 2220f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 22367e38cf2SRalf Baechle select IRQ_DOMAIN 2240e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 22567e38cf2SRalf Baechle 226afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 227afc98d90SAlexander Shiyan bool 228afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 229afc98d90SAlexander Shiyan select IRQ_DOMAIN 230afc98d90SAlexander Shiyan select SPARSE_IRQ 231afc98d90SAlexander Shiyan default y 232afc98d90SAlexander Shiyan 2339b54470aSStafford Horneconfig OMPIC 2349b54470aSStafford Horne bool 2359b54470aSStafford Horne 2364db8e6d2SStefan Kristianssonconfig OR1K_PIC 2374db8e6d2SStefan Kristiansson bool 2384db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2394db8e6d2SStefan Kristiansson 2408598066cSFelipe Balbiconfig OMAP_IRQCHIP 2418598066cSFelipe Balbi bool 2428598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2438598066cSFelipe Balbi select IRQ_DOMAIN 2448598066cSFelipe Balbi 2459dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2469dbd90f1SSebastian Hesselbarth bool 2479dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2489dbd90f1SSebastian Hesselbarth 249aaa8666aSCristian Birsanconfig PIC32_EVIC 250aaa8666aSCristian Birsan bool 251aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 252aaa8666aSCristian Birsan select IRQ_DOMAIN 253aaa8666aSCristian Birsan 254981b58f6SRich Felkerconfig JCORE_AIC 2553602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2563602ffdeSRich Felker depends on OF 257981b58f6SRich Felker select IRQ_DOMAIN 258981b58f6SRich Felker help 259981b58f6SRich Felker Support for the J-Core integrated AIC. 260981b58f6SRich Felker 261d852e62aSManivannan Sadhasivamconfig RDA_INTC 262d852e62aSManivannan Sadhasivam bool 263d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 264d852e62aSManivannan Sadhasivam 26544358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 26602d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 26744358048SMagnus Damm select IRQ_DOMAIN 26802d7e041SGeert Uytterhoeven help 26902d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 27002d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 27144358048SMagnus Damm 272fbc83b7fSMagnus Dammconfig RENESAS_IRQC 27372d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 27499c221dfSMagnus Damm select GENERIC_IRQ_CHIP 275fbc83b7fSMagnus Damm select IRQ_DOMAIN 27602d7e041SGeert Uytterhoeven help 27702d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 27872d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 279fbc83b7fSMagnus Damm 280a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 28102d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 282a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 28302d7e041SGeert Uytterhoeven help 28402d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 28502d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 286a644ccb8SGeert Uytterhoeven 2873fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2883fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2893fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2903fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2913fed0955SLad Prabhakar help 2923fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2933fed0955SLad Prabhakar for external devices. 2943fed0955SLad Prabhakar 2950d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2960d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 2970d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 2980d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 2990d7605e7SFabrizio Castro help 3000d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 3010d7605e7SFabrizio Castro 30203ac990eSMichael Walleconfig SL28CPLD_INTC 30303ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 30403ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 30503ac990eSMichael Walle select REGMAP_IRQ 30603ac990eSMichael Walle help 30703ac990eSMichael Walle Interrupt controller driver for the board management controller 30803ac990eSMichael Walle found on the Kontron sl28 CPLD. 30903ac990eSMichael Walle 31007088484SLee Jonesconfig ST_IRQCHIP 31107088484SLee Jones bool 31207088484SLee Jones select REGMAP 31307088484SLee Jones select MFD_SYSCON 31407088484SLee Jones help 31507088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 31607088484SLee Jones 317d421fd6dSSamuel Hollandconfig SUN4I_INTC 318d421fd6dSSamuel Holland bool 319d421fd6dSSamuel Holland 320d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 321d421fd6dSSamuel Holland bool 322d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 323d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 324d421fd6dSSamuel Holland 325d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 326d421fd6dSSamuel Holland bool 327d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 328d421fd6dSSamuel Holland 329b06eb017SChristian Ruppertconfig TB10X_IRQC 330b06eb017SChristian Ruppert bool 331b06eb017SChristian Ruppert select IRQ_DOMAIN 332b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 333b06eb017SChristian Ruppert 334d01f8633SDamien Riegelconfig TS4800_IRQ 335d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 336d01f8633SDamien Riegel select IRQ_DOMAIN 3370df337cfSRichard Weinberger depends on HAS_IOMEM 338d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 339d01f8633SDamien Riegel help 340d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 341d01f8633SDamien Riegel 3422389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3432389d501SLinus Walleij bool 3442389d501SLinus Walleij select IRQ_DOMAIN 3452389d501SLinus Walleij 3462389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3472389d501SLinus Walleij int 3482389d501SLinus Walleij default 4 3492389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 35026a8e96aSMax Filippov 35126a8e96aSMax Filippovconfig XTENSA_MX 35226a8e96aSMax Filippov bool 35326a8e96aSMax Filippov select IRQ_DOMAIN 3540e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 35596ca848eSSricharan R 3560547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 357debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 358fd31000dSJamie Iles depends on OF_ADDRESS 3590547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 360debf69cfSRobert Hancock help 361debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 362debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 363debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3640547dc78SZubair Lutfullah Kakakhel 36596ca848eSSricharan Rconfig IRQ_CROSSBAR 36696ca848eSSricharan R bool 36796ca848eSSricharan R help 368f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 36996ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 37096ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 37196ca848eSSricharan R routed to one of the free irqchip interrupt lines. 37289323f8cSGrygorii Strashko 37389323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 37489323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 37589323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 37689323f8cSGrygorii Strashko help 37789323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 37889323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3798a19b8f1SAndrew Bresticker 3808a19b8f1SAndrew Brestickerconfig MIPS_GIC 3818a19b8f1SAndrew Bresticker bool 3820053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3838190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3848190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3858a19b8f1SAndrew Bresticker select MIPS_CM 3868a764482SYoshinori Sato 38744e08e70SPaul Burtonconfig INGENIC_IRQ 38844e08e70SPaul Burton bool 38944e08e70SPaul Burton depends on MACH_INGENIC 39044e08e70SPaul Burton default y 39178c10e55SLinus Torvalds 3929536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3939536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3949536eba0SPaul Cercueil default MACH_INGENIC 3959536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3969536eba0SPaul Cercueil select MFD_SYSCON 3978084499bSYueHaibing select GENERIC_IRQ_CHIP 3989536eba0SPaul Cercueil help 3999536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 4009536eba0SPaul Cercueil JZ47xx SoCs. 4019536eba0SPaul Cercueil 4029536eba0SPaul Cercueil If unsure, say N. 4039536eba0SPaul Cercueil 404e324c4dcSShenwei Wangconfig IMX_GPCV2 405e324c4dcSShenwei Wang bool 406e324c4dcSShenwei Wang select IRQ_DOMAIN 407e324c4dcSShenwei Wang help 408e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 4097e4ac676SOleksij Rempel 4107e4ac676SOleksij Rempelconfig IRQ_MXS 4117e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 4127e4ac676SOleksij Rempel select IRQ_DOMAIN 4137e4ac676SOleksij Rempel select STMP_DEVICE 414c27f29bbSThomas Petazzoni 41519d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 41619d99164SAlexandre Belloni bool 41719d99164SAlexandre Belloni select IRQ_DOMAIN 41819d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 41919d99164SAlexandre Belloni 420a68a63cbSThomas Petazzoniconfig MVEBU_GICP 421cdb23872SThomas Gleixner select IRQ_MSI_LIB 422a68a63cbSThomas Petazzoni bool 423a68a63cbSThomas Petazzoni 424e0de91a9SThomas Petazzoniconfig MVEBU_ICU 425e0de91a9SThomas Petazzoni bool 426e0de91a9SThomas Petazzoni 427c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 428c27f29bbSThomas Petazzoni bool 429e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 43013e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4319e2c986cSMarc Zyngier 432a109893bSThomas Petazzoniconfig MVEBU_PIC 433a109893bSThomas Petazzoni bool 434a109893bSThomas Petazzoni 43561ce8d8dSMiquel Raynalconfig MVEBU_SEI 43661ce8d8dSMiquel Raynal bool 43761ce8d8dSMiquel Raynal 4380dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4390dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4400dcd9f87SRasmus Villemoes select MFD_SYSCON 4410dcd9f87SRasmus Villemoes 442b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 443b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 44496093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4459c1a7bfcSLukas Bulwahn depends on PCI_MSI 446b8f3ebe6SMinghuan Lian 4479e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4489e2c986cSMarc Zyngier bool 4490efacbbaSLinus Torvalds 450b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4510be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4520be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4539151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4540be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 455350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4560be58e05SAntonio Borneo help 4570be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 458b20cf2dcSAntonio Borneo 459e0720416SAlexandre TORGUEconfig STM32_EXTI 460e0720416SAlexandre TORGUE bool 461e0720416SAlexandre TORGUE select IRQ_DOMAIN 4620e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 463f20cc9b0SAgustin Vega-Frias 464f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 465f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 466f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 467f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 468f20cc9b0SAgustin Vega-Frias help 469f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 470f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4715ed34d3aSMasahiro Yamada 4725ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4735ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4745ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4755ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4765ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4775ed34d3aSMasahiro Yamada help 4785ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 479c94fb639SRandy Dunlap 480215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 481a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 482a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 483a947aa00SNeil Armstrong default ARCH_MESON 484215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 485215f4cc0SJerome Brunet help 486215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 487215f4cc0SJerome Brunet 4884235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4894235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4904235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 491969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4924235ff50SMiodrag Dinic select IRQ_DOMAIN 4934235ff50SMiodrag Dinic help 4944235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4954235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4964235ff50SMiodrag Dinic 497f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4984acd8a4bSSaravana Kannan tristate "QCOM PDC" 499f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 500f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 501f55c73aeSArchana Sathyakumar help 502f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 503f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 504f55c73aeSArchana Sathyakumar 505a6199bb5SShawn Guoconfig QCOM_MPM 506a6199bb5SShawn Guo tristate "QCOM MPM" 507a6199bb5SShawn Guo depends on ARCH_QCOM 508fa4dcc88SYueHaibing depends on MAILBOX 509a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 510a6199bb5SShawn Guo help 511a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 512a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 513a6199bb5SShawn Guo 514d8a5f5f7SGuo Renconfig CSKY_MPINTC 515be1abc5bSGuo Ren bool 516d8a5f5f7SGuo Ren depends on CSKY 517d8a5f5f7SGuo Ren help 518d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 519d8a5f5f7SGuo Ren for C-SKY SMP system. 520656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 521d8a5f5f7SGuo Ren controller's register inside CPU. 522d8a5f5f7SGuo Ren 523edff1b48SGuo Renconfig CSKY_APB_INTC 524edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 525edff1b48SGuo Ren depends on CSKY 526edff1b48SGuo Ren help 527edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 528656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 529edff1b48SGuo Ren the controller's register. 530edff1b48SGuo Ren 5310136afa0SLucas Stachconfig IMX_IRQSTEER 5320136afa0SLucas Stach bool "i.MX IRQSTEER support" 5330136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5340136afa0SLucas Stach default ARCH_MXC 5350136afa0SLucas Stach select IRQ_DOMAIN 5360136afa0SLucas Stach help 5370136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5380136afa0SLucas Stach 5392fbb1396SJoakim Zhangconfig IMX_INTMUX 540a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 541a890caebSGeert Uytterhoeven default y if ARCH_MXC 5422fbb1396SJoakim Zhang select IRQ_DOMAIN 5432fbb1396SJoakim Zhang help 5442fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5452fbb1396SJoakim Zhang 54670afdab9SFrank Liconfig IMX_MU_MSI 54770afdab9SFrank Li tristate "i.MX MU used as MSI controller" 54870afdab9SFrank Li depends on OF && HAS_IOMEM 5496c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 55070afdab9SFrank Li default m if ARCH_MXC 55170afdab9SFrank Li select IRQ_DOMAIN 55270afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 55313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5547b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 55570afdab9SFrank Li help 5566c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5576c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5586c9f7434SGeert Uytterhoeven to make use of this driver. 55970afdab9SFrank Li 56070afdab9SFrank Li If unsure, say N 56170afdab9SFrank Li 5629e543e22SJiaxun Yangconfig LS1X_IRQ 5639e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5649e543e22SJiaxun Yang depends on MACH_LOONGSON32 5659e543e22SJiaxun Yang default y 5669e543e22SJiaxun Yang select IRQ_DOMAIN 5679e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5689e543e22SJiaxun Yang help 5699e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5709e543e22SJiaxun Yang 571cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5722d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 573cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5742d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 575cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 576cd844b07SLokesh Vutla help 577cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 578cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 579cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 580cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 581cd844b07SLokesh Vutla 5829f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 583b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5849f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 585b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5869f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 587f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5889f1463b8SLokesh Vutla help 5899f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5909f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5919f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5929f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5939f1463b8SLokesh Vutla 59404e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 595b8e594faSSuman Anna tristate 596b8e594faSSuman Anna depends on TI_PRUSS 597b8e594faSSuman Anna default TI_PRUSS 59804e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 59904e2d1e0SGrzegorz Jaszczyk help 60004e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 60104e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 60204e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 60304e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 60404e2d1e0SGrzegorz Jaszczyk 6056b7ce892SAnup Patelconfig RISCV_INTC 606d8fb1307SConor Dooley bool 6076b7ce892SAnup Patel depends on RISCV 608832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 6096b7ce892SAnup Patel 6102333df5aSAnup Patelconfig RISCV_APLIC 6112333df5aSAnup Patel bool 6122333df5aSAnup Patel depends on RISCV 6132333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 6142333df5aSAnup Patel 615ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 616ca8df97fSAnup Patel bool 617ca8df97fSAnup Patel depends on RISCV_APLIC 618ca8df97fSAnup Patel select GENERIC_MSI_IRQ 619ca8df97fSAnup Patel default RISCV_APLIC 620ca8df97fSAnup Patel 62121a8f8a0SAnup Patelconfig RISCV_IMSIC 62221a8f8a0SAnup Patel bool 62321a8f8a0SAnup Patel depends on RISCV 62421a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 62521a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 62621a8f8a0SAnup Patel select GENERIC_MSI_IRQ 627fe35eceeSThomas Gleixner select IRQ_MSI_LIB 6285c5a71d0SAnup Patel 6298237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 630fdb1742aSConor Dooley bool 6318237f8bcSChristoph Hellwig depends on RISCV 632466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 633de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 63401493855SJonathan Neuschäfer 635e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 636e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 637e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 638e4e53503SChanghuang Liang default ARCH_STARFIVE 639e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 640e4e53503SChanghuang Liang help 641e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 642e4e53503SChanghuang Liang SoC. 643e4e53503SChanghuang Liang 644e4e53503SChanghuang Liang If you don't know what to do here, say Y. 645e4e53503SChanghuang Liang 64625caea95SInochi Amaotoconfig THEAD_C900_ACLINT_SSWI 64725caea95SInochi Amaoto bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 64825caea95SInochi Amaoto depends on RISCV 64925caea95SInochi Amaoto depends on SMP 65025caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 65125caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 65225caea95SInochi Amaoto help 65325caea95SInochi Amaoto This enables support for T-HEAD specific ACLINT SSWI device 65425caea95SInochi Amaoto support. 65525caea95SInochi Amaoto 65625caea95SInochi Amaoto If you don't know what to do here, say Y. 65725caea95SInochi Amaoto 658b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 659b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 660b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 661b74416dbSHyunki Koo help 662b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 663b74416dbSHyunki Koo in Samsung Exynos chips. 664b74416dbSHyunki Koo 665b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 666b2d3e335SHuacai Chen bool 667b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 668b2d3e335SHuacai Chen select IRQ_DOMAIN 66942a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 67070f7b6c0SHuacai Chen select LOONGSON_HTVEC 6718d5356f9SHuacai Chen select LOONGSON_LIOINTC 6728d5356f9SHuacai Chen select LOONGSON_EIOINTC 6738d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6748d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6758d5356f9SHuacai Chen select LOONGSON_PCH_LPC 676b2d3e335SHuacai Chen help 677b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 678b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 67951712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 680b2d3e335SHuacai Chen 681dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 682dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 683dbb15226SJiaxun Yang depends on MACH_LOONGSON64 684dbb15226SJiaxun Yang default y 685dbb15226SJiaxun Yang select IRQ_DOMAIN 686dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 687dbb15226SJiaxun Yang help 688dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 689dbb15226SJiaxun Yang 690dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 691dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 692dd281e1aSHuacai Chen depends on LOONGARCH 693dd281e1aSHuacai Chen depends on MACH_LOONGSON64 694dd281e1aSHuacai Chen default MACH_LOONGSON64 695dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 696dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 697dd281e1aSHuacai Chen help 698dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 699dd281e1aSHuacai Chen 700a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 701a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 702987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 703a93f1d90SJiaxun Yang default y 704a93f1d90SJiaxun Yang select IRQ_DOMAIN 705a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 706a93f1d90SJiaxun Yang help 707a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 708a93f1d90SJiaxun Yang 709818e915fSJiaxun Yangconfig LOONGSON_HTVEC 710987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 711d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 712818e915fSJiaxun Yang default MACH_LOONGSON64 713818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 714818e915fSJiaxun Yang help 715987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 716818e915fSJiaxun Yang 717ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 718ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 719bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 720ef8c01ebSJiaxun Yang default MACH_LOONGSON64 721ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 722ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 723ef8c01ebSJiaxun Yang help 724ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 725ef8c01ebSJiaxun Yang 726632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 727a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 72802308732SHuacai Chen depends on MACH_LOONGSON64 729632dcc2cSJiaxun Yang depends on PCI 730632dcc2cSJiaxun Yang default MACH_LOONGSON64 731632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7320b3af759SHuacai Chen select IRQ_MSI_LIB 733632dcc2cSJiaxun Yang select PCI_MSI 734632dcc2cSJiaxun Yang help 735632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 736632dcc2cSJiaxun Yang 737ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 738ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 739e7ccba77SJianmin Lv depends on LOONGARCH 740ee73f14eSHuacai Chen depends on MACH_LOONGSON64 741e7ccba77SJianmin Lv default MACH_LOONGSON64 742ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 743ee73f14eSHuacai Chen help 744ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 745ee73f14eSHuacai Chen 746ad4c938cSMark-PK Tsaiconfig MST_IRQ 747ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 74861b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 749ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 750ad4c938cSMark-PK Tsai select IRQ_DOMAIN 751ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 752ad4c938cSMark-PK Tsai help 753ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 754ad4c938cSMark-PK Tsai 755fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 756fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 75794bc9420SMarc Zyngier depends on ARCH_WPCM450 758fead4dd4SJonathan Neuschäfer help 759fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 760fead4dd4SJonathan Neuschäfer 761529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 762529ea368SThomas Bogendoerfer bool 763529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 764529ea368SThomas Bogendoerfer select IRQ_DOMAIN 765529ea368SThomas Bogendoerfer 76676cde263SHector Martinconfig APPLE_AIC 76776cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 76876cde263SHector Martin depends on ARM64 7695b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 770c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 77176cde263SHector Martin help 77276cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 77376cde263SHector Martin such as the M1. 77476cde263SHector Martin 77500fa3461SClaudiu Bezneaconfig MCHP_EIC 77600fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 77700fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 77800fa3461SClaudiu Beznea select IRQ_DOMAIN 77900fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 78000fa3461SClaudiu Beznea help 78100fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 78200fa3461SClaudiu Beznea 783c6674154SChen Wangconfig SOPHGO_SG2042_MSI 784c6674154SChen Wang bool "Sophgo SG2042 MSI Controller" 785c6674154SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 786c6674154SChen Wang depends on PCI 787c6674154SChen Wang select IRQ_DOMAIN_HIERARCHY 788c6674154SChen Wang select IRQ_MSI_LIB 789c6674154SChen Wang select PCI_MSI 790c6674154SChen Wang help 791c6674154SChen Wang Support for the Sophgo SG2042 MSI Controller. 792c6674154SChen Wang This on-chip interrupt controller enables MSI sources to be 793c6674154SChen Wang routed to the primary PLIC controller on SoC. 794c6674154SChen Wang 795f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 796f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 797f7189d93SQin Jian default SOC_SP7021 798f7189d93SQin Jian help 799f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 800f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 801f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 802f7189d93SQin Jian the primary controller on C-Chip. 803f7189d93SQin Jian 80401493855SJonathan Neuschäferendmenu 805