1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 3196093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 4296093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 4419812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4519812729SMarc Zyngier bool 4613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4748f71d56SThomas Gleixner select IRQ_MSI_LIB 4829f41139SMarc Zyngier default ARM_GIC_V3 4996093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5029f41139SMarc Zyngier 517afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 527afe031cSBogdan Purcareata bool 537afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 547afe031cSBogdan Purcareata depends on FSL_MC_BUS 557afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata 57292ec080SUwe Kleine-Königconfig ARM_NVIC 58292ec080SUwe Kleine-König bool 592d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 60292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 61292ec080SUwe Kleine-König 6244430ec0SRob Herringconfig ARM_VIC 6344430ec0SRob Herring bool 6444430ec0SRob Herring select IRQ_DOMAIN 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC_NR 6744430ec0SRob Herring int 6844430ec0SRob Herring default 4 if ARCH_S5PV210 6944430ec0SRob Herring default 2 7044430ec0SRob Herring depends on ARM_VIC 7144430ec0SRob Herring help 7244430ec0SRob Herring The maximum number of VICs available in the system, for 7344430ec0SRob Herring power management. 7444430ec0SRob Herring 7572e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 7672e257c6SThomas Gleixner bool 7772e257c6SThomas Gleixner 78fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 79fed6d336SThomas Petazzoni bool 80fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 813ee80364SArnd Bergmann select PCI_MSI if PCI 820e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 83fed6d336SThomas Petazzoni 84e6b78f2cSAntoine Tenartconfig ALPINE_MSI 85e6b78f2cSAntoine Tenart bool 863ee80364SArnd Bergmann depends on PCI 873ee80364SArnd Bergmann select PCI_MSI 88e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 89e6b78f2cSAntoine Tenart 901eb77c3bSTalel Shenharconfig AL_FIC 911eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 929869f37aSJean Delvare depends on OF 9335e0cd77SBaoquan He depends on HAS_IOMEM 941eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 951eb77c3bSTalel Shenhar select IRQ_DOMAIN 961eb77c3bSTalel Shenhar help 971eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 981eb77c3bSTalel Shenhar 99b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 100b1479ebbSBoris BREZILLON bool 101b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 102b1479ebbSBoris BREZILLON select IRQ_DOMAIN 103b1479ebbSBoris BREZILLON select SPARSE_IRQ 104b1479ebbSBoris BREZILLON 105b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 106b1479ebbSBoris BREZILLON bool 107b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 108b1479ebbSBoris BREZILLON select IRQ_DOMAIN 109b1479ebbSBoris BREZILLON select SPARSE_IRQ 110b1479ebbSBoris BREZILLON 1110509cfdeSRalf Baechleconfig I8259 1120509cfdeSRalf Baechle bool 1130509cfdeSRalf Baechle select IRQ_DOMAIN 1140509cfdeSRalf Baechle 11532c6c054SStanimir Varbanovconfig BCM2712_MIP 11632c6c054SStanimir Varbanov tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 117*9b3ae50cSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 118*9b3ae50cSPeter Robinson default m if ARCH_BRCMSTB || ARCH_BCM2835 11932c6c054SStanimir Varbanov depends on ARM_GIC 12032c6c054SStanimir Varbanov select GENERIC_IRQ_CHIP 12132c6c054SStanimir Varbanov select IRQ_DOMAIN_HIERARCHY 12232c6c054SStanimir Varbanov select GENERIC_MSI_IRQ 12332c6c054SStanimir Varbanov select IRQ_MSI_LIB 12432c6c054SStanimir Varbanov help 12532c6c054SStanimir Varbanov Enable support for the Broadcom BCM2712 MSI-X target peripheral 12632c6c054SStanimir Varbanov (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 12732c6c054SStanimir Varbanov Raspberry Pi 5. 12832c6c054SStanimir Varbanov 12932c6c054SStanimir Varbanov If unsure say n. 13032c6c054SStanimir Varbanov 131c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 132c7c42ec2SSimon Arlott bool 133c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 134c7c42ec2SSimon Arlott select IRQ_DOMAIN 1350e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 136c7c42ec2SSimon Arlott 1375f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 138c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 139c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 140c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1415f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1425f7f0317SKevin Cernekee select IRQ_DOMAIN 1430e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1445f7f0317SKevin Cernekee 145a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1463ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1473ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1483ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 149a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 150a4fcbb86SKevin Cernekee select IRQ_DOMAIN 151a4fcbb86SKevin Cernekee 1527f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 15351d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 15451d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 15551d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1567f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1577f646e92SFlorian Fainelli select IRQ_DOMAIN 1587f646e92SFlorian Fainelli 1590fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1600fc3d74cSBartosz Golaszewski bool 1610fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1620fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1630fc3d74cSBartosz Golaszewski 164350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 165be5e5f3aSThomas Gleixner bool 166e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 16754a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 168350d71b9SSebastian Hesselbarth 1696ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1706ee532e2SLinus Walleij bool 1716ee532e2SLinus Walleij select IRQ_DOMAIN 1726ee532e2SLinus Walleij select SPARSE_IRQ 1736ee532e2SLinus Walleij 1749a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1759a7c4abdSMaJun bool 1769a7c4abdSMaJun select ARM_GIC_V3 1779a7c4abdSMaJun select ARM_GIC_V3_ITS 1789a7c4abdSMaJun 179b6ef9161SJames Hoganconfig IMGPDC_IRQ 180b6ef9161SJames Hogan bool 181b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 182b6ef9161SJames Hogan select IRQ_DOMAIN 183b6ef9161SJames Hogan 1845b978c10SLinus Walleijconfig IXP4XX_IRQ 1855b978c10SLinus Walleij bool 1865b978c10SLinus Walleij select IRQ_DOMAIN 1875b978c10SLinus Walleij select SPARSE_IRQ 1885b978c10SLinus Walleij 1893e3a7b35SHerve Codinaconfig LAN966X_OIC 1903e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 191e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 1923e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 1933e3a7b35SHerve Codina select IRQ_DOMAIN 1943e3a7b35SHerve Codina help 1953e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 1963e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 1973e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 1983e3a7b35SHerve Codina 1993e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 2003e3a7b35SHerve Codina will be called irq-lan966x-oic. 2013e3a7b35SHerve Codina 202da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 203da0abe1aSRichard Fitzgerald tristate 204da0abe1aSRichard Fitzgerald 20567e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 20667e38cf2SRalf Baechle bool 20767e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 2080f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 20967e38cf2SRalf Baechle select IRQ_DOMAIN 2100e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 21167e38cf2SRalf Baechle 212afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 213afc98d90SAlexander Shiyan bool 214afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 215afc98d90SAlexander Shiyan select IRQ_DOMAIN 216afc98d90SAlexander Shiyan select SPARSE_IRQ 217afc98d90SAlexander Shiyan default y 218afc98d90SAlexander Shiyan 2199b54470aSStafford Horneconfig OMPIC 2209b54470aSStafford Horne bool 2219b54470aSStafford Horne 2224db8e6d2SStefan Kristianssonconfig OR1K_PIC 2234db8e6d2SStefan Kristiansson bool 2244db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2254db8e6d2SStefan Kristiansson 2268598066cSFelipe Balbiconfig OMAP_IRQCHIP 2278598066cSFelipe Balbi bool 2288598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2298598066cSFelipe Balbi select IRQ_DOMAIN 2308598066cSFelipe Balbi 2319dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2329dbd90f1SSebastian Hesselbarth bool 2339dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2349dbd90f1SSebastian Hesselbarth 235aaa8666aSCristian Birsanconfig PIC32_EVIC 236aaa8666aSCristian Birsan bool 237aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 238aaa8666aSCristian Birsan select IRQ_DOMAIN 239aaa8666aSCristian Birsan 240981b58f6SRich Felkerconfig JCORE_AIC 2413602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2423602ffdeSRich Felker depends on OF 243981b58f6SRich Felker select IRQ_DOMAIN 244981b58f6SRich Felker help 245981b58f6SRich Felker Support for the J-Core integrated AIC. 246981b58f6SRich Felker 247d852e62aSManivannan Sadhasivamconfig RDA_INTC 248d852e62aSManivannan Sadhasivam bool 249d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 250d852e62aSManivannan Sadhasivam 25144358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 25202d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 25344358048SMagnus Damm select IRQ_DOMAIN 25402d7e041SGeert Uytterhoeven help 25502d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 25602d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 25744358048SMagnus Damm 258fbc83b7fSMagnus Dammconfig RENESAS_IRQC 25972d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 26099c221dfSMagnus Damm select GENERIC_IRQ_CHIP 261fbc83b7fSMagnus Damm select IRQ_DOMAIN 26202d7e041SGeert Uytterhoeven help 26302d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 26472d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 265fbc83b7fSMagnus Damm 266a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 26702d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 268a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 26902d7e041SGeert Uytterhoeven help 27002d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 27102d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 272a644ccb8SGeert Uytterhoeven 2733fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2743fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2753fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2763fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2773fed0955SLad Prabhakar help 2783fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2793fed0955SLad Prabhakar for external devices. 2803fed0955SLad Prabhakar 2810d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2820d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 2830d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 2840d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 2850d7605e7SFabrizio Castro help 2860d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 2870d7605e7SFabrizio Castro 28803ac990eSMichael Walleconfig SL28CPLD_INTC 28903ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 29003ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 29103ac990eSMichael Walle select REGMAP_IRQ 29203ac990eSMichael Walle help 29303ac990eSMichael Walle Interrupt controller driver for the board management controller 29403ac990eSMichael Walle found on the Kontron sl28 CPLD. 29503ac990eSMichael Walle 29607088484SLee Jonesconfig ST_IRQCHIP 29707088484SLee Jones bool 29807088484SLee Jones select REGMAP 29907088484SLee Jones select MFD_SYSCON 30007088484SLee Jones help 30107088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 30207088484SLee Jones 303d421fd6dSSamuel Hollandconfig SUN4I_INTC 304d421fd6dSSamuel Holland bool 305d421fd6dSSamuel Holland 306d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 307d421fd6dSSamuel Holland bool 308d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 309d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 310d421fd6dSSamuel Holland 311d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 312d421fd6dSSamuel Holland bool 313d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 314d421fd6dSSamuel Holland 315b06eb017SChristian Ruppertconfig TB10X_IRQC 316b06eb017SChristian Ruppert bool 317b06eb017SChristian Ruppert select IRQ_DOMAIN 318b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 319b06eb017SChristian Ruppert 320d01f8633SDamien Riegelconfig TS4800_IRQ 321d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 322d01f8633SDamien Riegel select IRQ_DOMAIN 3230df337cfSRichard Weinberger depends on HAS_IOMEM 324d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 325d01f8633SDamien Riegel help 326d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 327d01f8633SDamien Riegel 3282389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3292389d501SLinus Walleij bool 3302389d501SLinus Walleij select IRQ_DOMAIN 3312389d501SLinus Walleij 3322389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3332389d501SLinus Walleij int 3342389d501SLinus Walleij default 4 3352389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 33626a8e96aSMax Filippov 33726a8e96aSMax Filippovconfig XTENSA_MX 33826a8e96aSMax Filippov bool 33926a8e96aSMax Filippov select IRQ_DOMAIN 3400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 34196ca848eSSricharan R 3420547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 343debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 344fd31000dSJamie Iles depends on OF_ADDRESS 3450547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 346debf69cfSRobert Hancock help 347debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 348debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 349debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3500547dc78SZubair Lutfullah Kakakhel 35196ca848eSSricharan Rconfig IRQ_CROSSBAR 35296ca848eSSricharan R bool 35396ca848eSSricharan R help 354f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 35596ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 35696ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 35796ca848eSSricharan R routed to one of the free irqchip interrupt lines. 35889323f8cSGrygorii Strashko 35989323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 36089323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 36189323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 36289323f8cSGrygorii Strashko help 36389323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 36489323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3658a19b8f1SAndrew Bresticker 3668a19b8f1SAndrew Brestickerconfig MIPS_GIC 3678a19b8f1SAndrew Bresticker bool 3680053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3698190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3708190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3718a19b8f1SAndrew Bresticker select MIPS_CM 3728a764482SYoshinori Sato 37344e08e70SPaul Burtonconfig INGENIC_IRQ 37444e08e70SPaul Burton bool 37544e08e70SPaul Burton depends on MACH_INGENIC 37644e08e70SPaul Burton default y 37778c10e55SLinus Torvalds 3789536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3799536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3809536eba0SPaul Cercueil default MACH_INGENIC 3819536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3829536eba0SPaul Cercueil select MFD_SYSCON 3838084499bSYueHaibing select GENERIC_IRQ_CHIP 3849536eba0SPaul Cercueil help 3859536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3869536eba0SPaul Cercueil JZ47xx SoCs. 3879536eba0SPaul Cercueil 3889536eba0SPaul Cercueil If unsure, say N. 3899536eba0SPaul Cercueil 390e324c4dcSShenwei Wangconfig IMX_GPCV2 391e324c4dcSShenwei Wang bool 392e324c4dcSShenwei Wang select IRQ_DOMAIN 393e324c4dcSShenwei Wang help 394e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3957e4ac676SOleksij Rempel 3967e4ac676SOleksij Rempelconfig IRQ_MXS 3977e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3987e4ac676SOleksij Rempel select IRQ_DOMAIN 3997e4ac676SOleksij Rempel select STMP_DEVICE 400c27f29bbSThomas Petazzoni 40119d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 40219d99164SAlexandre Belloni bool 40319d99164SAlexandre Belloni select IRQ_DOMAIN 40419d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 40519d99164SAlexandre Belloni 406a68a63cbSThomas Petazzoniconfig MVEBU_GICP 407cdb23872SThomas Gleixner select IRQ_MSI_LIB 408a68a63cbSThomas Petazzoni bool 409a68a63cbSThomas Petazzoni 410e0de91a9SThomas Petazzoniconfig MVEBU_ICU 411e0de91a9SThomas Petazzoni bool 412e0de91a9SThomas Petazzoni 413c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 414c27f29bbSThomas Petazzoni bool 415e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 41613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4179e2c986cSMarc Zyngier 418a109893bSThomas Petazzoniconfig MVEBU_PIC 419a109893bSThomas Petazzoni bool 420a109893bSThomas Petazzoni 42161ce8d8dSMiquel Raynalconfig MVEBU_SEI 42261ce8d8dSMiquel Raynal bool 42361ce8d8dSMiquel Raynal 4240dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4250dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4260dcd9f87SRasmus Villemoes select MFD_SYSCON 4270dcd9f87SRasmus Villemoes 428b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 429b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 43096093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4319c1a7bfcSLukas Bulwahn depends on PCI_MSI 432b8f3ebe6SMinghuan Lian 4339e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4349e2c986cSMarc Zyngier bool 4350efacbbaSLinus Torvalds 436b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4370be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4380be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4399151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4400be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 441350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4420be58e05SAntonio Borneo help 4430be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 444b20cf2dcSAntonio Borneo 445e0720416SAlexandre TORGUEconfig STM32_EXTI 446e0720416SAlexandre TORGUE bool 447e0720416SAlexandre TORGUE select IRQ_DOMAIN 4480e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 449f20cc9b0SAgustin Vega-Frias 450f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 451f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 452f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 453f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 454f20cc9b0SAgustin Vega-Frias help 455f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 456f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4575ed34d3aSMasahiro Yamada 4585ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4595ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4605ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4615ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4625ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4635ed34d3aSMasahiro Yamada help 4645ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 465c94fb639SRandy Dunlap 466215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 467a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 468a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 469a947aa00SNeil Armstrong default ARCH_MESON 470215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 471215f4cc0SJerome Brunet help 472215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 473215f4cc0SJerome Brunet 4744235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4754235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4764235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 477969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4784235ff50SMiodrag Dinic select IRQ_DOMAIN 4794235ff50SMiodrag Dinic help 4804235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4814235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4824235ff50SMiodrag Dinic 483f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4844acd8a4bSSaravana Kannan tristate "QCOM PDC" 485f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 486f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 487f55c73aeSArchana Sathyakumar help 488f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 489f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 490f55c73aeSArchana Sathyakumar 491a6199bb5SShawn Guoconfig QCOM_MPM 492a6199bb5SShawn Guo tristate "QCOM MPM" 493a6199bb5SShawn Guo depends on ARCH_QCOM 494fa4dcc88SYueHaibing depends on MAILBOX 495a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 496a6199bb5SShawn Guo help 497a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 498a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 499a6199bb5SShawn Guo 500d8a5f5f7SGuo Renconfig CSKY_MPINTC 501be1abc5bSGuo Ren bool 502d8a5f5f7SGuo Ren depends on CSKY 503d8a5f5f7SGuo Ren help 504d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 505d8a5f5f7SGuo Ren for C-SKY SMP system. 506656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 507d8a5f5f7SGuo Ren controller's register inside CPU. 508d8a5f5f7SGuo Ren 509edff1b48SGuo Renconfig CSKY_APB_INTC 510edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 511edff1b48SGuo Ren depends on CSKY 512edff1b48SGuo Ren help 513edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 514656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 515edff1b48SGuo Ren the controller's register. 516edff1b48SGuo Ren 5170136afa0SLucas Stachconfig IMX_IRQSTEER 5180136afa0SLucas Stach bool "i.MX IRQSTEER support" 5190136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5200136afa0SLucas Stach default ARCH_MXC 5210136afa0SLucas Stach select IRQ_DOMAIN 5220136afa0SLucas Stach help 5230136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5240136afa0SLucas Stach 5252fbb1396SJoakim Zhangconfig IMX_INTMUX 526a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 527a890caebSGeert Uytterhoeven default y if ARCH_MXC 5282fbb1396SJoakim Zhang select IRQ_DOMAIN 5292fbb1396SJoakim Zhang help 5302fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5312fbb1396SJoakim Zhang 53270afdab9SFrank Liconfig IMX_MU_MSI 53370afdab9SFrank Li tristate "i.MX MU used as MSI controller" 53470afdab9SFrank Li depends on OF && HAS_IOMEM 5356c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 53670afdab9SFrank Li default m if ARCH_MXC 53770afdab9SFrank Li select IRQ_DOMAIN 53870afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 53913e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5407b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 54170afdab9SFrank Li help 5426c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5436c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5446c9f7434SGeert Uytterhoeven to make use of this driver. 54570afdab9SFrank Li 54670afdab9SFrank Li If unsure, say N 54770afdab9SFrank Li 5489e543e22SJiaxun Yangconfig LS1X_IRQ 5499e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5509e543e22SJiaxun Yang depends on MACH_LOONGSON32 5519e543e22SJiaxun Yang default y 5529e543e22SJiaxun Yang select IRQ_DOMAIN 5539e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5549e543e22SJiaxun Yang help 5559e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5569e543e22SJiaxun Yang 557cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5582d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 559cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5602d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 561cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 562cd844b07SLokesh Vutla help 563cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 564cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 565cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 566cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 567cd844b07SLokesh Vutla 5689f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 569b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5709f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 571b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5729f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 573f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5749f1463b8SLokesh Vutla help 5759f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5769f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5779f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5789f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5799f1463b8SLokesh Vutla 58004e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 581b8e594faSSuman Anna tristate 582b8e594faSSuman Anna depends on TI_PRUSS 583b8e594faSSuman Anna default TI_PRUSS 58404e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 58504e2d1e0SGrzegorz Jaszczyk help 58604e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 58704e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 58804e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 58904e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 59004e2d1e0SGrzegorz Jaszczyk 5916b7ce892SAnup Patelconfig RISCV_INTC 592d8fb1307SConor Dooley bool 5936b7ce892SAnup Patel depends on RISCV 594832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5956b7ce892SAnup Patel 5962333df5aSAnup Patelconfig RISCV_APLIC 5972333df5aSAnup Patel bool 5982333df5aSAnup Patel depends on RISCV 5992333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 6002333df5aSAnup Patel 601ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 602ca8df97fSAnup Patel bool 603ca8df97fSAnup Patel depends on RISCV_APLIC 604ca8df97fSAnup Patel select GENERIC_MSI_IRQ 605ca8df97fSAnup Patel default RISCV_APLIC 606ca8df97fSAnup Patel 60721a8f8a0SAnup Patelconfig RISCV_IMSIC 60821a8f8a0SAnup Patel bool 60921a8f8a0SAnup Patel depends on RISCV 61021a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 61121a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 61221a8f8a0SAnup Patel select GENERIC_MSI_IRQ 613fe35eceeSThomas Gleixner select IRQ_MSI_LIB 6145c5a71d0SAnup Patel 6158237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 616fdb1742aSConor Dooley bool 6178237f8bcSChristoph Hellwig depends on RISCV 618466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 619de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 62001493855SJonathan Neuschäfer 621e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 622e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 623e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 624e4e53503SChanghuang Liang default ARCH_STARFIVE 625e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 626e4e53503SChanghuang Liang help 627e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 628e4e53503SChanghuang Liang SoC. 629e4e53503SChanghuang Liang 630e4e53503SChanghuang Liang If you don't know what to do here, say Y. 631e4e53503SChanghuang Liang 63225caea95SInochi Amaotoconfig THEAD_C900_ACLINT_SSWI 63325caea95SInochi Amaoto bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 63425caea95SInochi Amaoto depends on RISCV 63525caea95SInochi Amaoto depends on SMP 63625caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 63725caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 63825caea95SInochi Amaoto help 63925caea95SInochi Amaoto This enables support for T-HEAD specific ACLINT SSWI device 64025caea95SInochi Amaoto support. 64125caea95SInochi Amaoto 64225caea95SInochi Amaoto If you don't know what to do here, say Y. 64325caea95SInochi Amaoto 644b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 645b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 646b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 647b74416dbSHyunki Koo help 648b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 649b74416dbSHyunki Koo in Samsung Exynos chips. 650b74416dbSHyunki Koo 651b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 652b2d3e335SHuacai Chen bool 653b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 654b2d3e335SHuacai Chen select IRQ_DOMAIN 65542a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 65670f7b6c0SHuacai Chen select LOONGSON_HTVEC 6578d5356f9SHuacai Chen select LOONGSON_LIOINTC 6588d5356f9SHuacai Chen select LOONGSON_EIOINTC 6598d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6608d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6618d5356f9SHuacai Chen select LOONGSON_PCH_LPC 662b2d3e335SHuacai Chen help 663b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 664b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 66551712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 666b2d3e335SHuacai Chen 667dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 668dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 669dbb15226SJiaxun Yang depends on MACH_LOONGSON64 670dbb15226SJiaxun Yang default y 671dbb15226SJiaxun Yang select IRQ_DOMAIN 672dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 673dbb15226SJiaxun Yang help 674dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 675dbb15226SJiaxun Yang 676dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 677dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 678dd281e1aSHuacai Chen depends on LOONGARCH 679dd281e1aSHuacai Chen depends on MACH_LOONGSON64 680dd281e1aSHuacai Chen default MACH_LOONGSON64 681dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 682dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 683dd281e1aSHuacai Chen help 684dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 685dd281e1aSHuacai Chen 686a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 687a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 688987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 689a93f1d90SJiaxun Yang default y 690a93f1d90SJiaxun Yang select IRQ_DOMAIN 691a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 692a93f1d90SJiaxun Yang help 693a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 694a93f1d90SJiaxun Yang 695818e915fSJiaxun Yangconfig LOONGSON_HTVEC 696987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 697d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 698818e915fSJiaxun Yang default MACH_LOONGSON64 699818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 700818e915fSJiaxun Yang help 701987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 702818e915fSJiaxun Yang 703ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 704ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 705bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 706ef8c01ebSJiaxun Yang default MACH_LOONGSON64 707ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 708ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 709ef8c01ebSJiaxun Yang help 710ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 711ef8c01ebSJiaxun Yang 712632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 713a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 71402308732SHuacai Chen depends on MACH_LOONGSON64 715632dcc2cSJiaxun Yang depends on PCI 716632dcc2cSJiaxun Yang default MACH_LOONGSON64 717632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7180b3af759SHuacai Chen select IRQ_MSI_LIB 719632dcc2cSJiaxun Yang select PCI_MSI 720632dcc2cSJiaxun Yang help 721632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 722632dcc2cSJiaxun Yang 723ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 724ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 725e7ccba77SJianmin Lv depends on LOONGARCH 726ee73f14eSHuacai Chen depends on MACH_LOONGSON64 727e7ccba77SJianmin Lv default MACH_LOONGSON64 728ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 729ee73f14eSHuacai Chen help 730ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 731ee73f14eSHuacai Chen 732ad4c938cSMark-PK Tsaiconfig MST_IRQ 733ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 73461b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 735ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 736ad4c938cSMark-PK Tsai select IRQ_DOMAIN 737ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 738ad4c938cSMark-PK Tsai help 739ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 740ad4c938cSMark-PK Tsai 741fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 742fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 74394bc9420SMarc Zyngier depends on ARCH_WPCM450 744fead4dd4SJonathan Neuschäfer help 745fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 746fead4dd4SJonathan Neuschäfer 747529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 748529ea368SThomas Bogendoerfer bool 749529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 750529ea368SThomas Bogendoerfer select IRQ_DOMAIN 751529ea368SThomas Bogendoerfer 75276cde263SHector Martinconfig APPLE_AIC 75376cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 75476cde263SHector Martin depends on ARM64 7555b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 756c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 75776cde263SHector Martin help 75876cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 75976cde263SHector Martin such as the M1. 76076cde263SHector Martin 76100fa3461SClaudiu Bezneaconfig MCHP_EIC 76200fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 76300fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 76400fa3461SClaudiu Beznea select IRQ_DOMAIN 76500fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 76600fa3461SClaudiu Beznea help 76700fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 76800fa3461SClaudiu Beznea 769c6674154SChen Wangconfig SOPHGO_SG2042_MSI 770c6674154SChen Wang bool "Sophgo SG2042 MSI Controller" 771c6674154SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 772c6674154SChen Wang depends on PCI 773c6674154SChen Wang select IRQ_DOMAIN_HIERARCHY 774c6674154SChen Wang select IRQ_MSI_LIB 775c6674154SChen Wang select PCI_MSI 776c6674154SChen Wang help 777c6674154SChen Wang Support for the Sophgo SG2042 MSI Controller. 778c6674154SChen Wang This on-chip interrupt controller enables MSI sources to be 779c6674154SChen Wang routed to the primary PLIC controller on SoC. 780c6674154SChen Wang 781f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 782f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 783f7189d93SQin Jian default SOC_SP7021 784f7189d93SQin Jian help 785f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 786f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 787f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 788f7189d93SQin Jian the primary controller on C-Chip. 789f7189d93SQin Jian 79001493855SJonathan Neuschäferendmenu 791