1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 31*96093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 42*96093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 4419812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4519812729SMarc Zyngier bool 4613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4748f71d56SThomas Gleixner select IRQ_MSI_LIB 4829f41139SMarc Zyngier default ARM_GIC_V3 49*96093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5029f41139SMarc Zyngier 517afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 527afe031cSBogdan Purcareata bool 537afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 547afe031cSBogdan Purcareata depends on FSL_MC_BUS 557afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata 57292ec080SUwe Kleine-Königconfig ARM_NVIC 58292ec080SUwe Kleine-König bool 592d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 60292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 61292ec080SUwe Kleine-König 6244430ec0SRob Herringconfig ARM_VIC 6344430ec0SRob Herring bool 6444430ec0SRob Herring select IRQ_DOMAIN 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC_NR 6744430ec0SRob Herring int 6844430ec0SRob Herring default 4 if ARCH_S5PV210 6944430ec0SRob Herring default 2 7044430ec0SRob Herring depends on ARM_VIC 7144430ec0SRob Herring help 7244430ec0SRob Herring The maximum number of VICs available in the system, for 7344430ec0SRob Herring power management. 7444430ec0SRob Herring 7572e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 7672e257c6SThomas Gleixner bool 7772e257c6SThomas Gleixner 78fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 79fed6d336SThomas Petazzoni bool 80fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 813ee80364SArnd Bergmann select PCI_MSI if PCI 820e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 83fed6d336SThomas Petazzoni 84e6b78f2cSAntoine Tenartconfig ALPINE_MSI 85e6b78f2cSAntoine Tenart bool 863ee80364SArnd Bergmann depends on PCI 873ee80364SArnd Bergmann select PCI_MSI 88e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 89e6b78f2cSAntoine Tenart 901eb77c3bSTalel Shenharconfig AL_FIC 911eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 929869f37aSJean Delvare depends on OF 9335e0cd77SBaoquan He depends on HAS_IOMEM 941eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 951eb77c3bSTalel Shenhar select IRQ_DOMAIN 961eb77c3bSTalel Shenhar help 971eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 981eb77c3bSTalel Shenhar 99b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 100b1479ebbSBoris BREZILLON bool 101b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 102b1479ebbSBoris BREZILLON select IRQ_DOMAIN 103b1479ebbSBoris BREZILLON select SPARSE_IRQ 104b1479ebbSBoris BREZILLON 105b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 106b1479ebbSBoris BREZILLON bool 107b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 108b1479ebbSBoris BREZILLON select IRQ_DOMAIN 109b1479ebbSBoris BREZILLON select SPARSE_IRQ 110b1479ebbSBoris BREZILLON 1110509cfdeSRalf Baechleconfig I8259 1120509cfdeSRalf Baechle bool 1130509cfdeSRalf Baechle select IRQ_DOMAIN 1140509cfdeSRalf Baechle 115c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 116c7c42ec2SSimon Arlott bool 117c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 118c7c42ec2SSimon Arlott select IRQ_DOMAIN 1190e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 120c7c42ec2SSimon Arlott 1215f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 122c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 123c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 124c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1255f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1265f7f0317SKevin Cernekee select IRQ_DOMAIN 1270e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1285f7f0317SKevin Cernekee 129a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1303ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1313ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1323ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 133a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 134a4fcbb86SKevin Cernekee select IRQ_DOMAIN 135a4fcbb86SKevin Cernekee 1367f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 13751d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 13851d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 13951d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1407f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1417f646e92SFlorian Fainelli select IRQ_DOMAIN 1427f646e92SFlorian Fainelli 1430fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1440fc3d74cSBartosz Golaszewski bool 1450fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1460fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1470fc3d74cSBartosz Golaszewski 148350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 149be5e5f3aSThomas Gleixner bool 150e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15154a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 152350d71b9SSebastian Hesselbarth 1536ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1546ee532e2SLinus Walleij bool 1556ee532e2SLinus Walleij select IRQ_DOMAIN 1566ee532e2SLinus Walleij select SPARSE_IRQ 1576ee532e2SLinus Walleij 1589a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1599a7c4abdSMaJun bool 1609a7c4abdSMaJun select ARM_GIC_V3 1619a7c4abdSMaJun select ARM_GIC_V3_ITS 1629a7c4abdSMaJun 163b6ef9161SJames Hoganconfig IMGPDC_IRQ 164b6ef9161SJames Hogan bool 165b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 166b6ef9161SJames Hogan select IRQ_DOMAIN 167b6ef9161SJames Hogan 1685b978c10SLinus Walleijconfig IXP4XX_IRQ 1695b978c10SLinus Walleij bool 1705b978c10SLinus Walleij select IRQ_DOMAIN 1715b978c10SLinus Walleij select SPARSE_IRQ 1725b978c10SLinus Walleij 1733e3a7b35SHerve Codinaconfig LAN966X_OIC 1743e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 175e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 1763e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 1773e3a7b35SHerve Codina select IRQ_DOMAIN 1783e3a7b35SHerve Codina help 1793e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 1803e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 1813e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 1823e3a7b35SHerve Codina 1833e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 1843e3a7b35SHerve Codina will be called irq-lan966x-oic. 1853e3a7b35SHerve Codina 186da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 187da0abe1aSRichard Fitzgerald tristate 188da0abe1aSRichard Fitzgerald 18967e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 19067e38cf2SRalf Baechle bool 19167e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1920f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 19367e38cf2SRalf Baechle select IRQ_DOMAIN 1940e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 19567e38cf2SRalf Baechle 196afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 197afc98d90SAlexander Shiyan bool 198afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 199afc98d90SAlexander Shiyan select IRQ_DOMAIN 200afc98d90SAlexander Shiyan select SPARSE_IRQ 201afc98d90SAlexander Shiyan default y 202afc98d90SAlexander Shiyan 2039b54470aSStafford Horneconfig OMPIC 2049b54470aSStafford Horne bool 2059b54470aSStafford Horne 2064db8e6d2SStefan Kristianssonconfig OR1K_PIC 2074db8e6d2SStefan Kristiansson bool 2084db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2094db8e6d2SStefan Kristiansson 2108598066cSFelipe Balbiconfig OMAP_IRQCHIP 2118598066cSFelipe Balbi bool 2128598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2138598066cSFelipe Balbi select IRQ_DOMAIN 2148598066cSFelipe Balbi 2159dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2169dbd90f1SSebastian Hesselbarth bool 2179dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2189dbd90f1SSebastian Hesselbarth 219aaa8666aSCristian Birsanconfig PIC32_EVIC 220aaa8666aSCristian Birsan bool 221aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 222aaa8666aSCristian Birsan select IRQ_DOMAIN 223aaa8666aSCristian Birsan 224981b58f6SRich Felkerconfig JCORE_AIC 2253602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2263602ffdeSRich Felker depends on OF 227981b58f6SRich Felker select IRQ_DOMAIN 228981b58f6SRich Felker help 229981b58f6SRich Felker Support for the J-Core integrated AIC. 230981b58f6SRich Felker 231d852e62aSManivannan Sadhasivamconfig RDA_INTC 232d852e62aSManivannan Sadhasivam bool 233d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 234d852e62aSManivannan Sadhasivam 23544358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 23602d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 23744358048SMagnus Damm select IRQ_DOMAIN 23802d7e041SGeert Uytterhoeven help 23902d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 24002d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 24144358048SMagnus Damm 242fbc83b7fSMagnus Dammconfig RENESAS_IRQC 24372d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 24499c221dfSMagnus Damm select GENERIC_IRQ_CHIP 245fbc83b7fSMagnus Damm select IRQ_DOMAIN 24602d7e041SGeert Uytterhoeven help 24702d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 24872d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 249fbc83b7fSMagnus Damm 250a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 25102d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 252a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 25302d7e041SGeert Uytterhoeven help 25402d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 25502d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 256a644ccb8SGeert Uytterhoeven 2573fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2583fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2593fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2603fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2613fed0955SLad Prabhakar help 2623fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2633fed0955SLad Prabhakar for external devices. 2643fed0955SLad Prabhakar 2650d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2660d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 2670d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 2680d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 2690d7605e7SFabrizio Castro help 2700d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 2710d7605e7SFabrizio Castro 27203ac990eSMichael Walleconfig SL28CPLD_INTC 27303ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 27403ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 27503ac990eSMichael Walle select REGMAP_IRQ 27603ac990eSMichael Walle help 27703ac990eSMichael Walle Interrupt controller driver for the board management controller 27803ac990eSMichael Walle found on the Kontron sl28 CPLD. 27903ac990eSMichael Walle 28007088484SLee Jonesconfig ST_IRQCHIP 28107088484SLee Jones bool 28207088484SLee Jones select REGMAP 28307088484SLee Jones select MFD_SYSCON 28407088484SLee Jones help 28507088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 28607088484SLee Jones 287d421fd6dSSamuel Hollandconfig SUN4I_INTC 288d421fd6dSSamuel Holland bool 289d421fd6dSSamuel Holland 290d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 291d421fd6dSSamuel Holland bool 292d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 293d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 294d421fd6dSSamuel Holland 295d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 296d421fd6dSSamuel Holland bool 297d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 298d421fd6dSSamuel Holland 299b06eb017SChristian Ruppertconfig TB10X_IRQC 300b06eb017SChristian Ruppert bool 301b06eb017SChristian Ruppert select IRQ_DOMAIN 302b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 303b06eb017SChristian Ruppert 304d01f8633SDamien Riegelconfig TS4800_IRQ 305d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 306d01f8633SDamien Riegel select IRQ_DOMAIN 3070df337cfSRichard Weinberger depends on HAS_IOMEM 308d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 309d01f8633SDamien Riegel help 310d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 311d01f8633SDamien Riegel 3122389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3132389d501SLinus Walleij bool 3142389d501SLinus Walleij select IRQ_DOMAIN 3152389d501SLinus Walleij 3162389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3172389d501SLinus Walleij int 3182389d501SLinus Walleij default 4 3192389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 32026a8e96aSMax Filippov 32126a8e96aSMax Filippovconfig XTENSA_MX 32226a8e96aSMax Filippov bool 32326a8e96aSMax Filippov select IRQ_DOMAIN 3240e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 32596ca848eSSricharan R 3260547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 327debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 328fd31000dSJamie Iles depends on OF_ADDRESS 3290547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 330debf69cfSRobert Hancock help 331debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 332debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 333debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3340547dc78SZubair Lutfullah Kakakhel 33596ca848eSSricharan Rconfig IRQ_CROSSBAR 33696ca848eSSricharan R bool 33796ca848eSSricharan R help 338f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 33996ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 34096ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 34196ca848eSSricharan R routed to one of the free irqchip interrupt lines. 34289323f8cSGrygorii Strashko 34389323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 34489323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 34589323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 34689323f8cSGrygorii Strashko help 34789323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 34889323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3498a19b8f1SAndrew Bresticker 3508a19b8f1SAndrew Brestickerconfig MIPS_GIC 3518a19b8f1SAndrew Bresticker bool 3520053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3538190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3548190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3558a19b8f1SAndrew Bresticker select MIPS_CM 3568a764482SYoshinori Sato 35744e08e70SPaul Burtonconfig INGENIC_IRQ 35844e08e70SPaul Burton bool 35944e08e70SPaul Burton depends on MACH_INGENIC 36044e08e70SPaul Burton default y 36178c10e55SLinus Torvalds 3629536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3639536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3649536eba0SPaul Cercueil default MACH_INGENIC 3659536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3669536eba0SPaul Cercueil select MFD_SYSCON 3678084499bSYueHaibing select GENERIC_IRQ_CHIP 3689536eba0SPaul Cercueil help 3699536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3709536eba0SPaul Cercueil JZ47xx SoCs. 3719536eba0SPaul Cercueil 3729536eba0SPaul Cercueil If unsure, say N. 3739536eba0SPaul Cercueil 374e324c4dcSShenwei Wangconfig IMX_GPCV2 375e324c4dcSShenwei Wang bool 376e324c4dcSShenwei Wang select IRQ_DOMAIN 377e324c4dcSShenwei Wang help 378e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3797e4ac676SOleksij Rempel 3807e4ac676SOleksij Rempelconfig IRQ_MXS 3817e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3827e4ac676SOleksij Rempel select IRQ_DOMAIN 3837e4ac676SOleksij Rempel select STMP_DEVICE 384c27f29bbSThomas Petazzoni 38519d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 38619d99164SAlexandre Belloni bool 38719d99164SAlexandre Belloni select IRQ_DOMAIN 38819d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 38919d99164SAlexandre Belloni 390a68a63cbSThomas Petazzoniconfig MVEBU_GICP 391cdb23872SThomas Gleixner select IRQ_MSI_LIB 392a68a63cbSThomas Petazzoni bool 393a68a63cbSThomas Petazzoni 394e0de91a9SThomas Petazzoniconfig MVEBU_ICU 395e0de91a9SThomas Petazzoni bool 396e0de91a9SThomas Petazzoni 397c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 398c27f29bbSThomas Petazzoni bool 399e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 40013e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4019e2c986cSMarc Zyngier 402a109893bSThomas Petazzoniconfig MVEBU_PIC 403a109893bSThomas Petazzoni bool 404a109893bSThomas Petazzoni 40561ce8d8dSMiquel Raynalconfig MVEBU_SEI 40661ce8d8dSMiquel Raynal bool 40761ce8d8dSMiquel Raynal 4080dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4090dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4100dcd9f87SRasmus Villemoes select MFD_SYSCON 4110dcd9f87SRasmus Villemoes 412b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 413b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 414*96093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4159c1a7bfcSLukas Bulwahn depends on PCI_MSI 416b8f3ebe6SMinghuan Lian 4179e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4189e2c986cSMarc Zyngier bool 4190efacbbaSLinus Torvalds 420b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4210be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4220be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4239151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4240be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 425350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4260be58e05SAntonio Borneo help 4270be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 428b20cf2dcSAntonio Borneo 429e0720416SAlexandre TORGUEconfig STM32_EXTI 430e0720416SAlexandre TORGUE bool 431e0720416SAlexandre TORGUE select IRQ_DOMAIN 4320e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 433f20cc9b0SAgustin Vega-Frias 434f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 435f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 436f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 437f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 438f20cc9b0SAgustin Vega-Frias help 439f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 440f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4415ed34d3aSMasahiro Yamada 4425ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4435ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4445ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4455ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4465ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4475ed34d3aSMasahiro Yamada help 4485ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 449c94fb639SRandy Dunlap 450215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 451a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 452a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 453a947aa00SNeil Armstrong default ARCH_MESON 454215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 455215f4cc0SJerome Brunet help 456215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 457215f4cc0SJerome Brunet 4584235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4594235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4604235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 461969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4624235ff50SMiodrag Dinic select IRQ_DOMAIN 4634235ff50SMiodrag Dinic help 4644235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4654235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4664235ff50SMiodrag Dinic 467f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4684acd8a4bSSaravana Kannan tristate "QCOM PDC" 469f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 470f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 471f55c73aeSArchana Sathyakumar help 472f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 473f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 474f55c73aeSArchana Sathyakumar 475a6199bb5SShawn Guoconfig QCOM_MPM 476a6199bb5SShawn Guo tristate "QCOM MPM" 477a6199bb5SShawn Guo depends on ARCH_QCOM 478fa4dcc88SYueHaibing depends on MAILBOX 479a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 480a6199bb5SShawn Guo help 481a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 482a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 483a6199bb5SShawn Guo 484d8a5f5f7SGuo Renconfig CSKY_MPINTC 485be1abc5bSGuo Ren bool 486d8a5f5f7SGuo Ren depends on CSKY 487d8a5f5f7SGuo Ren help 488d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 489d8a5f5f7SGuo Ren for C-SKY SMP system. 490656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 491d8a5f5f7SGuo Ren controller's register inside CPU. 492d8a5f5f7SGuo Ren 493edff1b48SGuo Renconfig CSKY_APB_INTC 494edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 495edff1b48SGuo Ren depends on CSKY 496edff1b48SGuo Ren help 497edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 498656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 499edff1b48SGuo Ren the controller's register. 500edff1b48SGuo Ren 5010136afa0SLucas Stachconfig IMX_IRQSTEER 5020136afa0SLucas Stach bool "i.MX IRQSTEER support" 5030136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5040136afa0SLucas Stach default ARCH_MXC 5050136afa0SLucas Stach select IRQ_DOMAIN 5060136afa0SLucas Stach help 5070136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5080136afa0SLucas Stach 5092fbb1396SJoakim Zhangconfig IMX_INTMUX 510a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 511a890caebSGeert Uytterhoeven default y if ARCH_MXC 5122fbb1396SJoakim Zhang select IRQ_DOMAIN 5132fbb1396SJoakim Zhang help 5142fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5152fbb1396SJoakim Zhang 51670afdab9SFrank Liconfig IMX_MU_MSI 51770afdab9SFrank Li tristate "i.MX MU used as MSI controller" 51870afdab9SFrank Li depends on OF && HAS_IOMEM 5196c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 52070afdab9SFrank Li default m if ARCH_MXC 52170afdab9SFrank Li select IRQ_DOMAIN 52270afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 52313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5247b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 52570afdab9SFrank Li help 5266c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5276c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5286c9f7434SGeert Uytterhoeven to make use of this driver. 52970afdab9SFrank Li 53070afdab9SFrank Li If unsure, say N 53170afdab9SFrank Li 5329e543e22SJiaxun Yangconfig LS1X_IRQ 5339e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5349e543e22SJiaxun Yang depends on MACH_LOONGSON32 5359e543e22SJiaxun Yang default y 5369e543e22SJiaxun Yang select IRQ_DOMAIN 5379e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5389e543e22SJiaxun Yang help 5399e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5409e543e22SJiaxun Yang 541cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5422d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 543cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5442d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 545cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 546cd844b07SLokesh Vutla help 547cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 548cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 549cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 550cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 551cd844b07SLokesh Vutla 5529f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 553b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5549f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 555b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5569f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 557f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5589f1463b8SLokesh Vutla help 5599f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5609f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5619f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5629f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5639f1463b8SLokesh Vutla 56404e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 565b8e594faSSuman Anna tristate 566b8e594faSSuman Anna depends on TI_PRUSS 567b8e594faSSuman Anna default TI_PRUSS 56804e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 56904e2d1e0SGrzegorz Jaszczyk help 57004e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 57104e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 57204e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 57304e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 57404e2d1e0SGrzegorz Jaszczyk 5756b7ce892SAnup Patelconfig RISCV_INTC 576d8fb1307SConor Dooley bool 5776b7ce892SAnup Patel depends on RISCV 578832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5796b7ce892SAnup Patel 5802333df5aSAnup Patelconfig RISCV_APLIC 5812333df5aSAnup Patel bool 5822333df5aSAnup Patel depends on RISCV 5832333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 5842333df5aSAnup Patel 585ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 586ca8df97fSAnup Patel bool 587ca8df97fSAnup Patel depends on RISCV_APLIC 588ca8df97fSAnup Patel select GENERIC_MSI_IRQ 589ca8df97fSAnup Patel default RISCV_APLIC 590ca8df97fSAnup Patel 59121a8f8a0SAnup Patelconfig RISCV_IMSIC 59221a8f8a0SAnup Patel bool 59321a8f8a0SAnup Patel depends on RISCV 59421a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 59521a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 59621a8f8a0SAnup Patel select GENERIC_MSI_IRQ 59721a8f8a0SAnup Patel 5985c5a71d0SAnup Patelconfig RISCV_IMSIC_PCI 5995c5a71d0SAnup Patel bool 6005c5a71d0SAnup Patel depends on RISCV_IMSIC 6015c5a71d0SAnup Patel depends on PCI 6025c5a71d0SAnup Patel depends on PCI_MSI 6035c5a71d0SAnup Patel default RISCV_IMSIC 6045c5a71d0SAnup Patel 6058237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 606fdb1742aSConor Dooley bool 6078237f8bcSChristoph Hellwig depends on RISCV 608466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 609de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 61001493855SJonathan Neuschäfer 611e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 612e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 613e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 614e4e53503SChanghuang Liang default ARCH_STARFIVE 615e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 616e4e53503SChanghuang Liang help 617e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 618e4e53503SChanghuang Liang SoC. 619e4e53503SChanghuang Liang 620e4e53503SChanghuang Liang If you don't know what to do here, say Y. 621e4e53503SChanghuang Liang 62225caea95SInochi Amaotoconfig THEAD_C900_ACLINT_SSWI 62325caea95SInochi Amaoto bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 62425caea95SInochi Amaoto depends on RISCV 62525caea95SInochi Amaoto depends on SMP 62625caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 62725caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 62825caea95SInochi Amaoto help 62925caea95SInochi Amaoto This enables support for T-HEAD specific ACLINT SSWI device 63025caea95SInochi Amaoto support. 63125caea95SInochi Amaoto 63225caea95SInochi Amaoto If you don't know what to do here, say Y. 63325caea95SInochi Amaoto 634b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 635b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 636b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 637b74416dbSHyunki Koo help 638b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 639b74416dbSHyunki Koo in Samsung Exynos chips. 640b74416dbSHyunki Koo 641b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 642b2d3e335SHuacai Chen bool 643b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 644b2d3e335SHuacai Chen select IRQ_DOMAIN 64542a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 64670f7b6c0SHuacai Chen select LOONGSON_HTVEC 6478d5356f9SHuacai Chen select LOONGSON_LIOINTC 6488d5356f9SHuacai Chen select LOONGSON_EIOINTC 6498d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6508d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6518d5356f9SHuacai Chen select LOONGSON_PCH_LPC 652b2d3e335SHuacai Chen help 653b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 654b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 65551712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 656b2d3e335SHuacai Chen 657dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 658dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 659dbb15226SJiaxun Yang depends on MACH_LOONGSON64 660dbb15226SJiaxun Yang default y 661dbb15226SJiaxun Yang select IRQ_DOMAIN 662dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 663dbb15226SJiaxun Yang help 664dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 665dbb15226SJiaxun Yang 666dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 667dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 668dd281e1aSHuacai Chen depends on LOONGARCH 669dd281e1aSHuacai Chen depends on MACH_LOONGSON64 670dd281e1aSHuacai Chen default MACH_LOONGSON64 671dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 672dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 673dd281e1aSHuacai Chen help 674dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 675dd281e1aSHuacai Chen 676a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 677a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 678987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 679a93f1d90SJiaxun Yang default y 680a93f1d90SJiaxun Yang select IRQ_DOMAIN 681a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 682a93f1d90SJiaxun Yang help 683a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 684a93f1d90SJiaxun Yang 685818e915fSJiaxun Yangconfig LOONGSON_HTVEC 686987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 687d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 688818e915fSJiaxun Yang default MACH_LOONGSON64 689818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 690818e915fSJiaxun Yang help 691987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 692818e915fSJiaxun Yang 693ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 694ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 695bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 696ef8c01ebSJiaxun Yang default MACH_LOONGSON64 697ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 698ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 699ef8c01ebSJiaxun Yang help 700ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 701ef8c01ebSJiaxun Yang 702632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 703a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 70402308732SHuacai Chen depends on MACH_LOONGSON64 705632dcc2cSJiaxun Yang depends on PCI 706632dcc2cSJiaxun Yang default MACH_LOONGSON64 707632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7080b3af759SHuacai Chen select IRQ_MSI_LIB 709632dcc2cSJiaxun Yang select PCI_MSI 710632dcc2cSJiaxun Yang help 711632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 712632dcc2cSJiaxun Yang 713ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 714ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 715e7ccba77SJianmin Lv depends on LOONGARCH 716ee73f14eSHuacai Chen depends on MACH_LOONGSON64 717e7ccba77SJianmin Lv default MACH_LOONGSON64 718ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 719ee73f14eSHuacai Chen help 720ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 721ee73f14eSHuacai Chen 722ad4c938cSMark-PK Tsaiconfig MST_IRQ 723ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 72461b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 725ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 726ad4c938cSMark-PK Tsai select IRQ_DOMAIN 727ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 728ad4c938cSMark-PK Tsai help 729ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 730ad4c938cSMark-PK Tsai 731fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 732fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 73394bc9420SMarc Zyngier depends on ARCH_WPCM450 734fead4dd4SJonathan Neuschäfer help 735fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 736fead4dd4SJonathan Neuschäfer 737529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 738529ea368SThomas Bogendoerfer bool 739529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 740529ea368SThomas Bogendoerfer select IRQ_DOMAIN 741529ea368SThomas Bogendoerfer 74276cde263SHector Martinconfig APPLE_AIC 74376cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 74476cde263SHector Martin depends on ARM64 7455b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 746c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 74776cde263SHector Martin help 74876cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 74976cde263SHector Martin such as the M1. 75076cde263SHector Martin 75100fa3461SClaudiu Bezneaconfig MCHP_EIC 75200fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 75300fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 75400fa3461SClaudiu Beznea select IRQ_DOMAIN 75500fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 75600fa3461SClaudiu Beznea help 75700fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 75800fa3461SClaudiu Beznea 759f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 760f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 761f7189d93SQin Jian default SOC_SP7021 762f7189d93SQin Jian help 763f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 764f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 765f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 766f7189d93SQin Jian the primary controller on C-Chip. 767f7189d93SQin Jian 76801493855SJonathan Neuschäferendmenu 769