1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 3196093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 4296093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 4419812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4519812729SMarc Zyngier bool 4613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4748f71d56SThomas Gleixner select IRQ_MSI_LIB 4829f41139SMarc Zyngier default ARM_GIC_V3 4996093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5029f41139SMarc Zyngier 517afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 527afe031cSBogdan Purcareata bool 537afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 547afe031cSBogdan Purcareata depends on FSL_MC_BUS 557afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata 57292ec080SUwe Kleine-Königconfig ARM_NVIC 58292ec080SUwe Kleine-König bool 592d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 60292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 61292ec080SUwe Kleine-König 6244430ec0SRob Herringconfig ARM_VIC 6344430ec0SRob Herring bool 6444430ec0SRob Herring select IRQ_DOMAIN 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC_NR 6744430ec0SRob Herring int 6844430ec0SRob Herring default 4 if ARCH_S5PV210 6944430ec0SRob Herring default 2 7044430ec0SRob Herring depends on ARM_VIC 7144430ec0SRob Herring help 7244430ec0SRob Herring The maximum number of VICs available in the system, for 7344430ec0SRob Herring power management. 7444430ec0SRob Herring 7572e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 7672e257c6SThomas Gleixner bool 7772e257c6SThomas Gleixner 78fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 79fed6d336SThomas Petazzoni bool 80fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 813ee80364SArnd Bergmann select PCI_MSI if PCI 82bafb2901SNam Cao select IRQ_MSI_LIB if PCI 830e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 84fed6d336SThomas Petazzoni 85e6b78f2cSAntoine Tenartconfig ALPINE_MSI 86e6b78f2cSAntoine Tenart bool 873ee80364SArnd Bergmann depends on PCI 883ee80364SArnd Bergmann select PCI_MSI 897a91ad7eSThomas Gleixner select IRQ_MSI_LIB 90e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 91e6b78f2cSAntoine Tenart 921eb77c3bSTalel Shenharconfig AL_FIC 931eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 949869f37aSJean Delvare depends on OF 9535e0cd77SBaoquan He depends on HAS_IOMEM 961eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 971eb77c3bSTalel Shenhar select IRQ_DOMAIN 981eb77c3bSTalel Shenhar help 991eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1001eb77c3bSTalel Shenhar 101b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 102b1479ebbSBoris BREZILLON bool 103b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 104b1479ebbSBoris BREZILLON select IRQ_DOMAIN 105b1479ebbSBoris BREZILLON select SPARSE_IRQ 106b1479ebbSBoris BREZILLON 107b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 108b1479ebbSBoris BREZILLON bool 109b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 110b1479ebbSBoris BREZILLON select IRQ_DOMAIN 111b1479ebbSBoris BREZILLON select SPARSE_IRQ 112b1479ebbSBoris BREZILLON 1130509cfdeSRalf Baechleconfig I8259 1140509cfdeSRalf Baechle bool 1150509cfdeSRalf Baechle select IRQ_DOMAIN 1160509cfdeSRalf Baechle 11732c6c054SStanimir Varbanovconfig BCM2712_MIP 11832c6c054SStanimir Varbanov tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 1199b3ae50cSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 1209b3ae50cSPeter Robinson default m if ARCH_BRCMSTB || ARCH_BCM2835 12132c6c054SStanimir Varbanov depends on ARM_GIC 12232c6c054SStanimir Varbanov select GENERIC_IRQ_CHIP 12332c6c054SStanimir Varbanov select IRQ_DOMAIN_HIERARCHY 12432c6c054SStanimir Varbanov select GENERIC_MSI_IRQ 12532c6c054SStanimir Varbanov select IRQ_MSI_LIB 12632c6c054SStanimir Varbanov help 12732c6c054SStanimir Varbanov Enable support for the Broadcom BCM2712 MSI-X target peripheral 12832c6c054SStanimir Varbanov (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 12932c6c054SStanimir Varbanov Raspberry Pi 5. 13032c6c054SStanimir Varbanov 13132c6c054SStanimir Varbanov If unsure say n. 13232c6c054SStanimir Varbanov 133c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 134c7c42ec2SSimon Arlott bool 135c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 136c7c42ec2SSimon Arlott select IRQ_DOMAIN 1370e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 138c7c42ec2SSimon Arlott 1395f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 140c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 141c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 142c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1435f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1445f7f0317SKevin Cernekee select IRQ_DOMAIN 1450e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1465f7f0317SKevin Cernekee 147a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1483ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1493ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1503ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 151a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 152a4fcbb86SKevin Cernekee select IRQ_DOMAIN 153a4fcbb86SKevin Cernekee 1547f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 15551d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 15651d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 15751d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1587f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1597f646e92SFlorian Fainelli select IRQ_DOMAIN 1607f646e92SFlorian Fainelli 1610fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1620fc3d74cSBartosz Golaszewski bool 1630fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1640fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1650fc3d74cSBartosz Golaszewski 166350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 167be5e5f3aSThomas Gleixner bool 168e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 16954a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 170350d71b9SSebastian Hesselbarth 1711902a59cSCaleb James DeLisleconfig ECONET_EN751221_INTC 1721902a59cSCaleb James DeLisle bool 1731902a59cSCaleb James DeLisle select GENERIC_IRQ_CHIP 1741902a59cSCaleb James DeLisle select IRQ_DOMAIN 1751902a59cSCaleb James DeLisle 1766ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1776ee532e2SLinus Walleij bool 1786ee532e2SLinus Walleij select IRQ_DOMAIN 1796ee532e2SLinus Walleij select SPARSE_IRQ 1806ee532e2SLinus Walleij 1819a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1829a7c4abdSMaJun bool 1839a7c4abdSMaJun select ARM_GIC_V3 1849a7c4abdSMaJun select ARM_GIC_V3_ITS 1859a7c4abdSMaJun 186b6ef9161SJames Hoganconfig IMGPDC_IRQ 187b6ef9161SJames Hogan bool 188b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 189b6ef9161SJames Hogan select IRQ_DOMAIN 190b6ef9161SJames Hogan 1915b978c10SLinus Walleijconfig IXP4XX_IRQ 1925b978c10SLinus Walleij bool 1935b978c10SLinus Walleij select IRQ_DOMAIN 1945b978c10SLinus Walleij select SPARSE_IRQ 1955b978c10SLinus Walleij 1963e3a7b35SHerve Codinaconfig LAN966X_OIC 1973e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 198e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 1993e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 2003e3a7b35SHerve Codina select IRQ_DOMAIN 2013e3a7b35SHerve Codina help 2023e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 2033e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 2043e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 2053e3a7b35SHerve Codina 2063e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 2073e3a7b35SHerve Codina will be called irq-lan966x-oic. 2083e3a7b35SHerve Codina 209da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 210da0abe1aSRichard Fitzgerald tristate 211da0abe1aSRichard Fitzgerald 21267e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 21367e38cf2SRalf Baechle bool 21467e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 2150f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 21667e38cf2SRalf Baechle select IRQ_DOMAIN 2170e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 21867e38cf2SRalf Baechle 219afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 220afc98d90SAlexander Shiyan bool 221afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 222afc98d90SAlexander Shiyan select IRQ_DOMAIN 223afc98d90SAlexander Shiyan select SPARSE_IRQ 224afc98d90SAlexander Shiyan default y 225afc98d90SAlexander Shiyan 2269b54470aSStafford Horneconfig OMPIC 2279b54470aSStafford Horne bool 2289b54470aSStafford Horne 2294db8e6d2SStefan Kristianssonconfig OR1K_PIC 2304db8e6d2SStefan Kristiansson bool 2314db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2324db8e6d2SStefan Kristiansson 2338598066cSFelipe Balbiconfig OMAP_IRQCHIP 2348598066cSFelipe Balbi bool 2358598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2368598066cSFelipe Balbi select IRQ_DOMAIN 2378598066cSFelipe Balbi 2389dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2399dbd90f1SSebastian Hesselbarth bool 2409dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2419dbd90f1SSebastian Hesselbarth 242aaa8666aSCristian Birsanconfig PIC32_EVIC 243aaa8666aSCristian Birsan bool 244aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 245aaa8666aSCristian Birsan select IRQ_DOMAIN 246aaa8666aSCristian Birsan 247981b58f6SRich Felkerconfig JCORE_AIC 2483602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2493602ffdeSRich Felker depends on OF 250981b58f6SRich Felker select IRQ_DOMAIN 251981b58f6SRich Felker help 252981b58f6SRich Felker Support for the J-Core integrated AIC. 253981b58f6SRich Felker 254d852e62aSManivannan Sadhasivamconfig RDA_INTC 255d852e62aSManivannan Sadhasivam bool 256d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 257d852e62aSManivannan Sadhasivam 25844358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 25902d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 26044358048SMagnus Damm select IRQ_DOMAIN 26102d7e041SGeert Uytterhoeven help 26202d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 26302d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 26444358048SMagnus Damm 265fbc83b7fSMagnus Dammconfig RENESAS_IRQC 26672d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 26799c221dfSMagnus Damm select GENERIC_IRQ_CHIP 268fbc83b7fSMagnus Damm select IRQ_DOMAIN 26902d7e041SGeert Uytterhoeven help 27002d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 27172d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 272fbc83b7fSMagnus Damm 273a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 27402d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 275a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 27602d7e041SGeert Uytterhoeven help 27702d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 27802d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 279a644ccb8SGeert Uytterhoeven 2803fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2813fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2823fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2833fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2843fed0955SLad Prabhakar help 2853fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2863fed0955SLad Prabhakar for external devices. 2873fed0955SLad Prabhakar 2880d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2890d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 2900d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 2910d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 2920d7605e7SFabrizio Castro help 2930d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 2940d7605e7SFabrizio Castro 29503ac990eSMichael Walleconfig SL28CPLD_INTC 29603ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 29703ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 29803ac990eSMichael Walle select REGMAP_IRQ 29903ac990eSMichael Walle help 30003ac990eSMichael Walle Interrupt controller driver for the board management controller 30103ac990eSMichael Walle found on the Kontron sl28 CPLD. 30203ac990eSMichael Walle 30307088484SLee Jonesconfig ST_IRQCHIP 30407088484SLee Jones bool 30507088484SLee Jones select REGMAP 30607088484SLee Jones select MFD_SYSCON 30707088484SLee Jones help 30807088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 30907088484SLee Jones 310d421fd6dSSamuel Hollandconfig SUN4I_INTC 311d421fd6dSSamuel Holland bool 312d421fd6dSSamuel Holland 313d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 314d421fd6dSSamuel Holland bool 315d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 316d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 317d421fd6dSSamuel Holland 318d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 319d421fd6dSSamuel Holland bool 320d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 321d421fd6dSSamuel Holland 322b06eb017SChristian Ruppertconfig TB10X_IRQC 323b06eb017SChristian Ruppert bool 324b06eb017SChristian Ruppert select IRQ_DOMAIN 325b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 326b06eb017SChristian Ruppert 327d01f8633SDamien Riegelconfig TS4800_IRQ 328d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 329d01f8633SDamien Riegel select IRQ_DOMAIN 3300df337cfSRichard Weinberger depends on HAS_IOMEM 331d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 332d01f8633SDamien Riegel help 333d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 334d01f8633SDamien Riegel 3352389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3362389d501SLinus Walleij bool 3372389d501SLinus Walleij select IRQ_DOMAIN 3382389d501SLinus Walleij 3392389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3402389d501SLinus Walleij int 3412389d501SLinus Walleij default 4 3422389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 34326a8e96aSMax Filippov 34426a8e96aSMax Filippovconfig XTENSA_MX 34526a8e96aSMax Filippov bool 34626a8e96aSMax Filippov select IRQ_DOMAIN 3470e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 34896ca848eSSricharan R 3490547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 350debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 351fd31000dSJamie Iles depends on OF_ADDRESS 3520547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 353debf69cfSRobert Hancock help 354debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 355debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 356debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3570547dc78SZubair Lutfullah Kakakhel 35896ca848eSSricharan Rconfig IRQ_CROSSBAR 35996ca848eSSricharan R bool 36096ca848eSSricharan R help 361f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 36296ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 36396ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 36496ca848eSSricharan R routed to one of the free irqchip interrupt lines. 36589323f8cSGrygorii Strashko 36689323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 36789323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 36889323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 36989323f8cSGrygorii Strashko help 37089323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 37189323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3728a19b8f1SAndrew Bresticker 3738a19b8f1SAndrew Brestickerconfig MIPS_GIC 3748a19b8f1SAndrew Bresticker bool 3750053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3768190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3778190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3788a19b8f1SAndrew Bresticker select MIPS_CM 3798a764482SYoshinori Sato 38044e08e70SPaul Burtonconfig INGENIC_IRQ 38144e08e70SPaul Burton bool 38244e08e70SPaul Burton depends on MACH_INGENIC 38344e08e70SPaul Burton default y 38478c10e55SLinus Torvalds 3859536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3869536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3879536eba0SPaul Cercueil default MACH_INGENIC 3889536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3899536eba0SPaul Cercueil select MFD_SYSCON 3908084499bSYueHaibing select GENERIC_IRQ_CHIP 3919536eba0SPaul Cercueil help 3929536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3939536eba0SPaul Cercueil JZ47xx SoCs. 3949536eba0SPaul Cercueil 3959536eba0SPaul Cercueil If unsure, say N. 3969536eba0SPaul Cercueil 397e324c4dcSShenwei Wangconfig IMX_GPCV2 398e324c4dcSShenwei Wang bool 399e324c4dcSShenwei Wang select IRQ_DOMAIN 400e324c4dcSShenwei Wang help 401e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 4027e4ac676SOleksij Rempel 4037e4ac676SOleksij Rempelconfig IRQ_MXS 4047e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 4057e4ac676SOleksij Rempel select IRQ_DOMAIN 4067e4ac676SOleksij Rempel select STMP_DEVICE 407c27f29bbSThomas Petazzoni 40819d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 40919d99164SAlexandre Belloni bool 41019d99164SAlexandre Belloni select IRQ_DOMAIN 41119d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 41219d99164SAlexandre Belloni 413a68a63cbSThomas Petazzoniconfig MVEBU_GICP 414cdb23872SThomas Gleixner select IRQ_MSI_LIB 415a68a63cbSThomas Petazzoni bool 416a68a63cbSThomas Petazzoni 417e0de91a9SThomas Petazzoniconfig MVEBU_ICU 418e0de91a9SThomas Petazzoni bool 419e0de91a9SThomas Petazzoni 420c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 421c27f29bbSThomas Petazzoni bool 422e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 42313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4249e2c986cSMarc Zyngier 425a109893bSThomas Petazzoniconfig MVEBU_PIC 426a109893bSThomas Petazzoni bool 427a109893bSThomas Petazzoni 42861ce8d8dSMiquel Raynalconfig MVEBU_SEI 42961ce8d8dSMiquel Raynal bool 43061ce8d8dSMiquel Raynal 4310dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4320dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4330dcd9f87SRasmus Villemoes select MFD_SYSCON 4340dcd9f87SRasmus Villemoes 435b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 436b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 43796093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4389c1a7bfcSLukas Bulwahn depends on PCI_MSI 439*94b59d5fSNam Cao select IRQ_MSI_LIB 440b8f3ebe6SMinghuan Lian 4419e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4429e2c986cSMarc Zyngier bool 4430efacbbaSLinus Torvalds 444b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4450be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4460be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4479151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4480be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 449350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4500be58e05SAntonio Borneo help 4510be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 452b20cf2dcSAntonio Borneo 453e0720416SAlexandre TORGUEconfig STM32_EXTI 454e0720416SAlexandre TORGUE bool 455e0720416SAlexandre TORGUE select IRQ_DOMAIN 4560e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 457f20cc9b0SAgustin Vega-Frias 458f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 459f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 460f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 461f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 462f20cc9b0SAgustin Vega-Frias help 463f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 464f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4655ed34d3aSMasahiro Yamada 4665ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4675ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4685ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4695ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4705ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4715ed34d3aSMasahiro Yamada help 4725ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 473c94fb639SRandy Dunlap 474215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 475a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 476a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 477a947aa00SNeil Armstrong default ARCH_MESON 478215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 479215f4cc0SJerome Brunet help 480215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 481215f4cc0SJerome Brunet 4824235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4834235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4844235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 485969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4864235ff50SMiodrag Dinic select IRQ_DOMAIN 4874235ff50SMiodrag Dinic help 4884235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4894235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4904235ff50SMiodrag Dinic 491f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4924acd8a4bSSaravana Kannan tristate "QCOM PDC" 493f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 494f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 495f55c73aeSArchana Sathyakumar help 496f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 497f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 498f55c73aeSArchana Sathyakumar 499a6199bb5SShawn Guoconfig QCOM_MPM 500a6199bb5SShawn Guo tristate "QCOM MPM" 501a6199bb5SShawn Guo depends on ARCH_QCOM 502fa4dcc88SYueHaibing depends on MAILBOX 503a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 504a6199bb5SShawn Guo help 505a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 506a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 507a6199bb5SShawn Guo 508d8a5f5f7SGuo Renconfig CSKY_MPINTC 509be1abc5bSGuo Ren bool 510d8a5f5f7SGuo Ren depends on CSKY 511d8a5f5f7SGuo Ren help 512d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 513d8a5f5f7SGuo Ren for C-SKY SMP system. 514656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 515d8a5f5f7SGuo Ren controller's register inside CPU. 516d8a5f5f7SGuo Ren 517edff1b48SGuo Renconfig CSKY_APB_INTC 518edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 519edff1b48SGuo Ren depends on CSKY 520edff1b48SGuo Ren help 521edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 522656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 523edff1b48SGuo Ren the controller's register. 524edff1b48SGuo Ren 5250136afa0SLucas Stachconfig IMX_IRQSTEER 5260136afa0SLucas Stach bool "i.MX IRQSTEER support" 5270136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5280136afa0SLucas Stach default ARCH_MXC 5290136afa0SLucas Stach select IRQ_DOMAIN 5300136afa0SLucas Stach help 5310136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5320136afa0SLucas Stach 5332fbb1396SJoakim Zhangconfig IMX_INTMUX 534a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 535a890caebSGeert Uytterhoeven default y if ARCH_MXC 5362fbb1396SJoakim Zhang select IRQ_DOMAIN 5372fbb1396SJoakim Zhang help 5382fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5392fbb1396SJoakim Zhang 54070afdab9SFrank Liconfig IMX_MU_MSI 54170afdab9SFrank Li tristate "i.MX MU used as MSI controller" 54270afdab9SFrank Li depends on OF && HAS_IOMEM 5436c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 54470afdab9SFrank Li default m if ARCH_MXC 54570afdab9SFrank Li select IRQ_DOMAIN 54670afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 54713e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5487b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 54970afdab9SFrank Li help 5506c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5516c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5526c9f7434SGeert Uytterhoeven to make use of this driver. 55370afdab9SFrank Li 55470afdab9SFrank Li If unsure, say N 55570afdab9SFrank Li 5569e543e22SJiaxun Yangconfig LS1X_IRQ 5579e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5589e543e22SJiaxun Yang depends on MACH_LOONGSON32 5599e543e22SJiaxun Yang default y 5609e543e22SJiaxun Yang select IRQ_DOMAIN 5619e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5629e543e22SJiaxun Yang help 5639e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5649e543e22SJiaxun Yang 565cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5662d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 567cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5682d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 569cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 570cd844b07SLokesh Vutla help 571cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 572cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 573cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 574cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 575cd844b07SLokesh Vutla 5769f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 577b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5789f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 579b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5809f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 581f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5829f1463b8SLokesh Vutla help 5839f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5849f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5859f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5869f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5879f1463b8SLokesh Vutla 58804e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 589b8e594faSSuman Anna tristate 590b8e594faSSuman Anna depends on TI_PRUSS 591b8e594faSSuman Anna default TI_PRUSS 59204e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 59304e2d1e0SGrzegorz Jaszczyk help 59404e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 59504e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 59604e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 59704e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 59804e2d1e0SGrzegorz Jaszczyk 5996b7ce892SAnup Patelconfig RISCV_INTC 600d8fb1307SConor Dooley bool 6016b7ce892SAnup Patel depends on RISCV 602832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 6036b7ce892SAnup Patel 6042333df5aSAnup Patelconfig RISCV_APLIC 6052333df5aSAnup Patel bool 6062333df5aSAnup Patel depends on RISCV 6072333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 6082333df5aSAnup Patel 609ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 610ca8df97fSAnup Patel bool 611ca8df97fSAnup Patel depends on RISCV_APLIC 612ca8df97fSAnup Patel select GENERIC_MSI_IRQ 613ca8df97fSAnup Patel default RISCV_APLIC 614ca8df97fSAnup Patel 61521a8f8a0SAnup Patelconfig RISCV_IMSIC 61621a8f8a0SAnup Patel bool 61721a8f8a0SAnup Patel depends on RISCV 61821a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 61921a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 62021a8f8a0SAnup Patel select GENERIC_MSI_IRQ 621fe35eceeSThomas Gleixner select IRQ_MSI_LIB 6225c5a71d0SAnup Patel 6238237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 624fdb1742aSConor Dooley bool 6258237f8bcSChristoph Hellwig depends on RISCV 626466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 627de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 62801493855SJonathan Neuschäfer 629e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 630e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 631e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 632e4e53503SChanghuang Liang default ARCH_STARFIVE 633e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 634e4e53503SChanghuang Liang help 635e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 636e4e53503SChanghuang Liang SoC. 637e4e53503SChanghuang Liang 638e4e53503SChanghuang Liang If you don't know what to do here, say Y. 639e4e53503SChanghuang Liang 640df0f030eSVladimir Kondratievconfig ACLINT_SSWI 641df0f030eSVladimir Kondratiev bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 64225caea95SInochi Amaoto depends on RISCV 64325caea95SInochi Amaoto depends on SMP 64425caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 64525caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 64625caea95SInochi Amaoto help 647df0f030eSVladimir Kondratiev This enables support for variants of the RISC-V ACLINT-SSWI device. 648df0f030eSVladimir Kondratiev Supported variants are: 649df0f030eSVladimir Kondratiev - T-HEAD, with compatible "thead,c900-aclint-sswi" 650df0f030eSVladimir Kondratiev - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 65125caea95SInochi Amaoto 65225caea95SInochi Amaoto If you don't know what to do here, say Y. 65325caea95SInochi Amaoto 654df0f030eSVladimir Kondratiev# Backwards compatibility so oldconfig does not drop it. 655df0f030eSVladimir Kondratievconfig THEAD_C900_ACLINT_SSWI 656df0f030eSVladimir Kondratiev bool 657df0f030eSVladimir Kondratiev select ACLINT_SSWI 658df0f030eSVladimir Kondratiev 659b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 660b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 661b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 662b74416dbSHyunki Koo help 663b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 664b74416dbSHyunki Koo in Samsung Exynos chips. 665b74416dbSHyunki Koo 666b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 667b2d3e335SHuacai Chen bool 668b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 669b2d3e335SHuacai Chen select IRQ_DOMAIN 67042a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 67170f7b6c0SHuacai Chen select LOONGSON_HTVEC 6728d5356f9SHuacai Chen select LOONGSON_LIOINTC 6738d5356f9SHuacai Chen select LOONGSON_EIOINTC 6748d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6758d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6768d5356f9SHuacai Chen select LOONGSON_PCH_LPC 677b2d3e335SHuacai Chen help 678b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 679b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 68051712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 681b2d3e335SHuacai Chen 682dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 683dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 684dbb15226SJiaxun Yang depends on MACH_LOONGSON64 685dbb15226SJiaxun Yang default y 686dbb15226SJiaxun Yang select IRQ_DOMAIN 687dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 688dbb15226SJiaxun Yang help 689dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 690dbb15226SJiaxun Yang 691dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 692dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 693dd281e1aSHuacai Chen depends on LOONGARCH 694dd281e1aSHuacai Chen depends on MACH_LOONGSON64 695dd281e1aSHuacai Chen default MACH_LOONGSON64 696dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 697dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 698dd281e1aSHuacai Chen help 699dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 700dd281e1aSHuacai Chen 701a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 702a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 703987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 704a93f1d90SJiaxun Yang default y 705a93f1d90SJiaxun Yang select IRQ_DOMAIN 706a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 707a93f1d90SJiaxun Yang help 708a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 709a93f1d90SJiaxun Yang 710818e915fSJiaxun Yangconfig LOONGSON_HTVEC 711987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 712d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 713818e915fSJiaxun Yang default MACH_LOONGSON64 714818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 715818e915fSJiaxun Yang help 716987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 717818e915fSJiaxun Yang 718ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 719ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 720bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 721ef8c01ebSJiaxun Yang default MACH_LOONGSON64 722ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 723ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 724ef8c01ebSJiaxun Yang help 725ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 726ef8c01ebSJiaxun Yang 727632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 728a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 72902308732SHuacai Chen depends on MACH_LOONGSON64 730632dcc2cSJiaxun Yang depends on PCI 731632dcc2cSJiaxun Yang default MACH_LOONGSON64 732632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7330b3af759SHuacai Chen select IRQ_MSI_LIB 734632dcc2cSJiaxun Yang select PCI_MSI 735632dcc2cSJiaxun Yang help 736632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 737632dcc2cSJiaxun Yang 738ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 739ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 740e7ccba77SJianmin Lv depends on LOONGARCH 741ee73f14eSHuacai Chen depends on MACH_LOONGSON64 742e7ccba77SJianmin Lv default MACH_LOONGSON64 743ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 744ee73f14eSHuacai Chen help 745ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 746ee73f14eSHuacai Chen 747ad4c938cSMark-PK Tsaiconfig MST_IRQ 748ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 74961b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 750ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 751ad4c938cSMark-PK Tsai select IRQ_DOMAIN 752ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 753ad4c938cSMark-PK Tsai help 754ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 755ad4c938cSMark-PK Tsai 756fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 757fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 75894bc9420SMarc Zyngier depends on ARCH_WPCM450 759fead4dd4SJonathan Neuschäfer help 760fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 761fead4dd4SJonathan Neuschäfer 762529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 763529ea368SThomas Bogendoerfer bool 764529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 765529ea368SThomas Bogendoerfer select IRQ_DOMAIN 766529ea368SThomas Bogendoerfer 76776cde263SHector Martinconfig APPLE_AIC 76876cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 76976cde263SHector Martin depends on ARM64 7705b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 771c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 77276cde263SHector Martin help 77376cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 77476cde263SHector Martin such as the M1. 77576cde263SHector Martin 77600fa3461SClaudiu Bezneaconfig MCHP_EIC 77700fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 77800fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 77900fa3461SClaudiu Beznea select IRQ_DOMAIN 78000fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 78100fa3461SClaudiu Beznea help 78200fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 78300fa3461SClaudiu Beznea 784c6674154SChen Wangconfig SOPHGO_SG2042_MSI 785c6674154SChen Wang bool "Sophgo SG2042 MSI Controller" 786c6674154SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 787c6674154SChen Wang depends on PCI 788c6674154SChen Wang select IRQ_DOMAIN_HIERARCHY 789c6674154SChen Wang select IRQ_MSI_LIB 790c6674154SChen Wang select PCI_MSI 791c6674154SChen Wang help 792c6674154SChen Wang Support for the Sophgo SG2042 MSI Controller. 793c6674154SChen Wang This on-chip interrupt controller enables MSI sources to be 794c6674154SChen Wang routed to the primary PLIC controller on SoC. 795c6674154SChen Wang 796f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 797f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 798f7189d93SQin Jian default SOC_SP7021 799f7189d93SQin Jian help 800f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 801f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 802f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 803f7189d93SQin Jian the primary controller on C-Chip. 804f7189d93SQin Jian 80501493855SJonathan Neuschäferendmenu 806