1f6e916b8SThomas Petazzoniconfig IRQCHIP 2f6e916b8SThomas Petazzoni def_bool y 3f6e916b8SThomas Petazzoni depends on OF_IRQ 4f6e916b8SThomas Petazzoni 581243e44SRob Herringconfig ARM_GIC 681243e44SRob Herring bool 781243e44SRob Herring select IRQ_DOMAIN 881243e44SRob Herring select MULTI_IRQ_HANDLER 981243e44SRob Herring 1081243e44SRob Herringconfig GIC_NON_BANKED 1181243e44SRob Herring bool 1281243e44SRob Herring 13292ec080SUwe Kleine-Königconfig ARM_NVIC 14292ec080SUwe Kleine-König bool 15292ec080SUwe Kleine-König select IRQ_DOMAIN 16292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 17292ec080SUwe Kleine-König 1844430ec0SRob Herringconfig ARM_VIC 1944430ec0SRob Herring bool 2044430ec0SRob Herring select IRQ_DOMAIN 2144430ec0SRob Herring select MULTI_IRQ_HANDLER 2244430ec0SRob Herring 2344430ec0SRob Herringconfig ARM_VIC_NR 2444430ec0SRob Herring int 2544430ec0SRob Herring default 4 if ARCH_S5PV210 2644430ec0SRob Herring default 3 if ARCH_S5PC100 2744430ec0SRob Herring default 2 2844430ec0SRob Herring depends on ARM_VIC 2944430ec0SRob Herring help 3044430ec0SRob Herring The maximum number of VICs available in the system, for 3144430ec0SRob Herring power management. 3244430ec0SRob Herring 33*7f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 34*7f646e92SFlorian Fainelli bool 35*7f646e92SFlorian Fainelli depends on ARM 36*7f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 37*7f646e92SFlorian Fainelli select IRQ_DOMAIN 38*7f646e92SFlorian Fainelli 39350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 40350d71b9SSebastian Hesselbarth bool 41350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 42350d71b9SSebastian Hesselbarth 43b6ef9161SJames Hoganconfig IMGPDC_IRQ 44b6ef9161SJames Hogan bool 45b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 46b6ef9161SJames Hogan select IRQ_DOMAIN 47b6ef9161SJames Hogan 48afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 49afc98d90SAlexander Shiyan bool 50afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 51afc98d90SAlexander Shiyan select IRQ_DOMAIN 52afc98d90SAlexander Shiyan select MULTI_IRQ_HANDLER 53afc98d90SAlexander Shiyan select SPARSE_IRQ 54afc98d90SAlexander Shiyan default y 55afc98d90SAlexander Shiyan 569dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 579dbd90f1SSebastian Hesselbarth bool 589dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 599dbd90f1SSebastian Hesselbarth select MULTI_IRQ_HANDLER 609dbd90f1SSebastian Hesselbarth 6144358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 6244358048SMagnus Damm bool 6344358048SMagnus Damm select IRQ_DOMAIN 6444358048SMagnus Damm 65fbc83b7fSMagnus Dammconfig RENESAS_IRQC 66fbc83b7fSMagnus Damm bool 67fbc83b7fSMagnus Damm select IRQ_DOMAIN 68fbc83b7fSMagnus Damm 69b06eb017SChristian Ruppertconfig TB10X_IRQC 70b06eb017SChristian Ruppert bool 71b06eb017SChristian Ruppert select IRQ_DOMAIN 72b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 73b06eb017SChristian Ruppert 742389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 752389d501SLinus Walleij bool 762389d501SLinus Walleij select IRQ_DOMAIN 772389d501SLinus Walleij 782389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 792389d501SLinus Walleij int 802389d501SLinus Walleij default 4 812389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 8226a8e96aSMax Filippov 8326a8e96aSMax Filippovconfig XTENSA_MX 8426a8e96aSMax Filippov bool 8526a8e96aSMax Filippov select IRQ_DOMAIN 8696ca848eSSricharan R 8796ca848eSSricharan Rconfig IRQ_CROSSBAR 8896ca848eSSricharan R bool 8996ca848eSSricharan R help 9096ca848eSSricharan R Support for a CROSSBAR ip that preceeds the main interrupt controller. 9196ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 9296ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 9396ca848eSSricharan R routed to one of the free irqchip interrupt lines. 94