1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 293ee80364SArnd Bergmann select PCI_MSI 30853a33ceSSuravee Suthikulpanit 3181243e44SRob Herringconfig GIC_NON_BANKED 3281243e44SRob Herring bool 3381243e44SRob Herring 34021f6537SMarc Zyngierconfig ARM_GIC_V3 35021f6537SMarc Zyngier bool 36443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 37e3825ba1SMarc Zyngier select PARTITION_PERCPU 380e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3935727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 40021f6537SMarc Zyngier 4119812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4219812729SMarc Zyngier bool 4313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4429f41139SMarc Zyngier default ARM_GIC_V3 4529f41139SMarc Zyngier 4629f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4729f41139SMarc Zyngier bool 4829f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 493ee80364SArnd Bergmann depends on PCI 503ee80364SArnd Bergmann depends on PCI_MSI 5129f41139SMarc Zyngier default ARM_GIC_V3_ITS 52292ec080SUwe Kleine-König 537afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 547afe031cSBogdan Purcareata bool 557afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata depends on FSL_MC_BUS 577afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata 5944430ec0SRob Herringconfig ARM_NVIC 6044430ec0SRob Herring bool 612d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6244430ec0SRob Herring select GENERIC_IRQ_CHIP 6344430ec0SRob Herring 6444430ec0SRob Herringconfig ARM_VIC 6544430ec0SRob Herring bool 6644430ec0SRob Herring select IRQ_DOMAIN 6744430ec0SRob Herring 6844430ec0SRob Herringconfig ARM_VIC_NR 6944430ec0SRob Herring int 7044430ec0SRob Herring default 4 if ARCH_S5PV210 7144430ec0SRob Herring default 2 7244430ec0SRob Herring depends on ARM_VIC 7344430ec0SRob Herring help 7444430ec0SRob Herring The maximum number of VICs available in the system, for 7544430ec0SRob Herring power management. 7644430ec0SRob Herring 77fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 78fed6d336SThomas Petazzoni bool 79fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 803ee80364SArnd Bergmann select PCI_MSI if PCI 810e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 82fed6d336SThomas Petazzoni 83e6b78f2cSAntoine Tenartconfig ALPINE_MSI 84e6b78f2cSAntoine Tenart bool 853ee80364SArnd Bergmann depends on PCI 863ee80364SArnd Bergmann select PCI_MSI 87e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 88e6b78f2cSAntoine Tenart 891eb77c3bSTalel Shenharconfig AL_FIC 901eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 919869f37aSJean Delvare depends on OF 9235e0cd77SBaoquan He depends on HAS_IOMEM 931eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 941eb77c3bSTalel Shenhar select IRQ_DOMAIN 951eb77c3bSTalel Shenhar help 961eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 971eb77c3bSTalel Shenhar 98b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 99b1479ebbSBoris BREZILLON bool 100b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 101b1479ebbSBoris BREZILLON select IRQ_DOMAIN 102b1479ebbSBoris BREZILLON select SPARSE_IRQ 103b1479ebbSBoris BREZILLON 104b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 105b1479ebbSBoris BREZILLON bool 106b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 107b1479ebbSBoris BREZILLON select IRQ_DOMAIN 108b1479ebbSBoris BREZILLON select SPARSE_IRQ 109b1479ebbSBoris BREZILLON 1100509cfdeSRalf Baechleconfig I8259 1110509cfdeSRalf Baechle bool 1120509cfdeSRalf Baechle select IRQ_DOMAIN 1130509cfdeSRalf Baechle 114c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 115c7c42ec2SSimon Arlott bool 116c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 117c7c42ec2SSimon Arlott select IRQ_DOMAIN 1180e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 119c7c42ec2SSimon Arlott 1205f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 121c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 122c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 123c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1245f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1255f7f0317SKevin Cernekee select IRQ_DOMAIN 1260e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1275f7f0317SKevin Cernekee 128a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1293ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1303ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1313ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 132a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 133a4fcbb86SKevin Cernekee select IRQ_DOMAIN 134a4fcbb86SKevin Cernekee 1357f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 13651d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 13751d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 13851d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1397f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1407f646e92SFlorian Fainelli select IRQ_DOMAIN 1417f646e92SFlorian Fainelli 1420fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1430fc3d74cSBartosz Golaszewski bool 1440fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1450fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1460fc3d74cSBartosz Golaszewski 147350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 148*7cc4f309SJisheng Zhang tristate "DesignWare APB Interrupt Controller" 149e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15054a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 151350d71b9SSebastian Hesselbarth 1526ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1536ee532e2SLinus Walleij bool 1546ee532e2SLinus Walleij select IRQ_DOMAIN 1556ee532e2SLinus Walleij select SPARSE_IRQ 1566ee532e2SLinus Walleij 1579a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1589a7c4abdSMaJun bool 1599a7c4abdSMaJun select ARM_GIC_V3 1609a7c4abdSMaJun select ARM_GIC_V3_ITS 1619a7c4abdSMaJun 162b6ef9161SJames Hoganconfig IMGPDC_IRQ 163b6ef9161SJames Hogan bool 164b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 165b6ef9161SJames Hogan select IRQ_DOMAIN 166b6ef9161SJames Hogan 1675b978c10SLinus Walleijconfig IXP4XX_IRQ 1685b978c10SLinus Walleij bool 1695b978c10SLinus Walleij select IRQ_DOMAIN 1705b978c10SLinus Walleij select SPARSE_IRQ 1715b978c10SLinus Walleij 1723e3a7b35SHerve Codinaconfig LAN966X_OIC 1733e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 1743e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 1753e3a7b35SHerve Codina select IRQ_DOMAIN 1763e3a7b35SHerve Codina help 1773e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 1783e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 1793e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 1803e3a7b35SHerve Codina 1813e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 1823e3a7b35SHerve Codina will be called irq-lan966x-oic. 1833e3a7b35SHerve Codina 184da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 185da0abe1aSRichard Fitzgerald tristate 186da0abe1aSRichard Fitzgerald 18767e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 18867e38cf2SRalf Baechle bool 18967e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1900f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 19167e38cf2SRalf Baechle select IRQ_DOMAIN 1920e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 19367e38cf2SRalf Baechle 194afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 195afc98d90SAlexander Shiyan bool 196afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 197afc98d90SAlexander Shiyan select IRQ_DOMAIN 198afc98d90SAlexander Shiyan select SPARSE_IRQ 199afc98d90SAlexander Shiyan default y 200afc98d90SAlexander Shiyan 2019b54470aSStafford Horneconfig OMPIC 2029b54470aSStafford Horne bool 2039b54470aSStafford Horne 2044db8e6d2SStefan Kristianssonconfig OR1K_PIC 2054db8e6d2SStefan Kristiansson bool 2064db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2074db8e6d2SStefan Kristiansson 2088598066cSFelipe Balbiconfig OMAP_IRQCHIP 2098598066cSFelipe Balbi bool 2108598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2118598066cSFelipe Balbi select IRQ_DOMAIN 2128598066cSFelipe Balbi 2139dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2149dbd90f1SSebastian Hesselbarth bool 2159dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2169dbd90f1SSebastian Hesselbarth 217aaa8666aSCristian Birsanconfig PIC32_EVIC 218aaa8666aSCristian Birsan bool 219aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 220aaa8666aSCristian Birsan select IRQ_DOMAIN 221aaa8666aSCristian Birsan 222981b58f6SRich Felkerconfig JCORE_AIC 2233602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2243602ffdeSRich Felker depends on OF 225981b58f6SRich Felker select IRQ_DOMAIN 226981b58f6SRich Felker help 227981b58f6SRich Felker Support for the J-Core integrated AIC. 228981b58f6SRich Felker 229d852e62aSManivannan Sadhasivamconfig RDA_INTC 230d852e62aSManivannan Sadhasivam bool 231d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 232d852e62aSManivannan Sadhasivam 23344358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 23402d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 23544358048SMagnus Damm select IRQ_DOMAIN 23602d7e041SGeert Uytterhoeven help 23702d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23802d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 23944358048SMagnus Damm 240fbc83b7fSMagnus Dammconfig RENESAS_IRQC 24172d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 24299c221dfSMagnus Damm select GENERIC_IRQ_CHIP 243fbc83b7fSMagnus Damm select IRQ_DOMAIN 24402d7e041SGeert Uytterhoeven help 24502d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 24672d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 247fbc83b7fSMagnus Damm 248a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 24902d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 250a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 25102d7e041SGeert Uytterhoeven help 25202d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 25302d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 254a644ccb8SGeert Uytterhoeven 2553fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2563fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2573fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2583fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2593fed0955SLad Prabhakar help 2603fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2613fed0955SLad Prabhakar for external devices. 2623fed0955SLad Prabhakar 26303ac990eSMichael Walleconfig SL28CPLD_INTC 26403ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 26503ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 26603ac990eSMichael Walle select REGMAP_IRQ 26703ac990eSMichael Walle help 26803ac990eSMichael Walle Interrupt controller driver for the board management controller 26903ac990eSMichael Walle found on the Kontron sl28 CPLD. 27003ac990eSMichael Walle 27107088484SLee Jonesconfig ST_IRQCHIP 27207088484SLee Jones bool 27307088484SLee Jones select REGMAP 27407088484SLee Jones select MFD_SYSCON 27507088484SLee Jones help 27607088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 27707088484SLee Jones 278d421fd6dSSamuel Hollandconfig SUN4I_INTC 279d421fd6dSSamuel Holland bool 280d421fd6dSSamuel Holland 281d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 282d421fd6dSSamuel Holland bool 283d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 284d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 285d421fd6dSSamuel Holland 286d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 287d421fd6dSSamuel Holland bool 288d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 289d421fd6dSSamuel Holland 290b06eb017SChristian Ruppertconfig TB10X_IRQC 291b06eb017SChristian Ruppert bool 292b06eb017SChristian Ruppert select IRQ_DOMAIN 293b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 294b06eb017SChristian Ruppert 295d01f8633SDamien Riegelconfig TS4800_IRQ 296d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 297d01f8633SDamien Riegel select IRQ_DOMAIN 2980df337cfSRichard Weinberger depends on HAS_IOMEM 299d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 300d01f8633SDamien Riegel help 301d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 302d01f8633SDamien Riegel 3032389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3042389d501SLinus Walleij bool 3052389d501SLinus Walleij select IRQ_DOMAIN 3062389d501SLinus Walleij 3072389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3082389d501SLinus Walleij int 3092389d501SLinus Walleij default 4 3102389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 31126a8e96aSMax Filippov 31226a8e96aSMax Filippovconfig XTENSA_MX 31326a8e96aSMax Filippov bool 31426a8e96aSMax Filippov select IRQ_DOMAIN 3150e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 31696ca848eSSricharan R 3170547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 318debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 319fd31000dSJamie Iles depends on OF_ADDRESS 3200547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 321debf69cfSRobert Hancock help 322debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 323debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 324debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3250547dc78SZubair Lutfullah Kakakhel 32696ca848eSSricharan Rconfig IRQ_CROSSBAR 32796ca848eSSricharan R bool 32896ca848eSSricharan R help 329f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 33096ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 33196ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 33296ca848eSSricharan R routed to one of the free irqchip interrupt lines. 33389323f8cSGrygorii Strashko 33489323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 33589323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 33689323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 33789323f8cSGrygorii Strashko help 33889323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 33989323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3408a19b8f1SAndrew Bresticker 3418a19b8f1SAndrew Brestickerconfig MIPS_GIC 3428a19b8f1SAndrew Bresticker bool 3438190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3448190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3458a19b8f1SAndrew Bresticker select MIPS_CM 3468a764482SYoshinori Sato 34744e08e70SPaul Burtonconfig INGENIC_IRQ 34844e08e70SPaul Burton bool 34944e08e70SPaul Burton depends on MACH_INGENIC 35044e08e70SPaul Burton default y 35178c10e55SLinus Torvalds 3529536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3539536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3549536eba0SPaul Cercueil default MACH_INGENIC 3559536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3569536eba0SPaul Cercueil select MFD_SYSCON 3578084499bSYueHaibing select GENERIC_IRQ_CHIP 3589536eba0SPaul Cercueil help 3599536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3609536eba0SPaul Cercueil JZ47xx SoCs. 3619536eba0SPaul Cercueil 3629536eba0SPaul Cercueil If unsure, say N. 3639536eba0SPaul Cercueil 364e324c4dcSShenwei Wangconfig IMX_GPCV2 365e324c4dcSShenwei Wang bool 366e324c4dcSShenwei Wang select IRQ_DOMAIN 367e324c4dcSShenwei Wang help 368e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3697e4ac676SOleksij Rempel 3707e4ac676SOleksij Rempelconfig IRQ_MXS 3717e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3727e4ac676SOleksij Rempel select IRQ_DOMAIN 3737e4ac676SOleksij Rempel select STMP_DEVICE 374c27f29bbSThomas Petazzoni 37519d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 37619d99164SAlexandre Belloni bool 37719d99164SAlexandre Belloni select IRQ_DOMAIN 37819d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 37919d99164SAlexandre Belloni 380a68a63cbSThomas Petazzoniconfig MVEBU_GICP 381a68a63cbSThomas Petazzoni bool 382a68a63cbSThomas Petazzoni 383e0de91a9SThomas Petazzoniconfig MVEBU_ICU 384e0de91a9SThomas Petazzoni bool 385e0de91a9SThomas Petazzoni 386c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 387c27f29bbSThomas Petazzoni bool 38813e7accbSThomas Gleixner select GENERIC_MSI_IRQ 3899e2c986cSMarc Zyngier 390a109893bSThomas Petazzoniconfig MVEBU_PIC 391a109893bSThomas Petazzoni bool 392a109893bSThomas Petazzoni 39361ce8d8dSMiquel Raynalconfig MVEBU_SEI 39461ce8d8dSMiquel Raynal bool 39561ce8d8dSMiquel Raynal 3960dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3970dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3980dcd9f87SRasmus Villemoes select MFD_SYSCON 3990dcd9f87SRasmus Villemoes 400b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 401b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4029c1a7bfcSLukas Bulwahn depends on PCI_MSI 403b8f3ebe6SMinghuan Lian 4049e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4059e2c986cSMarc Zyngier bool 4060efacbbaSLinus Torvalds 407e0720416SAlexandre TORGUEconfig STM32_EXTI 408e0720416SAlexandre TORGUE bool 409e0720416SAlexandre TORGUE select IRQ_DOMAIN 4100e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 411f20cc9b0SAgustin Vega-Frias 412f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 413f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 414f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 415f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 416f20cc9b0SAgustin Vega-Frias help 417f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 418f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4195ed34d3aSMasahiro Yamada 4205ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4215ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4225ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4235ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4245ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4255ed34d3aSMasahiro Yamada help 4265ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 427c94fb639SRandy Dunlap 428215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 429a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 430a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 431a947aa00SNeil Armstrong default ARCH_MESON 432215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 433215f4cc0SJerome Brunet help 434215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 435215f4cc0SJerome Brunet 4364235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4374235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4384235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 439969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4404235ff50SMiodrag Dinic select IRQ_DOMAIN 4414235ff50SMiodrag Dinic help 4424235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4434235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4444235ff50SMiodrag Dinic 445f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4464acd8a4bSSaravana Kannan tristate "QCOM PDC" 447f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 448f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 449f55c73aeSArchana Sathyakumar help 450f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 451f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 452f55c73aeSArchana Sathyakumar 453a6199bb5SShawn Guoconfig QCOM_MPM 454a6199bb5SShawn Guo tristate "QCOM MPM" 455a6199bb5SShawn Guo depends on ARCH_QCOM 456fa4dcc88SYueHaibing depends on MAILBOX 457a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 458a6199bb5SShawn Guo help 459a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 460a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 461a6199bb5SShawn Guo 462d8a5f5f7SGuo Renconfig CSKY_MPINTC 463be1abc5bSGuo Ren bool 464d8a5f5f7SGuo Ren depends on CSKY 465d8a5f5f7SGuo Ren help 466d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 467d8a5f5f7SGuo Ren for C-SKY SMP system. 468656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 469d8a5f5f7SGuo Ren controller's register inside CPU. 470d8a5f5f7SGuo Ren 471edff1b48SGuo Renconfig CSKY_APB_INTC 472edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 473edff1b48SGuo Ren depends on CSKY 474edff1b48SGuo Ren help 475edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 476656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 477edff1b48SGuo Ren the controller's register. 478edff1b48SGuo Ren 4790136afa0SLucas Stachconfig IMX_IRQSTEER 4800136afa0SLucas Stach bool "i.MX IRQSTEER support" 4810136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4820136afa0SLucas Stach default ARCH_MXC 4830136afa0SLucas Stach select IRQ_DOMAIN 4840136afa0SLucas Stach help 4850136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4860136afa0SLucas Stach 4872fbb1396SJoakim Zhangconfig IMX_INTMUX 488a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 489a890caebSGeert Uytterhoeven default y if ARCH_MXC 4902fbb1396SJoakim Zhang select IRQ_DOMAIN 4912fbb1396SJoakim Zhang help 4922fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4932fbb1396SJoakim Zhang 49470afdab9SFrank Liconfig IMX_MU_MSI 49570afdab9SFrank Li tristate "i.MX MU used as MSI controller" 49670afdab9SFrank Li depends on OF && HAS_IOMEM 4976c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 49870afdab9SFrank Li default m if ARCH_MXC 49970afdab9SFrank Li select IRQ_DOMAIN 50070afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 50113e7accbSThomas Gleixner select GENERIC_MSI_IRQ 50270afdab9SFrank Li help 5036c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5046c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5056c9f7434SGeert Uytterhoeven to make use of this driver. 50670afdab9SFrank Li 50770afdab9SFrank Li If unsure, say N 50870afdab9SFrank Li 5099e543e22SJiaxun Yangconfig LS1X_IRQ 5109e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5119e543e22SJiaxun Yang depends on MACH_LOONGSON32 5129e543e22SJiaxun Yang default y 5139e543e22SJiaxun Yang select IRQ_DOMAIN 5149e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5159e543e22SJiaxun Yang help 5169e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5179e543e22SJiaxun Yang 518cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 519cd844b07SLokesh Vutla bool 520cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 521cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 522cd844b07SLokesh Vutla help 523cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 524cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 525cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 526cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 527cd844b07SLokesh Vutla 5289f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5299f1463b8SLokesh Vutla bool 5309f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5319f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 532f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5339f1463b8SLokesh Vutla help 5349f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5359f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5369f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5379f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5389f1463b8SLokesh Vutla 53904e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 540b8e594faSSuman Anna tristate 541b8e594faSSuman Anna depends on TI_PRUSS 542b8e594faSSuman Anna default TI_PRUSS 54304e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 54404e2d1e0SGrzegorz Jaszczyk help 54504e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 54604e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 54704e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 54804e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 54904e2d1e0SGrzegorz Jaszczyk 5506b7ce892SAnup Patelconfig RISCV_INTC 551d8fb1307SConor Dooley bool 5526b7ce892SAnup Patel depends on RISCV 553832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5546b7ce892SAnup Patel 5552333df5aSAnup Patelconfig RISCV_APLIC 5562333df5aSAnup Patel bool 5572333df5aSAnup Patel depends on RISCV 5582333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 5592333df5aSAnup Patel 560ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 561ca8df97fSAnup Patel bool 562ca8df97fSAnup Patel depends on RISCV_APLIC 563ca8df97fSAnup Patel select GENERIC_MSI_IRQ 564ca8df97fSAnup Patel default RISCV_APLIC 565ca8df97fSAnup Patel 56621a8f8a0SAnup Patelconfig RISCV_IMSIC 56721a8f8a0SAnup Patel bool 56821a8f8a0SAnup Patel depends on RISCV 56921a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 57021a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 57121a8f8a0SAnup Patel select GENERIC_MSI_IRQ 57221a8f8a0SAnup Patel 5735c5a71d0SAnup Patelconfig RISCV_IMSIC_PCI 5745c5a71d0SAnup Patel bool 5755c5a71d0SAnup Patel depends on RISCV_IMSIC 5765c5a71d0SAnup Patel depends on PCI 5775c5a71d0SAnup Patel depends on PCI_MSI 5785c5a71d0SAnup Patel default RISCV_IMSIC 5795c5a71d0SAnup Patel 5808237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 581fdb1742aSConor Dooley bool 5828237f8bcSChristoph Hellwig depends on RISCV 583466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 584de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 58501493855SJonathan Neuschäfer 586e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 587e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 588e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 589e4e53503SChanghuang Liang default ARCH_STARFIVE 590e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 591e4e53503SChanghuang Liang help 592e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 593e4e53503SChanghuang Liang SoC. 594e4e53503SChanghuang Liang 595e4e53503SChanghuang Liang If you don't know what to do here, say Y. 596e4e53503SChanghuang Liang 597b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 598b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 599b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 600b74416dbSHyunki Koo help 601b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 602b74416dbSHyunki Koo in Samsung Exynos chips. 603b74416dbSHyunki Koo 604b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 605b2d3e335SHuacai Chen bool 606b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 607b2d3e335SHuacai Chen select IRQ_DOMAIN 60842a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 60970f7b6c0SHuacai Chen select LOONGSON_HTVEC 6108d5356f9SHuacai Chen select LOONGSON_LIOINTC 6118d5356f9SHuacai Chen select LOONGSON_EIOINTC 6128d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6138d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6148d5356f9SHuacai Chen select LOONGSON_PCH_LPC 615b2d3e335SHuacai Chen help 616b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 617b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 61851712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 619b2d3e335SHuacai Chen 620dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 621dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 622dbb15226SJiaxun Yang depends on MACH_LOONGSON64 623dbb15226SJiaxun Yang default y 624dbb15226SJiaxun Yang select IRQ_DOMAIN 625dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 626dbb15226SJiaxun Yang help 627dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 628dbb15226SJiaxun Yang 629dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 630dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 631dd281e1aSHuacai Chen depends on LOONGARCH 632dd281e1aSHuacai Chen depends on MACH_LOONGSON64 633dd281e1aSHuacai Chen default MACH_LOONGSON64 634dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 635dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 636dd281e1aSHuacai Chen help 637dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 638dd281e1aSHuacai Chen 639a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 640a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 641987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 642a93f1d90SJiaxun Yang default y 643a93f1d90SJiaxun Yang select IRQ_DOMAIN 644a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 645a93f1d90SJiaxun Yang help 646a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 647a93f1d90SJiaxun Yang 648818e915fSJiaxun Yangconfig LOONGSON_HTVEC 649987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 650d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 651818e915fSJiaxun Yang default MACH_LOONGSON64 652818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 653818e915fSJiaxun Yang help 654987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 655818e915fSJiaxun Yang 656ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 657ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 658bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 659ef8c01ebSJiaxun Yang default MACH_LOONGSON64 660ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 661ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 662ef8c01ebSJiaxun Yang help 663ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 664ef8c01ebSJiaxun Yang 665632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 666a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 66702308732SHuacai Chen depends on MACH_LOONGSON64 668632dcc2cSJiaxun Yang depends on PCI 669632dcc2cSJiaxun Yang default MACH_LOONGSON64 670632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 671632dcc2cSJiaxun Yang select PCI_MSI 672632dcc2cSJiaxun Yang help 673632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 674632dcc2cSJiaxun Yang 675ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 676ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 677e7ccba77SJianmin Lv depends on LOONGARCH 678ee73f14eSHuacai Chen depends on MACH_LOONGSON64 679e7ccba77SJianmin Lv default MACH_LOONGSON64 680ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 681ee73f14eSHuacai Chen help 682ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 683ee73f14eSHuacai Chen 684ad4c938cSMark-PK Tsaiconfig MST_IRQ 685ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 68661b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 687ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 688ad4c938cSMark-PK Tsai select IRQ_DOMAIN 689ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 690ad4c938cSMark-PK Tsai help 691ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 692ad4c938cSMark-PK Tsai 693fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 694fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 69594bc9420SMarc Zyngier depends on ARCH_WPCM450 696fead4dd4SJonathan Neuschäfer help 697fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 698fead4dd4SJonathan Neuschäfer 699529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 700529ea368SThomas Bogendoerfer bool 701529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 702529ea368SThomas Bogendoerfer select IRQ_DOMAIN 703529ea368SThomas Bogendoerfer 70476cde263SHector Martinconfig APPLE_AIC 70576cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 70676cde263SHector Martin depends on ARM64 7075b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 708c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 70976cde263SHector Martin help 71076cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 71176cde263SHector Martin such as the M1. 71276cde263SHector Martin 71300fa3461SClaudiu Bezneaconfig MCHP_EIC 71400fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 71500fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 71600fa3461SClaudiu Beznea select IRQ_DOMAIN 71700fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 71800fa3461SClaudiu Beznea help 71900fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 72000fa3461SClaudiu Beznea 721f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 722f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 723f7189d93SQin Jian default SOC_SP7021 724f7189d93SQin Jian help 725f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 726f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 727f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 728f7189d93SQin Jian the primary controller on C-Chip. 729f7189d93SQin Jian 73001493855SJonathan Neuschäferendmenu 731