1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6f6e916b8SThomas Petazzoni depends on OF_IRQ 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 109a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 110e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1281243e44SRob Herring 139c8edddfSJon Hunterconfig ARM_GIC_PM 149c8edddfSJon Hunter bool 159c8edddfSJon Hunter depends on PM 169c8edddfSJon Hunter select ARM_GIC 179c8edddfSJon Hunter 18a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 19a27d21e0SLinus Walleij int 2070265523SJiangfeng Xiao depends on ARM_GIC 21a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 22a27d21e0SLinus Walleij default 1 23a27d21e0SLinus Walleij 24853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 25853a33ceSSuravee Suthikulpanit bool 263ee80364SArnd Bergmann depends on PCI 273ee80364SArnd Bergmann select ARM_GIC 283ee80364SArnd Bergmann select PCI_MSI 29853a33ceSSuravee Suthikulpanit 3081243e44SRob Herringconfig GIC_NON_BANKED 3181243e44SRob Herring bool 3281243e44SRob Herring 33021f6537SMarc Zyngierconfig ARM_GIC_V3 34021f6537SMarc Zyngier bool 35443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 36e3825ba1SMarc Zyngier select PARTITION_PERCPU 370e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 38021f6537SMarc Zyngier 3919812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4019812729SMarc Zyngier bool 4129f41139SMarc Zyngier select GENERIC_MSI_IRQ_DOMAIN 4229f41139SMarc Zyngier default ARM_GIC_V3 4329f41139SMarc Zyngier 4429f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4529f41139SMarc Zyngier bool 4629f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 473ee80364SArnd Bergmann depends on PCI 483ee80364SArnd Bergmann depends on PCI_MSI 4929f41139SMarc Zyngier default ARM_GIC_V3_ITS 50292ec080SUwe Kleine-König 517afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 527afe031cSBogdan Purcareata bool 537afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 547afe031cSBogdan Purcareata depends on FSL_MC_BUS 557afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata 5744430ec0SRob Herringconfig ARM_NVIC 5844430ec0SRob Herring bool 592d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6044430ec0SRob Herring select GENERIC_IRQ_CHIP 6144430ec0SRob Herring 6244430ec0SRob Herringconfig ARM_VIC 6344430ec0SRob Herring bool 6444430ec0SRob Herring select IRQ_DOMAIN 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC_NR 6744430ec0SRob Herring int 6844430ec0SRob Herring default 4 if ARCH_S5PV210 6944430ec0SRob Herring default 2 7044430ec0SRob Herring depends on ARM_VIC 7144430ec0SRob Herring help 7244430ec0SRob Herring The maximum number of VICs available in the system, for 7344430ec0SRob Herring power management. 7444430ec0SRob Herring 75fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 76fed6d336SThomas Petazzoni bool 77fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 783ee80364SArnd Bergmann select PCI_MSI if PCI 790e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 80fed6d336SThomas Petazzoni 81e6b78f2cSAntoine Tenartconfig ALPINE_MSI 82e6b78f2cSAntoine Tenart bool 833ee80364SArnd Bergmann depends on PCI 843ee80364SArnd Bergmann select PCI_MSI 85e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 86e6b78f2cSAntoine Tenart 871eb77c3bSTalel Shenharconfig AL_FIC 881eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 891eb77c3bSTalel Shenhar depends on OF || COMPILE_TEST 901eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 911eb77c3bSTalel Shenhar select IRQ_DOMAIN 921eb77c3bSTalel Shenhar help 931eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 941eb77c3bSTalel Shenhar 95b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 96b1479ebbSBoris BREZILLON bool 97b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 98b1479ebbSBoris BREZILLON select IRQ_DOMAIN 99b1479ebbSBoris BREZILLON select SPARSE_IRQ 100b1479ebbSBoris BREZILLON 101b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 102b1479ebbSBoris BREZILLON bool 103b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 104b1479ebbSBoris BREZILLON select IRQ_DOMAIN 105b1479ebbSBoris BREZILLON select SPARSE_IRQ 106b1479ebbSBoris BREZILLON 1070509cfdeSRalf Baechleconfig I8259 1080509cfdeSRalf Baechle bool 1090509cfdeSRalf Baechle select IRQ_DOMAIN 1100509cfdeSRalf Baechle 111c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 112c7c42ec2SSimon Arlott bool 113c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 114c7c42ec2SSimon Arlott select IRQ_DOMAIN 1150e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 116c7c42ec2SSimon Arlott 1175f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 118c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 119c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 120c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1215f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1225f7f0317SKevin Cernekee select IRQ_DOMAIN 1230e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1245f7f0317SKevin Cernekee 125a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1263ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1273ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1283ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 129a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 130a4fcbb86SKevin Cernekee select IRQ_DOMAIN 131a4fcbb86SKevin Cernekee 1327f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 13351d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 13451d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 13551d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1367f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1377f646e92SFlorian Fainelli select IRQ_DOMAIN 1387f646e92SFlorian Fainelli 1390145beedSBartosz Golaszewskiconfig DAVINCI_AINTC 1400145beedSBartosz Golaszewski bool 1410145beedSBartosz Golaszewski select GENERIC_IRQ_CHIP 1420145beedSBartosz Golaszewski select IRQ_DOMAIN 1430145beedSBartosz Golaszewski 1440fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1450fc3d74cSBartosz Golaszewski bool 1460fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1470fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1480fc3d74cSBartosz Golaszewski 149350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 150350d71b9SSebastian Hesselbarth bool 151e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15254a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 153350d71b9SSebastian Hesselbarth 1546ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1556ee532e2SLinus Walleij bool 1566ee532e2SLinus Walleij select IRQ_DOMAIN 1576ee532e2SLinus Walleij select SPARSE_IRQ 1586ee532e2SLinus Walleij 1599a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1609a7c4abdSMaJun bool 1619a7c4abdSMaJun select ARM_GIC_V3 1629a7c4abdSMaJun select ARM_GIC_V3_ITS 1639a7c4abdSMaJun 164b6ef9161SJames Hoganconfig IMGPDC_IRQ 165b6ef9161SJames Hogan bool 166b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 167b6ef9161SJames Hogan select IRQ_DOMAIN 168b6ef9161SJames Hogan 1695b978c10SLinus Walleijconfig IXP4XX_IRQ 1705b978c10SLinus Walleij bool 1715b978c10SLinus Walleij select IRQ_DOMAIN 1725b978c10SLinus Walleij select SPARSE_IRQ 1735b978c10SLinus Walleij 174da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 175da0abe1aSRichard Fitzgerald tristate 176da0abe1aSRichard Fitzgerald 17767e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 17867e38cf2SRalf Baechle bool 17967e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1800f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 18167e38cf2SRalf Baechle select IRQ_DOMAIN 1820e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 18367e38cf2SRalf Baechle 184afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 185afc98d90SAlexander Shiyan bool 186afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 187afc98d90SAlexander Shiyan select IRQ_DOMAIN 188afc98d90SAlexander Shiyan select SPARSE_IRQ 189afc98d90SAlexander Shiyan default y 190afc98d90SAlexander Shiyan 1919b54470aSStafford Horneconfig OMPIC 1929b54470aSStafford Horne bool 1939b54470aSStafford Horne 1944db8e6d2SStefan Kristianssonconfig OR1K_PIC 1954db8e6d2SStefan Kristiansson bool 1964db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1974db8e6d2SStefan Kristiansson 1988598066cSFelipe Balbiconfig OMAP_IRQCHIP 1998598066cSFelipe Balbi bool 2008598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2018598066cSFelipe Balbi select IRQ_DOMAIN 2028598066cSFelipe Balbi 2039dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2049dbd90f1SSebastian Hesselbarth bool 2059dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2069dbd90f1SSebastian Hesselbarth 207aaa8666aSCristian Birsanconfig PIC32_EVIC 208aaa8666aSCristian Birsan bool 209aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 210aaa8666aSCristian Birsan select IRQ_DOMAIN 211aaa8666aSCristian Birsan 212981b58f6SRich Felkerconfig JCORE_AIC 2133602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2143602ffdeSRich Felker depends on OF 215981b58f6SRich Felker select IRQ_DOMAIN 216981b58f6SRich Felker help 217981b58f6SRich Felker Support for the J-Core integrated AIC. 218981b58f6SRich Felker 219d852e62aSManivannan Sadhasivamconfig RDA_INTC 220d852e62aSManivannan Sadhasivam bool 221d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 222d852e62aSManivannan Sadhasivam 22344358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 22402d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 22544358048SMagnus Damm select IRQ_DOMAIN 22602d7e041SGeert Uytterhoeven help 22702d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 22802d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 22944358048SMagnus Damm 230fbc83b7fSMagnus Dammconfig RENESAS_IRQC 23172d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 23299c221dfSMagnus Damm select GENERIC_IRQ_CHIP 233fbc83b7fSMagnus Damm select IRQ_DOMAIN 23402d7e041SGeert Uytterhoeven help 23502d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23672d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 237fbc83b7fSMagnus Damm 238a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 23902d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 240a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 24102d7e041SGeert Uytterhoeven help 24202d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 24302d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 244a644ccb8SGeert Uytterhoeven 2453fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2463fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2473fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2483fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2493fed0955SLad Prabhakar help 2503fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2513fed0955SLad Prabhakar for external devices. 2523fed0955SLad Prabhakar 25303ac990eSMichael Walleconfig SL28CPLD_INTC 25403ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 25503ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 25603ac990eSMichael Walle select REGMAP_IRQ 25703ac990eSMichael Walle help 25803ac990eSMichael Walle Interrupt controller driver for the board management controller 25903ac990eSMichael Walle found on the Kontron sl28 CPLD. 26003ac990eSMichael Walle 26107088484SLee Jonesconfig ST_IRQCHIP 26207088484SLee Jones bool 26307088484SLee Jones select REGMAP 26407088484SLee Jones select MFD_SYSCON 26507088484SLee Jones help 26607088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 26707088484SLee Jones 268d421fd6dSSamuel Hollandconfig SUN4I_INTC 269d421fd6dSSamuel Holland bool 270d421fd6dSSamuel Holland 271d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 272d421fd6dSSamuel Holland bool 273d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 274d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 275d421fd6dSSamuel Holland 276d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 277d421fd6dSSamuel Holland bool 278d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 279d421fd6dSSamuel Holland 280b06eb017SChristian Ruppertconfig TB10X_IRQC 281b06eb017SChristian Ruppert bool 282b06eb017SChristian Ruppert select IRQ_DOMAIN 283b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 284b06eb017SChristian Ruppert 285d01f8633SDamien Riegelconfig TS4800_IRQ 286d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 287d01f8633SDamien Riegel select IRQ_DOMAIN 2880df337cfSRichard Weinberger depends on HAS_IOMEM 289d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 290d01f8633SDamien Riegel help 291d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 292d01f8633SDamien Riegel 2932389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2942389d501SLinus Walleij bool 2952389d501SLinus Walleij select IRQ_DOMAIN 2962389d501SLinus Walleij 2972389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2982389d501SLinus Walleij int 2992389d501SLinus Walleij default 4 3002389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 30126a8e96aSMax Filippov 30226a8e96aSMax Filippovconfig XTENSA_MX 30326a8e96aSMax Filippov bool 30426a8e96aSMax Filippov select IRQ_DOMAIN 3050e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 30696ca848eSSricharan R 3070547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 308debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 309fd31000dSJamie Iles depends on OF_ADDRESS 3100547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 311debf69cfSRobert Hancock help 312debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 313debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 314debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3150547dc78SZubair Lutfullah Kakakhel 31696ca848eSSricharan Rconfig IRQ_CROSSBAR 31796ca848eSSricharan R bool 31896ca848eSSricharan R help 319f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 32096ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 32196ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 32296ca848eSSricharan R routed to one of the free irqchip interrupt lines. 32389323f8cSGrygorii Strashko 32489323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 32589323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 32689323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 32789323f8cSGrygorii Strashko help 32889323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 32989323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3308a19b8f1SAndrew Bresticker 3318a19b8f1SAndrew Brestickerconfig MIPS_GIC 3328a19b8f1SAndrew Bresticker bool 3338190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3348190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3358a19b8f1SAndrew Bresticker select MIPS_CM 3368a764482SYoshinori Sato 33744e08e70SPaul Burtonconfig INGENIC_IRQ 33844e08e70SPaul Burton bool 33944e08e70SPaul Burton depends on MACH_INGENIC 34044e08e70SPaul Burton default y 34178c10e55SLinus Torvalds 3429536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3439536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3449536eba0SPaul Cercueil default MACH_INGENIC 3459536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3469536eba0SPaul Cercueil select MFD_SYSCON 3478084499bSYueHaibing select GENERIC_IRQ_CHIP 3489536eba0SPaul Cercueil help 3499536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3509536eba0SPaul Cercueil JZ47xx SoCs. 3519536eba0SPaul Cercueil 3529536eba0SPaul Cercueil If unsure, say N. 3539536eba0SPaul Cercueil 354e324c4dcSShenwei Wangconfig IMX_GPCV2 355e324c4dcSShenwei Wang bool 356e324c4dcSShenwei Wang select IRQ_DOMAIN 357e324c4dcSShenwei Wang help 358e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3597e4ac676SOleksij Rempel 3607e4ac676SOleksij Rempelconfig IRQ_MXS 3617e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3627e4ac676SOleksij Rempel select IRQ_DOMAIN 3637e4ac676SOleksij Rempel select STMP_DEVICE 364c27f29bbSThomas Petazzoni 36519d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 36619d99164SAlexandre Belloni bool 36719d99164SAlexandre Belloni select IRQ_DOMAIN 36819d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 36919d99164SAlexandre Belloni 370a68a63cbSThomas Petazzoniconfig MVEBU_GICP 371a68a63cbSThomas Petazzoni bool 372a68a63cbSThomas Petazzoni 373e0de91a9SThomas Petazzoniconfig MVEBU_ICU 374e0de91a9SThomas Petazzoni bool 375e0de91a9SThomas Petazzoni 376c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 377c27f29bbSThomas Petazzoni bool 378fa23b9d1SArnd Bergmann select GENERIC_MSI_IRQ_DOMAIN 3799e2c986cSMarc Zyngier 380a109893bSThomas Petazzoniconfig MVEBU_PIC 381a109893bSThomas Petazzoni bool 382a109893bSThomas Petazzoni 38361ce8d8dSMiquel Raynalconfig MVEBU_SEI 38461ce8d8dSMiquel Raynal bool 38561ce8d8dSMiquel Raynal 3860dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3870dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3880dcd9f87SRasmus Villemoes select MFD_SYSCON 3890dcd9f87SRasmus Villemoes 390b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 391b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 392b8f3ebe6SMinghuan Lian depends on PCI && PCI_MSI 393b8f3ebe6SMinghuan Lian 3949e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3959e2c986cSMarc Zyngier bool 3960efacbbaSLinus Torvalds 397e0720416SAlexandre TORGUEconfig STM32_EXTI 398e0720416SAlexandre TORGUE bool 399e0720416SAlexandre TORGUE select IRQ_DOMAIN 4000e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 401f20cc9b0SAgustin Vega-Frias 402f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 403f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 404f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 405f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 406f20cc9b0SAgustin Vega-Frias help 407f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 408f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4095ed34d3aSMasahiro Yamada 4105ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4115ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4125ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4135ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4145ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4155ed34d3aSMasahiro Yamada help 4165ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 417c94fb639SRandy Dunlap 418215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 419a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 420a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 421a947aa00SNeil Armstrong default ARCH_MESON 422215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 423215f4cc0SJerome Brunet help 424215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 425215f4cc0SJerome Brunet 4264235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4274235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4284235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 429969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4304235ff50SMiodrag Dinic select IRQ_DOMAIN 4314235ff50SMiodrag Dinic help 4324235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4334235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4344235ff50SMiodrag Dinic 435f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4364acd8a4bSSaravana Kannan tristate "QCOM PDC" 437f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 438f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 439f55c73aeSArchana Sathyakumar help 440f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 441f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 442f55c73aeSArchana Sathyakumar 443a6199bb5SShawn Guoconfig QCOM_MPM 444a6199bb5SShawn Guo tristate "QCOM MPM" 445a6199bb5SShawn Guo depends on ARCH_QCOM 446fa4dcc88SYueHaibing depends on MAILBOX 447a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 448a6199bb5SShawn Guo help 449a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 450a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 451a6199bb5SShawn Guo 452d8a5f5f7SGuo Renconfig CSKY_MPINTC 453be1abc5bSGuo Ren bool 454d8a5f5f7SGuo Ren depends on CSKY 455d8a5f5f7SGuo Ren help 456d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 457d8a5f5f7SGuo Ren for C-SKY SMP system. 458656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 459d8a5f5f7SGuo Ren controller's register inside CPU. 460d8a5f5f7SGuo Ren 461edff1b48SGuo Renconfig CSKY_APB_INTC 462edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 463edff1b48SGuo Ren depends on CSKY 464edff1b48SGuo Ren help 465edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 466656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 467edff1b48SGuo Ren the controller's register. 468edff1b48SGuo Ren 4690136afa0SLucas Stachconfig IMX_IRQSTEER 4700136afa0SLucas Stach bool "i.MX IRQSTEER support" 4710136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4720136afa0SLucas Stach default ARCH_MXC 4730136afa0SLucas Stach select IRQ_DOMAIN 4740136afa0SLucas Stach help 4750136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4760136afa0SLucas Stach 4772fbb1396SJoakim Zhangconfig IMX_INTMUX 478a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 479a890caebSGeert Uytterhoeven default y if ARCH_MXC 4802fbb1396SJoakim Zhang select IRQ_DOMAIN 4812fbb1396SJoakim Zhang help 4822fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4832fbb1396SJoakim Zhang 484*70afdab9SFrank Liconfig IMX_MU_MSI 485*70afdab9SFrank Li tristate "i.MX MU used as MSI controller" 486*70afdab9SFrank Li depends on OF && HAS_IOMEM 487*70afdab9SFrank Li default m if ARCH_MXC 488*70afdab9SFrank Li select IRQ_DOMAIN 489*70afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 490*70afdab9SFrank Li select GENERIC_MSI_IRQ_DOMAIN 491*70afdab9SFrank Li help 492*70afdab9SFrank Li Provide a driver for the MU block used as a CPU-to-CPU MSI 493*70afdab9SFrank Li controller. This requires a specially crafted DT to make use 494*70afdab9SFrank Li of this driver. 495*70afdab9SFrank Li 496*70afdab9SFrank Li If unsure, say N 497*70afdab9SFrank Li 4989e543e22SJiaxun Yangconfig LS1X_IRQ 4999e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5009e543e22SJiaxun Yang depends on MACH_LOONGSON32 5019e543e22SJiaxun Yang default y 5029e543e22SJiaxun Yang select IRQ_DOMAIN 5039e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5049e543e22SJiaxun Yang help 5059e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5069e543e22SJiaxun Yang 507cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 508cd844b07SLokesh Vutla bool 509cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 510cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 511cd844b07SLokesh Vutla help 512cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 513cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 514cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 515cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 516cd844b07SLokesh Vutla 5179f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5189f1463b8SLokesh Vutla bool 5199f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5209f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 521f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5229f1463b8SLokesh Vutla help 5239f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5249f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5259f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5269f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5279f1463b8SLokesh Vutla 52804e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 529b8e594faSSuman Anna tristate 530b8e594faSSuman Anna depends on TI_PRUSS 531b8e594faSSuman Anna default TI_PRUSS 53204e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 53304e2d1e0SGrzegorz Jaszczyk help 53404e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 53504e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 53604e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 53704e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 53804e2d1e0SGrzegorz Jaszczyk 5396b7ce892SAnup Patelconfig RISCV_INTC 5406b7ce892SAnup Patel bool "RISC-V Local Interrupt Controller" 5416b7ce892SAnup Patel depends on RISCV 5426b7ce892SAnup Patel default y 5436b7ce892SAnup Patel help 5446b7ce892SAnup Patel This enables support for the per-HART local interrupt controller 5456b7ce892SAnup Patel found in standard RISC-V systems. The per-HART local interrupt 5466b7ce892SAnup Patel controller handles timer interrupts, software interrupts, and 5476b7ce892SAnup Patel hardware interrupts. Without a per-HART local interrupt controller, 5486b7ce892SAnup Patel a RISC-V system will be unable to handle any interrupts. 5496b7ce892SAnup Patel 5506b7ce892SAnup Patel If you don't know what to do here, say Y. 5516b7ce892SAnup Patel 5528237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 5538237f8bcSChristoph Hellwig bool "SiFive Platform-Level Interrupt Controller" 5548237f8bcSChristoph Hellwig depends on RISCV 555466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 556de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 5578237f8bcSChristoph Hellwig help 5588237f8bcSChristoph Hellwig This enables support for the PLIC chip found in SiFive (and 5598237f8bcSChristoph Hellwig potentially other) RISC-V systems. The PLIC controls devices 5608237f8bcSChristoph Hellwig interrupts and connects them to each core's local interrupt 5618237f8bcSChristoph Hellwig controller. Aside from timer and software interrupts, all other 5628237f8bcSChristoph Hellwig interrupt sources are subordinate to the PLIC. 5638237f8bcSChristoph Hellwig 5648237f8bcSChristoph Hellwig If you don't know what to do here, say Y. 56501493855SJonathan Neuschäfer 566b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 567b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 568b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 569b74416dbSHyunki Koo help 570b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 571b74416dbSHyunki Koo in Samsung Exynos chips. 572b74416dbSHyunki Koo 573b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 574b2d3e335SHuacai Chen bool 575b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 576b2d3e335SHuacai Chen select IRQ_DOMAIN 577b2d3e335SHuacai Chen select GENERIC_IRQ_EFFECTIVE_AFF_MASK 578b2d3e335SHuacai Chen help 579b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 580b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 581b2d3e335SHuacai Chen Documentation/loongarch/irq-chip-model.rst. 582b2d3e335SHuacai Chen 583dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 584dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 585dbb15226SJiaxun Yang depends on MACH_LOONGSON64 586dbb15226SJiaxun Yang default y 587dbb15226SJiaxun Yang select IRQ_DOMAIN 588dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 589dbb15226SJiaxun Yang help 590dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 591dbb15226SJiaxun Yang 592dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 593dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 594dd281e1aSHuacai Chen depends on LOONGARCH 595dd281e1aSHuacai Chen depends on MACH_LOONGSON64 596dd281e1aSHuacai Chen default MACH_LOONGSON64 597dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 598dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 599dd281e1aSHuacai Chen help 600dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 601dd281e1aSHuacai Chen 602a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 603a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 604987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 605a93f1d90SJiaxun Yang default y 606a93f1d90SJiaxun Yang select IRQ_DOMAIN 607a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 608a93f1d90SJiaxun Yang help 609a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 610a93f1d90SJiaxun Yang 611818e915fSJiaxun Yangconfig LOONGSON_HTVEC 612987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 613d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 614818e915fSJiaxun Yang default MACH_LOONGSON64 615818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 616818e915fSJiaxun Yang help 617987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 618818e915fSJiaxun Yang 619ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 620ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 621bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 622ef8c01ebSJiaxun Yang default MACH_LOONGSON64 623ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 624ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 625ef8c01ebSJiaxun Yang help 626ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 627ef8c01ebSJiaxun Yang 628632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 629a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 63002308732SHuacai Chen depends on MACH_LOONGSON64 631632dcc2cSJiaxun Yang depends on PCI 632632dcc2cSJiaxun Yang default MACH_LOONGSON64 633632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 634632dcc2cSJiaxun Yang select PCI_MSI 635632dcc2cSJiaxun Yang help 636632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 637632dcc2cSJiaxun Yang 638ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 639ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 640ee73f14eSHuacai Chen depends on MACH_LOONGSON64 641ee73f14eSHuacai Chen default (MACH_LOONGSON64 && LOONGARCH) 642ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 643ee73f14eSHuacai Chen help 644ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 645ee73f14eSHuacai Chen 646ad4c938cSMark-PK Tsaiconfig MST_IRQ 647ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 64861b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 649ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 650ad4c938cSMark-PK Tsai select IRQ_DOMAIN 651ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 652ad4c938cSMark-PK Tsai help 653ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 654ad4c938cSMark-PK Tsai 655fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 656fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 65794bc9420SMarc Zyngier depends on ARCH_WPCM450 658fead4dd4SJonathan Neuschäfer help 659fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 660fead4dd4SJonathan Neuschäfer 661529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 662529ea368SThomas Bogendoerfer bool 663529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 664529ea368SThomas Bogendoerfer select IRQ_DOMAIN 665529ea368SThomas Bogendoerfer 66676cde263SHector Martinconfig APPLE_AIC 66776cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 66876cde263SHector Martin depends on ARM64 6695b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 67076cde263SHector Martin help 67176cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 67276cde263SHector Martin such as the M1. 67376cde263SHector Martin 67400fa3461SClaudiu Bezneaconfig MCHP_EIC 67500fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 67600fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 67700fa3461SClaudiu Beznea select IRQ_DOMAIN 67800fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 67900fa3461SClaudiu Beznea help 68000fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 68100fa3461SClaudiu Beznea 682f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 683f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 684f7189d93SQin Jian default SOC_SP7021 685f7189d93SQin Jian help 686f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 687f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 688f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 689f7189d93SQin Jian the primary controller on C-Chip. 690f7189d93SQin Jian 69101493855SJonathan Neuschäferendmenu 692