1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 3196093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 4296093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 44b4ead12dSLorenzo Pieralisiconfig ARM_GIC_ITS_PARENT 45b4ead12dSLorenzo Pieralisi bool 46b4ead12dSLorenzo Pieralisi 4719812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4819812729SMarc Zyngier bool 4913e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5048f71d56SThomas Gleixner select IRQ_MSI_LIB 51b4ead12dSLorenzo Pieralisi select ARM_GIC_ITS_PARENT 5229f41139SMarc Zyngier default ARM_GIC_V3 5396093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5429f41139SMarc Zyngier 557afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 567afe031cSBogdan Purcareata bool 577afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata depends on FSL_MC_BUS 597afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 607afe031cSBogdan Purcareata 617ec80fb3SLorenzo Pieralisiconfig ARM_GIC_V5 627ec80fb3SLorenzo Pieralisi bool 637ec80fb3SLorenzo Pieralisi select IRQ_DOMAIN_HIERARCHY 647ec80fb3SLorenzo Pieralisi select GENERIC_IRQ_EFFECTIVE_AFF_MASK 65*57d72196SLorenzo Pieralisi select GENERIC_MSI_IRQ 66*57d72196SLorenzo Pieralisi select IRQ_MSI_LIB 67*57d72196SLorenzo Pieralisi select ARM_GIC_ITS_PARENT 687ec80fb3SLorenzo Pieralisi 69292ec080SUwe Kleine-Königconfig ARM_NVIC 70292ec080SUwe Kleine-König bool 712d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 72292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 73292ec080SUwe Kleine-König 7444430ec0SRob Herringconfig ARM_VIC 7544430ec0SRob Herring bool 7644430ec0SRob Herring select IRQ_DOMAIN 7744430ec0SRob Herring 7844430ec0SRob Herringconfig ARM_VIC_NR 7944430ec0SRob Herring int 8044430ec0SRob Herring default 4 if ARCH_S5PV210 8144430ec0SRob Herring default 2 8244430ec0SRob Herring depends on ARM_VIC 8344430ec0SRob Herring help 8444430ec0SRob Herring The maximum number of VICs available in the system, for 8544430ec0SRob Herring power management. 8644430ec0SRob Herring 8772e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 8872e257c6SThomas Gleixner bool 8972e257c6SThomas Gleixner 90fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 91fed6d336SThomas Petazzoni bool 92fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 933ee80364SArnd Bergmann select PCI_MSI if PCI 940e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 95fed6d336SThomas Petazzoni 96e6b78f2cSAntoine Tenartconfig ALPINE_MSI 97e6b78f2cSAntoine Tenart bool 983ee80364SArnd Bergmann depends on PCI 993ee80364SArnd Bergmann select PCI_MSI 100e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 101e6b78f2cSAntoine Tenart 1021eb77c3bSTalel Shenharconfig AL_FIC 1031eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 1049869f37aSJean Delvare depends on OF 10535e0cd77SBaoquan He depends on HAS_IOMEM 1061eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 1071eb77c3bSTalel Shenhar select IRQ_DOMAIN 1081eb77c3bSTalel Shenhar help 1091eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1101eb77c3bSTalel Shenhar 111b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 112b1479ebbSBoris BREZILLON bool 113b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 114b1479ebbSBoris BREZILLON select IRQ_DOMAIN 115b1479ebbSBoris BREZILLON select SPARSE_IRQ 116b1479ebbSBoris BREZILLON 117b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 118b1479ebbSBoris BREZILLON bool 119b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 120b1479ebbSBoris BREZILLON select IRQ_DOMAIN 121b1479ebbSBoris BREZILLON select SPARSE_IRQ 122b1479ebbSBoris BREZILLON 1230509cfdeSRalf Baechleconfig I8259 1240509cfdeSRalf Baechle bool 1250509cfdeSRalf Baechle select IRQ_DOMAIN 1260509cfdeSRalf Baechle 12732c6c054SStanimir Varbanovconfig BCM2712_MIP 12832c6c054SStanimir Varbanov tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 1299b3ae50cSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 1309b3ae50cSPeter Robinson default m if ARCH_BRCMSTB || ARCH_BCM2835 13132c6c054SStanimir Varbanov depends on ARM_GIC 13232c6c054SStanimir Varbanov select GENERIC_IRQ_CHIP 13332c6c054SStanimir Varbanov select IRQ_DOMAIN_HIERARCHY 13432c6c054SStanimir Varbanov select GENERIC_MSI_IRQ 13532c6c054SStanimir Varbanov select IRQ_MSI_LIB 13632c6c054SStanimir Varbanov help 13732c6c054SStanimir Varbanov Enable support for the Broadcom BCM2712 MSI-X target peripheral 13832c6c054SStanimir Varbanov (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 13932c6c054SStanimir Varbanov Raspberry Pi 5. 14032c6c054SStanimir Varbanov 14132c6c054SStanimir Varbanov If unsure say n. 14232c6c054SStanimir Varbanov 143c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 144c7c42ec2SSimon Arlott bool 145c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 146c7c42ec2SSimon Arlott select IRQ_DOMAIN 1470e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 148c7c42ec2SSimon Arlott 1495f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 150c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 151c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 152c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1535f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1545f7f0317SKevin Cernekee select IRQ_DOMAIN 1550e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1565f7f0317SKevin Cernekee 157a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1583ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1593ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1603ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 161a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 162a4fcbb86SKevin Cernekee select IRQ_DOMAIN 163a4fcbb86SKevin Cernekee 1647f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 16551d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 16651d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 16751d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1687f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1697f646e92SFlorian Fainelli select IRQ_DOMAIN 1707f646e92SFlorian Fainelli 1710fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1720fc3d74cSBartosz Golaszewski bool 1730fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1740fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1750fc3d74cSBartosz Golaszewski 176350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 177be5e5f3aSThomas Gleixner bool 178e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 17954a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 180350d71b9SSebastian Hesselbarth 1811902a59cSCaleb James DeLisleconfig ECONET_EN751221_INTC 1821902a59cSCaleb James DeLisle bool 1831902a59cSCaleb James DeLisle select GENERIC_IRQ_CHIP 1841902a59cSCaleb James DeLisle select IRQ_DOMAIN 1851902a59cSCaleb James DeLisle 1866ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1876ee532e2SLinus Walleij bool 1886ee532e2SLinus Walleij select IRQ_DOMAIN 1896ee532e2SLinus Walleij select SPARSE_IRQ 1906ee532e2SLinus Walleij 1919a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1929a7c4abdSMaJun bool 1939a7c4abdSMaJun select ARM_GIC_V3 1949a7c4abdSMaJun select ARM_GIC_V3_ITS 1959a7c4abdSMaJun 196b6ef9161SJames Hoganconfig IMGPDC_IRQ 197b6ef9161SJames Hogan bool 198b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 199b6ef9161SJames Hogan select IRQ_DOMAIN 200b6ef9161SJames Hogan 2015b978c10SLinus Walleijconfig IXP4XX_IRQ 2025b978c10SLinus Walleij bool 2035b978c10SLinus Walleij select IRQ_DOMAIN 2045b978c10SLinus Walleij select SPARSE_IRQ 2055b978c10SLinus Walleij 2063e3a7b35SHerve Codinaconfig LAN966X_OIC 2073e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 208e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 2093e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 2103e3a7b35SHerve Codina select IRQ_DOMAIN 2113e3a7b35SHerve Codina help 2123e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 2133e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 2143e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 2153e3a7b35SHerve Codina 2163e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 2173e3a7b35SHerve Codina will be called irq-lan966x-oic. 2183e3a7b35SHerve Codina 219da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 220da0abe1aSRichard Fitzgerald tristate 221da0abe1aSRichard Fitzgerald 22267e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 22367e38cf2SRalf Baechle bool 22467e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 2250f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 22667e38cf2SRalf Baechle select IRQ_DOMAIN 2270e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 22867e38cf2SRalf Baechle 229afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 230afc98d90SAlexander Shiyan bool 231afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 232afc98d90SAlexander Shiyan select IRQ_DOMAIN 233afc98d90SAlexander Shiyan select SPARSE_IRQ 234afc98d90SAlexander Shiyan default y 235afc98d90SAlexander Shiyan 2369b54470aSStafford Horneconfig OMPIC 2379b54470aSStafford Horne bool 2389b54470aSStafford Horne 2394db8e6d2SStefan Kristianssonconfig OR1K_PIC 2404db8e6d2SStefan Kristiansson bool 2414db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2424db8e6d2SStefan Kristiansson 2438598066cSFelipe Balbiconfig OMAP_IRQCHIP 2448598066cSFelipe Balbi bool 2458598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2468598066cSFelipe Balbi select IRQ_DOMAIN 2478598066cSFelipe Balbi 2489dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2499dbd90f1SSebastian Hesselbarth bool 2509dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2519dbd90f1SSebastian Hesselbarth 252aaa8666aSCristian Birsanconfig PIC32_EVIC 253aaa8666aSCristian Birsan bool 254aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 255aaa8666aSCristian Birsan select IRQ_DOMAIN 256aaa8666aSCristian Birsan 257981b58f6SRich Felkerconfig JCORE_AIC 2583602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2593602ffdeSRich Felker depends on OF 260981b58f6SRich Felker select IRQ_DOMAIN 261981b58f6SRich Felker help 262981b58f6SRich Felker Support for the J-Core integrated AIC. 263981b58f6SRich Felker 264d852e62aSManivannan Sadhasivamconfig RDA_INTC 265d852e62aSManivannan Sadhasivam bool 266d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 267d852e62aSManivannan Sadhasivam 26844358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 26902d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 27044358048SMagnus Damm select IRQ_DOMAIN 27102d7e041SGeert Uytterhoeven help 27202d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 27302d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 27444358048SMagnus Damm 275fbc83b7fSMagnus Dammconfig RENESAS_IRQC 27672d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 27799c221dfSMagnus Damm select GENERIC_IRQ_CHIP 278fbc83b7fSMagnus Damm select IRQ_DOMAIN 27902d7e041SGeert Uytterhoeven help 28002d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 28172d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 282fbc83b7fSMagnus Damm 283a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 28402d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 285a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 28602d7e041SGeert Uytterhoeven help 28702d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 28802d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 289a644ccb8SGeert Uytterhoeven 2903fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2913fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2923fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2933fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2943fed0955SLad Prabhakar help 2953fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2963fed0955SLad Prabhakar for external devices. 2973fed0955SLad Prabhakar 2980d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2990d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 3000d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 3010d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 3020d7605e7SFabrizio Castro help 3030d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 3040d7605e7SFabrizio Castro 30503ac990eSMichael Walleconfig SL28CPLD_INTC 30603ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 30703ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 30803ac990eSMichael Walle select REGMAP_IRQ 30903ac990eSMichael Walle help 31003ac990eSMichael Walle Interrupt controller driver for the board management controller 31103ac990eSMichael Walle found on the Kontron sl28 CPLD. 31203ac990eSMichael Walle 31307088484SLee Jonesconfig ST_IRQCHIP 31407088484SLee Jones bool 31507088484SLee Jones select REGMAP 31607088484SLee Jones select MFD_SYSCON 31707088484SLee Jones help 31807088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 31907088484SLee Jones 320d421fd6dSSamuel Hollandconfig SUN4I_INTC 321d421fd6dSSamuel Holland bool 322d421fd6dSSamuel Holland 323d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 324d421fd6dSSamuel Holland bool 325d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 326d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 327d421fd6dSSamuel Holland 328d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 329d421fd6dSSamuel Holland bool 330d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 331d421fd6dSSamuel Holland 332b06eb017SChristian Ruppertconfig TB10X_IRQC 333b06eb017SChristian Ruppert bool 334b06eb017SChristian Ruppert select IRQ_DOMAIN 335b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 336b06eb017SChristian Ruppert 337d01f8633SDamien Riegelconfig TS4800_IRQ 338d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 339d01f8633SDamien Riegel select IRQ_DOMAIN 3400df337cfSRichard Weinberger depends on HAS_IOMEM 341d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 342d01f8633SDamien Riegel help 343d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 344d01f8633SDamien Riegel 3452389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3462389d501SLinus Walleij bool 3472389d501SLinus Walleij select IRQ_DOMAIN 3482389d501SLinus Walleij 3492389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3502389d501SLinus Walleij int 3512389d501SLinus Walleij default 4 3522389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 35326a8e96aSMax Filippov 35426a8e96aSMax Filippovconfig XTENSA_MX 35526a8e96aSMax Filippov bool 35626a8e96aSMax Filippov select IRQ_DOMAIN 3570e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 35896ca848eSSricharan R 3590547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 360debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 361fd31000dSJamie Iles depends on OF_ADDRESS 3620547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 363debf69cfSRobert Hancock help 364debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 365debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 366debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3670547dc78SZubair Lutfullah Kakakhel 36896ca848eSSricharan Rconfig IRQ_CROSSBAR 36996ca848eSSricharan R bool 37096ca848eSSricharan R help 371f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 37296ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 37396ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 37496ca848eSSricharan R routed to one of the free irqchip interrupt lines. 37589323f8cSGrygorii Strashko 37689323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 37789323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 37889323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 37989323f8cSGrygorii Strashko help 38089323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 38189323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3828a19b8f1SAndrew Bresticker 3838a19b8f1SAndrew Brestickerconfig MIPS_GIC 3848a19b8f1SAndrew Bresticker bool 3850053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3868190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3878190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3888a19b8f1SAndrew Bresticker select MIPS_CM 3898a764482SYoshinori Sato 39044e08e70SPaul Burtonconfig INGENIC_IRQ 39144e08e70SPaul Burton bool 39244e08e70SPaul Burton depends on MACH_INGENIC 39344e08e70SPaul Burton default y 39478c10e55SLinus Torvalds 3959536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3969536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3979536eba0SPaul Cercueil default MACH_INGENIC 3989536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3999536eba0SPaul Cercueil select MFD_SYSCON 4008084499bSYueHaibing select GENERIC_IRQ_CHIP 4019536eba0SPaul Cercueil help 4029536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 4039536eba0SPaul Cercueil JZ47xx SoCs. 4049536eba0SPaul Cercueil 4059536eba0SPaul Cercueil If unsure, say N. 4069536eba0SPaul Cercueil 407e324c4dcSShenwei Wangconfig IMX_GPCV2 408e324c4dcSShenwei Wang bool 409e324c4dcSShenwei Wang select IRQ_DOMAIN 410e324c4dcSShenwei Wang help 411e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 4127e4ac676SOleksij Rempel 4137e4ac676SOleksij Rempelconfig IRQ_MXS 4147e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 4157e4ac676SOleksij Rempel select IRQ_DOMAIN 4167e4ac676SOleksij Rempel select STMP_DEVICE 417c27f29bbSThomas Petazzoni 41819d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 41919d99164SAlexandre Belloni bool 42019d99164SAlexandre Belloni select IRQ_DOMAIN 42119d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 42219d99164SAlexandre Belloni 423a68a63cbSThomas Petazzoniconfig MVEBU_GICP 424cdb23872SThomas Gleixner select IRQ_MSI_LIB 425a68a63cbSThomas Petazzoni bool 426a68a63cbSThomas Petazzoni 427e0de91a9SThomas Petazzoniconfig MVEBU_ICU 428e0de91a9SThomas Petazzoni bool 429e0de91a9SThomas Petazzoni 430c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 431c27f29bbSThomas Petazzoni bool 432e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 43313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4349e2c986cSMarc Zyngier 435a109893bSThomas Petazzoniconfig MVEBU_PIC 436a109893bSThomas Petazzoni bool 437a109893bSThomas Petazzoni 43861ce8d8dSMiquel Raynalconfig MVEBU_SEI 43961ce8d8dSMiquel Raynal bool 44061ce8d8dSMiquel Raynal 4410dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4420dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4430dcd9f87SRasmus Villemoes select MFD_SYSCON 4440dcd9f87SRasmus Villemoes 445b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 446b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 44796093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4489c1a7bfcSLukas Bulwahn depends on PCI_MSI 449b8f3ebe6SMinghuan Lian 4509e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4519e2c986cSMarc Zyngier bool 4520efacbbaSLinus Torvalds 453b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4540be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4550be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4569151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4570be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 458350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4590be58e05SAntonio Borneo help 4600be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 461b20cf2dcSAntonio Borneo 462e0720416SAlexandre TORGUEconfig STM32_EXTI 463e0720416SAlexandre TORGUE bool 464e0720416SAlexandre TORGUE select IRQ_DOMAIN 4650e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 466f20cc9b0SAgustin Vega-Frias 467f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 468f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 469f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 470f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 471f20cc9b0SAgustin Vega-Frias help 472f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 473f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4745ed34d3aSMasahiro Yamada 4755ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4765ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4775ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4785ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4795ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4805ed34d3aSMasahiro Yamada help 4815ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 482c94fb639SRandy Dunlap 483215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 484a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 485a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 486a947aa00SNeil Armstrong default ARCH_MESON 487215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 488215f4cc0SJerome Brunet help 489215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 490215f4cc0SJerome Brunet 4914235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4924235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4934235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 494969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4954235ff50SMiodrag Dinic select IRQ_DOMAIN 4964235ff50SMiodrag Dinic help 4974235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4984235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4994235ff50SMiodrag Dinic 500f55c73aeSArchana Sathyakumarconfig QCOM_PDC 5014acd8a4bSSaravana Kannan tristate "QCOM PDC" 502f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 503f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 504f55c73aeSArchana Sathyakumar help 505f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 506f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 507f55c73aeSArchana Sathyakumar 508a6199bb5SShawn Guoconfig QCOM_MPM 509a6199bb5SShawn Guo tristate "QCOM MPM" 510a6199bb5SShawn Guo depends on ARCH_QCOM 511fa4dcc88SYueHaibing depends on MAILBOX 512a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 513a6199bb5SShawn Guo help 514a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 515a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 516a6199bb5SShawn Guo 517d8a5f5f7SGuo Renconfig CSKY_MPINTC 518be1abc5bSGuo Ren bool 519d8a5f5f7SGuo Ren depends on CSKY 520d8a5f5f7SGuo Ren help 521d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 522d8a5f5f7SGuo Ren for C-SKY SMP system. 523656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 524d8a5f5f7SGuo Ren controller's register inside CPU. 525d8a5f5f7SGuo Ren 526edff1b48SGuo Renconfig CSKY_APB_INTC 527edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 528edff1b48SGuo Ren depends on CSKY 529edff1b48SGuo Ren help 530edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 531656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 532edff1b48SGuo Ren the controller's register. 533edff1b48SGuo Ren 5340136afa0SLucas Stachconfig IMX_IRQSTEER 5350136afa0SLucas Stach bool "i.MX IRQSTEER support" 5360136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5370136afa0SLucas Stach default ARCH_MXC 5380136afa0SLucas Stach select IRQ_DOMAIN 5390136afa0SLucas Stach help 5400136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5410136afa0SLucas Stach 5422fbb1396SJoakim Zhangconfig IMX_INTMUX 543a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 544a890caebSGeert Uytterhoeven default y if ARCH_MXC 5452fbb1396SJoakim Zhang select IRQ_DOMAIN 5462fbb1396SJoakim Zhang help 5472fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5482fbb1396SJoakim Zhang 54970afdab9SFrank Liconfig IMX_MU_MSI 55070afdab9SFrank Li tristate "i.MX MU used as MSI controller" 55170afdab9SFrank Li depends on OF && HAS_IOMEM 5526c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 55370afdab9SFrank Li default m if ARCH_MXC 55470afdab9SFrank Li select IRQ_DOMAIN 55570afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 55613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5577b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 55870afdab9SFrank Li help 5596c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5606c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5616c9f7434SGeert Uytterhoeven to make use of this driver. 56270afdab9SFrank Li 56370afdab9SFrank Li If unsure, say N 56470afdab9SFrank Li 5659e543e22SJiaxun Yangconfig LS1X_IRQ 5669e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5679e543e22SJiaxun Yang depends on MACH_LOONGSON32 5689e543e22SJiaxun Yang default y 5699e543e22SJiaxun Yang select IRQ_DOMAIN 5709e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5719e543e22SJiaxun Yang help 5729e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5739e543e22SJiaxun Yang 574cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5752d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 576cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5772d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 578cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 579cd844b07SLokesh Vutla help 580cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 581cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 582cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 583cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 584cd844b07SLokesh Vutla 5859f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 586b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5879f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 588b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5899f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 590f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5919f1463b8SLokesh Vutla help 5929f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5939f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5949f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5959f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5969f1463b8SLokesh Vutla 59704e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 598b8e594faSSuman Anna tristate 599b8e594faSSuman Anna depends on TI_PRUSS 600b8e594faSSuman Anna default TI_PRUSS 60104e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 60204e2d1e0SGrzegorz Jaszczyk help 60304e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 60404e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 60504e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 60604e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 60704e2d1e0SGrzegorz Jaszczyk 6086b7ce892SAnup Patelconfig RISCV_INTC 609d8fb1307SConor Dooley bool 6106b7ce892SAnup Patel depends on RISCV 611832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 6126b7ce892SAnup Patel 6132333df5aSAnup Patelconfig RISCV_APLIC 6142333df5aSAnup Patel bool 6152333df5aSAnup Patel depends on RISCV 6162333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 6172333df5aSAnup Patel 618ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 619ca8df97fSAnup Patel bool 620ca8df97fSAnup Patel depends on RISCV_APLIC 621ca8df97fSAnup Patel select GENERIC_MSI_IRQ 622ca8df97fSAnup Patel default RISCV_APLIC 623ca8df97fSAnup Patel 62421a8f8a0SAnup Patelconfig RISCV_IMSIC 62521a8f8a0SAnup Patel bool 62621a8f8a0SAnup Patel depends on RISCV 62721a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 62821a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 62921a8f8a0SAnup Patel select GENERIC_MSI_IRQ 630fe35eceeSThomas Gleixner select IRQ_MSI_LIB 6315c5a71d0SAnup Patel 6328237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 633fdb1742aSConor Dooley bool 6348237f8bcSChristoph Hellwig depends on RISCV 635466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 636de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 63701493855SJonathan Neuschäfer 638e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 639e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 640e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 641e4e53503SChanghuang Liang default ARCH_STARFIVE 642e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 643e4e53503SChanghuang Liang help 644e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 645e4e53503SChanghuang Liang SoC. 646e4e53503SChanghuang Liang 647e4e53503SChanghuang Liang If you don't know what to do here, say Y. 648e4e53503SChanghuang Liang 64925caea95SInochi Amaotoconfig THEAD_C900_ACLINT_SSWI 65025caea95SInochi Amaoto bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 65125caea95SInochi Amaoto depends on RISCV 65225caea95SInochi Amaoto depends on SMP 65325caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 65425caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 65525caea95SInochi Amaoto help 65625caea95SInochi Amaoto This enables support for T-HEAD specific ACLINT SSWI device 65725caea95SInochi Amaoto support. 65825caea95SInochi Amaoto 65925caea95SInochi Amaoto If you don't know what to do here, say Y. 66025caea95SInochi Amaoto 661b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 662b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 663b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 664b74416dbSHyunki Koo help 665b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 666b74416dbSHyunki Koo in Samsung Exynos chips. 667b74416dbSHyunki Koo 668b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 669b2d3e335SHuacai Chen bool 670b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 671b2d3e335SHuacai Chen select IRQ_DOMAIN 67242a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 67370f7b6c0SHuacai Chen select LOONGSON_HTVEC 6748d5356f9SHuacai Chen select LOONGSON_LIOINTC 6758d5356f9SHuacai Chen select LOONGSON_EIOINTC 6768d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6778d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6788d5356f9SHuacai Chen select LOONGSON_PCH_LPC 679b2d3e335SHuacai Chen help 680b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 681b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 68251712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 683b2d3e335SHuacai Chen 684dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 685dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 686dbb15226SJiaxun Yang depends on MACH_LOONGSON64 687dbb15226SJiaxun Yang default y 688dbb15226SJiaxun Yang select IRQ_DOMAIN 689dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 690dbb15226SJiaxun Yang help 691dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 692dbb15226SJiaxun Yang 693dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 694dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 695dd281e1aSHuacai Chen depends on LOONGARCH 696dd281e1aSHuacai Chen depends on MACH_LOONGSON64 697dd281e1aSHuacai Chen default MACH_LOONGSON64 698dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 699dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 700dd281e1aSHuacai Chen help 701dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 702dd281e1aSHuacai Chen 703a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 704a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 705987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 706a93f1d90SJiaxun Yang default y 707a93f1d90SJiaxun Yang select IRQ_DOMAIN 708a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 709a93f1d90SJiaxun Yang help 710a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 711a93f1d90SJiaxun Yang 712818e915fSJiaxun Yangconfig LOONGSON_HTVEC 713987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 714d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 715818e915fSJiaxun Yang default MACH_LOONGSON64 716818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 717818e915fSJiaxun Yang help 718987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 719818e915fSJiaxun Yang 720ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 721ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 722bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 723ef8c01ebSJiaxun Yang default MACH_LOONGSON64 724ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 725ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 726ef8c01ebSJiaxun Yang help 727ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 728ef8c01ebSJiaxun Yang 729632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 730a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 73102308732SHuacai Chen depends on MACH_LOONGSON64 732632dcc2cSJiaxun Yang depends on PCI 733632dcc2cSJiaxun Yang default MACH_LOONGSON64 734632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7350b3af759SHuacai Chen select IRQ_MSI_LIB 736632dcc2cSJiaxun Yang select PCI_MSI 737632dcc2cSJiaxun Yang help 738632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 739632dcc2cSJiaxun Yang 740ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 741ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 742e7ccba77SJianmin Lv depends on LOONGARCH 743ee73f14eSHuacai Chen depends on MACH_LOONGSON64 744e7ccba77SJianmin Lv default MACH_LOONGSON64 745ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 746ee73f14eSHuacai Chen help 747ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 748ee73f14eSHuacai Chen 749ad4c938cSMark-PK Tsaiconfig MST_IRQ 750ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 75161b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 752ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 753ad4c938cSMark-PK Tsai select IRQ_DOMAIN 754ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 755ad4c938cSMark-PK Tsai help 756ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 757ad4c938cSMark-PK Tsai 758fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 759fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 76094bc9420SMarc Zyngier depends on ARCH_WPCM450 761fead4dd4SJonathan Neuschäfer help 762fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 763fead4dd4SJonathan Neuschäfer 764529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 765529ea368SThomas Bogendoerfer bool 766529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 767529ea368SThomas Bogendoerfer select IRQ_DOMAIN 768529ea368SThomas Bogendoerfer 76976cde263SHector Martinconfig APPLE_AIC 77076cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 77176cde263SHector Martin depends on ARM64 7725b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 773c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 77476cde263SHector Martin help 77576cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 77676cde263SHector Martin such as the M1. 77776cde263SHector Martin 77800fa3461SClaudiu Bezneaconfig MCHP_EIC 77900fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 78000fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 78100fa3461SClaudiu Beznea select IRQ_DOMAIN 78200fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 78300fa3461SClaudiu Beznea help 78400fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 78500fa3461SClaudiu Beznea 786c6674154SChen Wangconfig SOPHGO_SG2042_MSI 787c6674154SChen Wang bool "Sophgo SG2042 MSI Controller" 788c6674154SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 789c6674154SChen Wang depends on PCI 790c6674154SChen Wang select IRQ_DOMAIN_HIERARCHY 791c6674154SChen Wang select IRQ_MSI_LIB 792c6674154SChen Wang select PCI_MSI 793c6674154SChen Wang help 794c6674154SChen Wang Support for the Sophgo SG2042 MSI Controller. 795c6674154SChen Wang This on-chip interrupt controller enables MSI sources to be 796c6674154SChen Wang routed to the primary PLIC controller on SoC. 797c6674154SChen Wang 798f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 799f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 800f7189d93SQin Jian default SOC_SP7021 801f7189d93SQin Jian help 802f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 803f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 804f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 805f7189d93SQin Jian the primary controller on C-Chip. 806f7189d93SQin Jian 80701493855SJonathan Neuschäferendmenu 808