1f6e916b8SThomas Petazzoniconfig IRQCHIP 2f6e916b8SThomas Petazzoni def_bool y 3f6e916b8SThomas Petazzoni depends on OF_IRQ 4f6e916b8SThomas Petazzoni 581243e44SRob Herringconfig ARM_GIC 681243e44SRob Herring bool 781243e44SRob Herring select IRQ_DOMAIN 881243e44SRob Herring select MULTI_IRQ_HANDLER 981243e44SRob Herring 1081243e44SRob Herringconfig GIC_NON_BANKED 1181243e44SRob Herring bool 1281243e44SRob Herring 13292ec080SUwe Kleine-Königconfig ARM_NVIC 14292ec080SUwe Kleine-König bool 15292ec080SUwe Kleine-König select IRQ_DOMAIN 16292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 17292ec080SUwe Kleine-König 1844430ec0SRob Herringconfig ARM_VIC 1944430ec0SRob Herring bool 2044430ec0SRob Herring select IRQ_DOMAIN 2144430ec0SRob Herring select MULTI_IRQ_HANDLER 2244430ec0SRob Herring 2344430ec0SRob Herringconfig ARM_VIC_NR 2444430ec0SRob Herring int 2544430ec0SRob Herring default 4 if ARCH_S5PV210 2644430ec0SRob Herring default 3 if ARCH_S5PC100 2744430ec0SRob Herring default 2 2844430ec0SRob Herring depends on ARM_VIC 2944430ec0SRob Herring help 3044430ec0SRob Herring The maximum number of VICs available in the system, for 3144430ec0SRob Herring power management. 3244430ec0SRob Herring 337f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 347f646e92SFlorian Fainelli bool 357f646e92SFlorian Fainelli depends on ARM 367f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 377f646e92SFlorian Fainelli select IRQ_DOMAIN 387f646e92SFlorian Fainelli 39350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 40350d71b9SSebastian Hesselbarth bool 41350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 42350d71b9SSebastian Hesselbarth 43b6ef9161SJames Hoganconfig IMGPDC_IRQ 44b6ef9161SJames Hogan bool 45b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 46b6ef9161SJames Hogan select IRQ_DOMAIN 47b6ef9161SJames Hogan 48afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 49afc98d90SAlexander Shiyan bool 50afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 51afc98d90SAlexander Shiyan select IRQ_DOMAIN 52afc98d90SAlexander Shiyan select MULTI_IRQ_HANDLER 53afc98d90SAlexander Shiyan select SPARSE_IRQ 54afc98d90SAlexander Shiyan default y 55afc98d90SAlexander Shiyan 56*4db8e6d2SStefan Kristianssonconfig OR1K_PIC 57*4db8e6d2SStefan Kristiansson bool 58*4db8e6d2SStefan Kristiansson select IRQ_DOMAIN 59*4db8e6d2SStefan Kristiansson 609dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 619dbd90f1SSebastian Hesselbarth bool 629dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 639dbd90f1SSebastian Hesselbarth select MULTI_IRQ_HANDLER 649dbd90f1SSebastian Hesselbarth 6544358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 6644358048SMagnus Damm bool 6744358048SMagnus Damm select IRQ_DOMAIN 6844358048SMagnus Damm 69fbc83b7fSMagnus Dammconfig RENESAS_IRQC 70fbc83b7fSMagnus Damm bool 71fbc83b7fSMagnus Damm select IRQ_DOMAIN 72fbc83b7fSMagnus Damm 73b06eb017SChristian Ruppertconfig TB10X_IRQC 74b06eb017SChristian Ruppert bool 75b06eb017SChristian Ruppert select IRQ_DOMAIN 76b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 77b06eb017SChristian Ruppert 782389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 792389d501SLinus Walleij bool 802389d501SLinus Walleij select IRQ_DOMAIN 812389d501SLinus Walleij 822389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 832389d501SLinus Walleij int 842389d501SLinus Walleij default 4 852389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 8626a8e96aSMax Filippov 8726a8e96aSMax Filippovconfig XTENSA_MX 8826a8e96aSMax Filippov bool 8926a8e96aSMax Filippov select IRQ_DOMAIN 9096ca848eSSricharan R 9196ca848eSSricharan Rconfig IRQ_CROSSBAR 9296ca848eSSricharan R bool 9396ca848eSSricharan R help 9496ca848eSSricharan R Support for a CROSSBAR ip that preceeds the main interrupt controller. 9596ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 9696ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 9796ca848eSSricharan R routed to one of the free irqchip interrupt lines. 98