1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 293ee80364SArnd Bergmann select PCI_MSI 30853a33ceSSuravee Suthikulpanit 3181243e44SRob Herringconfig GIC_NON_BANKED 3281243e44SRob Herring bool 3381243e44SRob Herring 34021f6537SMarc Zyngierconfig ARM_GIC_V3 35021f6537SMarc Zyngier bool 36443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 37e3825ba1SMarc Zyngier select PARTITION_PERCPU 380e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3935727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 40021f6537SMarc Zyngier 4119812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4219812729SMarc Zyngier bool 4313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 44*48f71d56SThomas Gleixner select IRQ_MSI_LIB 4529f41139SMarc Zyngier default ARM_GIC_V3 4629f41139SMarc Zyngier 4729f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4829f41139SMarc Zyngier bool 4929f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 503ee80364SArnd Bergmann depends on PCI 513ee80364SArnd Bergmann depends on PCI_MSI 5229f41139SMarc Zyngier default ARM_GIC_V3_ITS 53292ec080SUwe Kleine-König 547afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 557afe031cSBogdan Purcareata bool 567afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 577afe031cSBogdan Purcareata depends on FSL_MC_BUS 587afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 597afe031cSBogdan Purcareata 6044430ec0SRob Herringconfig ARM_NVIC 6144430ec0SRob Herring bool 622d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6344430ec0SRob Herring select GENERIC_IRQ_CHIP 6444430ec0SRob Herring 6544430ec0SRob Herringconfig ARM_VIC 6644430ec0SRob Herring bool 6744430ec0SRob Herring select IRQ_DOMAIN 6844430ec0SRob Herring 6944430ec0SRob Herringconfig ARM_VIC_NR 7044430ec0SRob Herring int 7144430ec0SRob Herring default 4 if ARCH_S5PV210 7244430ec0SRob Herring default 2 7344430ec0SRob Herring depends on ARM_VIC 7444430ec0SRob Herring help 7544430ec0SRob Herring The maximum number of VICs available in the system, for 7644430ec0SRob Herring power management. 7744430ec0SRob Herring 7872e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 7972e257c6SThomas Gleixner bool 8072e257c6SThomas Gleixner 81fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 82fed6d336SThomas Petazzoni bool 83fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 843ee80364SArnd Bergmann select PCI_MSI if PCI 850e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 86fed6d336SThomas Petazzoni 87e6b78f2cSAntoine Tenartconfig ALPINE_MSI 88e6b78f2cSAntoine Tenart bool 893ee80364SArnd Bergmann depends on PCI 903ee80364SArnd Bergmann select PCI_MSI 91e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 92e6b78f2cSAntoine Tenart 931eb77c3bSTalel Shenharconfig AL_FIC 941eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 959869f37aSJean Delvare depends on OF 9635e0cd77SBaoquan He depends on HAS_IOMEM 971eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 981eb77c3bSTalel Shenhar select IRQ_DOMAIN 991eb77c3bSTalel Shenhar help 1001eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1011eb77c3bSTalel Shenhar 102b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 103b1479ebbSBoris BREZILLON bool 104b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 105b1479ebbSBoris BREZILLON select IRQ_DOMAIN 106b1479ebbSBoris BREZILLON select SPARSE_IRQ 107b1479ebbSBoris BREZILLON 108b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 109b1479ebbSBoris BREZILLON bool 110b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 111b1479ebbSBoris BREZILLON select IRQ_DOMAIN 112b1479ebbSBoris BREZILLON select SPARSE_IRQ 113b1479ebbSBoris BREZILLON 1140509cfdeSRalf Baechleconfig I8259 1150509cfdeSRalf Baechle bool 1160509cfdeSRalf Baechle select IRQ_DOMAIN 1170509cfdeSRalf Baechle 118c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 119c7c42ec2SSimon Arlott bool 120c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 121c7c42ec2SSimon Arlott select IRQ_DOMAIN 1220e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 123c7c42ec2SSimon Arlott 1245f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 125c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 126c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 127c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1285f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1295f7f0317SKevin Cernekee select IRQ_DOMAIN 1300e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1315f7f0317SKevin Cernekee 132a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1333ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1343ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1353ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 136a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 137a4fcbb86SKevin Cernekee select IRQ_DOMAIN 138a4fcbb86SKevin Cernekee 1397f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 14051d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 14151d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 14251d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1437f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1447f646e92SFlorian Fainelli select IRQ_DOMAIN 1457f646e92SFlorian Fainelli 1460fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1470fc3d74cSBartosz Golaszewski bool 1480fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1490fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1500fc3d74cSBartosz Golaszewski 151350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 152350d71b9SSebastian Hesselbarth bool 153e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15454a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 155350d71b9SSebastian Hesselbarth 1566ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1576ee532e2SLinus Walleij bool 1586ee532e2SLinus Walleij select IRQ_DOMAIN 1596ee532e2SLinus Walleij select SPARSE_IRQ 1606ee532e2SLinus Walleij 1619a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1629a7c4abdSMaJun bool 1639a7c4abdSMaJun select ARM_GIC_V3 1649a7c4abdSMaJun select ARM_GIC_V3_ITS 1659a7c4abdSMaJun 166b6ef9161SJames Hoganconfig IMGPDC_IRQ 167b6ef9161SJames Hogan bool 168b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 169b6ef9161SJames Hogan select IRQ_DOMAIN 170b6ef9161SJames Hogan 1715b978c10SLinus Walleijconfig IXP4XX_IRQ 1725b978c10SLinus Walleij bool 1735b978c10SLinus Walleij select IRQ_DOMAIN 1745b978c10SLinus Walleij select SPARSE_IRQ 1755b978c10SLinus Walleij 176da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 177da0abe1aSRichard Fitzgerald tristate 178da0abe1aSRichard Fitzgerald 17967e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 18067e38cf2SRalf Baechle bool 18167e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1820f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 18367e38cf2SRalf Baechle select IRQ_DOMAIN 1840e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 18567e38cf2SRalf Baechle 186afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 187afc98d90SAlexander Shiyan bool 188afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 189afc98d90SAlexander Shiyan select IRQ_DOMAIN 190afc98d90SAlexander Shiyan select SPARSE_IRQ 191afc98d90SAlexander Shiyan default y 192afc98d90SAlexander Shiyan 1939b54470aSStafford Horneconfig OMPIC 1949b54470aSStafford Horne bool 1959b54470aSStafford Horne 1964db8e6d2SStefan Kristianssonconfig OR1K_PIC 1974db8e6d2SStefan Kristiansson bool 1984db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1994db8e6d2SStefan Kristiansson 2008598066cSFelipe Balbiconfig OMAP_IRQCHIP 2018598066cSFelipe Balbi bool 2028598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2038598066cSFelipe Balbi select IRQ_DOMAIN 2048598066cSFelipe Balbi 2059dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2069dbd90f1SSebastian Hesselbarth bool 2079dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2089dbd90f1SSebastian Hesselbarth 209aaa8666aSCristian Birsanconfig PIC32_EVIC 210aaa8666aSCristian Birsan bool 211aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 212aaa8666aSCristian Birsan select IRQ_DOMAIN 213aaa8666aSCristian Birsan 214981b58f6SRich Felkerconfig JCORE_AIC 2153602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2163602ffdeSRich Felker depends on OF 217981b58f6SRich Felker select IRQ_DOMAIN 218981b58f6SRich Felker help 219981b58f6SRich Felker Support for the J-Core integrated AIC. 220981b58f6SRich Felker 221d852e62aSManivannan Sadhasivamconfig RDA_INTC 222d852e62aSManivannan Sadhasivam bool 223d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 224d852e62aSManivannan Sadhasivam 22544358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 22602d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 22744358048SMagnus Damm select IRQ_DOMAIN 22802d7e041SGeert Uytterhoeven help 22902d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23002d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 23144358048SMagnus Damm 232fbc83b7fSMagnus Dammconfig RENESAS_IRQC 23372d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 23499c221dfSMagnus Damm select GENERIC_IRQ_CHIP 235fbc83b7fSMagnus Damm select IRQ_DOMAIN 23602d7e041SGeert Uytterhoeven help 23702d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23872d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 239fbc83b7fSMagnus Damm 240a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 24102d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 242a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 24302d7e041SGeert Uytterhoeven help 24402d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 24502d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 246a644ccb8SGeert Uytterhoeven 2473fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2483fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2493fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2503fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2513fed0955SLad Prabhakar help 2523fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2533fed0955SLad Prabhakar for external devices. 2543fed0955SLad Prabhakar 25503ac990eSMichael Walleconfig SL28CPLD_INTC 25603ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 25703ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 25803ac990eSMichael Walle select REGMAP_IRQ 25903ac990eSMichael Walle help 26003ac990eSMichael Walle Interrupt controller driver for the board management controller 26103ac990eSMichael Walle found on the Kontron sl28 CPLD. 26203ac990eSMichael Walle 26307088484SLee Jonesconfig ST_IRQCHIP 26407088484SLee Jones bool 26507088484SLee Jones select REGMAP 26607088484SLee Jones select MFD_SYSCON 26707088484SLee Jones help 26807088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 26907088484SLee Jones 270d421fd6dSSamuel Hollandconfig SUN4I_INTC 271d421fd6dSSamuel Holland bool 272d421fd6dSSamuel Holland 273d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 274d421fd6dSSamuel Holland bool 275d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 276d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 277d421fd6dSSamuel Holland 278d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 279d421fd6dSSamuel Holland bool 280d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 281d421fd6dSSamuel Holland 282b06eb017SChristian Ruppertconfig TB10X_IRQC 283b06eb017SChristian Ruppert bool 284b06eb017SChristian Ruppert select IRQ_DOMAIN 285b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 286b06eb017SChristian Ruppert 287d01f8633SDamien Riegelconfig TS4800_IRQ 288d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 289d01f8633SDamien Riegel select IRQ_DOMAIN 2900df337cfSRichard Weinberger depends on HAS_IOMEM 291d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 292d01f8633SDamien Riegel help 293d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 294d01f8633SDamien Riegel 2952389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2962389d501SLinus Walleij bool 2972389d501SLinus Walleij select IRQ_DOMAIN 2982389d501SLinus Walleij 2992389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3002389d501SLinus Walleij int 3012389d501SLinus Walleij default 4 3022389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 30326a8e96aSMax Filippov 30426a8e96aSMax Filippovconfig XTENSA_MX 30526a8e96aSMax Filippov bool 30626a8e96aSMax Filippov select IRQ_DOMAIN 3070e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 30896ca848eSSricharan R 3090547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 310debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 311fd31000dSJamie Iles depends on OF_ADDRESS 3120547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 313debf69cfSRobert Hancock help 314debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 315debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 316debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3170547dc78SZubair Lutfullah Kakakhel 31896ca848eSSricharan Rconfig IRQ_CROSSBAR 31996ca848eSSricharan R bool 32096ca848eSSricharan R help 321f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 32296ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 32396ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 32496ca848eSSricharan R routed to one of the free irqchip interrupt lines. 32589323f8cSGrygorii Strashko 32689323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 32789323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 32889323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 32989323f8cSGrygorii Strashko help 33089323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 33189323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3328a19b8f1SAndrew Bresticker 3338a19b8f1SAndrew Brestickerconfig MIPS_GIC 3348a19b8f1SAndrew Bresticker bool 3358190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3368190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3378a19b8f1SAndrew Bresticker select MIPS_CM 3388a764482SYoshinori Sato 33944e08e70SPaul Burtonconfig INGENIC_IRQ 34044e08e70SPaul Burton bool 34144e08e70SPaul Burton depends on MACH_INGENIC 34244e08e70SPaul Burton default y 34378c10e55SLinus Torvalds 3449536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3459536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3469536eba0SPaul Cercueil default MACH_INGENIC 3479536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3489536eba0SPaul Cercueil select MFD_SYSCON 3498084499bSYueHaibing select GENERIC_IRQ_CHIP 3509536eba0SPaul Cercueil help 3519536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3529536eba0SPaul Cercueil JZ47xx SoCs. 3539536eba0SPaul Cercueil 3549536eba0SPaul Cercueil If unsure, say N. 3559536eba0SPaul Cercueil 356e324c4dcSShenwei Wangconfig IMX_GPCV2 357e324c4dcSShenwei Wang bool 358e324c4dcSShenwei Wang select IRQ_DOMAIN 359e324c4dcSShenwei Wang help 360e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3617e4ac676SOleksij Rempel 3627e4ac676SOleksij Rempelconfig IRQ_MXS 3637e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3647e4ac676SOleksij Rempel select IRQ_DOMAIN 3657e4ac676SOleksij Rempel select STMP_DEVICE 366c27f29bbSThomas Petazzoni 36719d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 36819d99164SAlexandre Belloni bool 36919d99164SAlexandre Belloni select IRQ_DOMAIN 37019d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 37119d99164SAlexandre Belloni 372a68a63cbSThomas Petazzoniconfig MVEBU_GICP 373a68a63cbSThomas Petazzoni bool 374a68a63cbSThomas Petazzoni 375e0de91a9SThomas Petazzoniconfig MVEBU_ICU 376e0de91a9SThomas Petazzoni bool 377e0de91a9SThomas Petazzoni 378c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 379c27f29bbSThomas Petazzoni bool 38013e7accbSThomas Gleixner select GENERIC_MSI_IRQ 3819e2c986cSMarc Zyngier 382a109893bSThomas Petazzoniconfig MVEBU_PIC 383a109893bSThomas Petazzoni bool 384a109893bSThomas Petazzoni 38561ce8d8dSMiquel Raynalconfig MVEBU_SEI 38661ce8d8dSMiquel Raynal bool 38761ce8d8dSMiquel Raynal 3880dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3890dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3900dcd9f87SRasmus Villemoes select MFD_SYSCON 3910dcd9f87SRasmus Villemoes 392b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 393b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3949c1a7bfcSLukas Bulwahn depends on PCI_MSI 395b8f3ebe6SMinghuan Lian 3969e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3979e2c986cSMarc Zyngier bool 3980efacbbaSLinus Torvalds 399e0720416SAlexandre TORGUEconfig STM32_EXTI 400e0720416SAlexandre TORGUE bool 401e0720416SAlexandre TORGUE select IRQ_DOMAIN 4020e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 403f20cc9b0SAgustin Vega-Frias 404f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 405f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 406f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 407f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 408f20cc9b0SAgustin Vega-Frias help 409f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 410f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4115ed34d3aSMasahiro Yamada 4125ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4135ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4145ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4155ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4165ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4175ed34d3aSMasahiro Yamada help 4185ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 419c94fb639SRandy Dunlap 420215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 421a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 422a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 423a947aa00SNeil Armstrong default ARCH_MESON 424215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 425215f4cc0SJerome Brunet help 426215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 427215f4cc0SJerome Brunet 4284235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4294235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4304235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 431969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4324235ff50SMiodrag Dinic select IRQ_DOMAIN 4334235ff50SMiodrag Dinic help 4344235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4354235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4364235ff50SMiodrag Dinic 437f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4384acd8a4bSSaravana Kannan tristate "QCOM PDC" 439f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 440f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 441f55c73aeSArchana Sathyakumar help 442f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 443f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 444f55c73aeSArchana Sathyakumar 445a6199bb5SShawn Guoconfig QCOM_MPM 446a6199bb5SShawn Guo tristate "QCOM MPM" 447a6199bb5SShawn Guo depends on ARCH_QCOM 448fa4dcc88SYueHaibing depends on MAILBOX 449a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 450a6199bb5SShawn Guo help 451a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 452a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 453a6199bb5SShawn Guo 454d8a5f5f7SGuo Renconfig CSKY_MPINTC 455be1abc5bSGuo Ren bool 456d8a5f5f7SGuo Ren depends on CSKY 457d8a5f5f7SGuo Ren help 458d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 459d8a5f5f7SGuo Ren for C-SKY SMP system. 460656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 461d8a5f5f7SGuo Ren controller's register inside CPU. 462d8a5f5f7SGuo Ren 463edff1b48SGuo Renconfig CSKY_APB_INTC 464edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 465edff1b48SGuo Ren depends on CSKY 466edff1b48SGuo Ren help 467edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 468656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 469edff1b48SGuo Ren the controller's register. 470edff1b48SGuo Ren 4710136afa0SLucas Stachconfig IMX_IRQSTEER 4720136afa0SLucas Stach bool "i.MX IRQSTEER support" 4730136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4740136afa0SLucas Stach default ARCH_MXC 4750136afa0SLucas Stach select IRQ_DOMAIN 4760136afa0SLucas Stach help 4770136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4780136afa0SLucas Stach 4792fbb1396SJoakim Zhangconfig IMX_INTMUX 480a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 481a890caebSGeert Uytterhoeven default y if ARCH_MXC 4822fbb1396SJoakim Zhang select IRQ_DOMAIN 4832fbb1396SJoakim Zhang help 4842fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4852fbb1396SJoakim Zhang 48670afdab9SFrank Liconfig IMX_MU_MSI 48770afdab9SFrank Li tristate "i.MX MU used as MSI controller" 48870afdab9SFrank Li depends on OF && HAS_IOMEM 4896c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 49070afdab9SFrank Li default m if ARCH_MXC 49170afdab9SFrank Li select IRQ_DOMAIN 49270afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 49313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 49470afdab9SFrank Li help 4956c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 4966c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 4976c9f7434SGeert Uytterhoeven to make use of this driver. 49870afdab9SFrank Li 49970afdab9SFrank Li If unsure, say N 50070afdab9SFrank Li 5019e543e22SJiaxun Yangconfig LS1X_IRQ 5029e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5039e543e22SJiaxun Yang depends on MACH_LOONGSON32 5049e543e22SJiaxun Yang default y 5059e543e22SJiaxun Yang select IRQ_DOMAIN 5069e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5079e543e22SJiaxun Yang help 5089e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5099e543e22SJiaxun Yang 510cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 511cd844b07SLokesh Vutla bool 512cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 513cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 514cd844b07SLokesh Vutla help 515cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 516cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 517cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 518cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 519cd844b07SLokesh Vutla 5209f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5219f1463b8SLokesh Vutla bool 5229f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5239f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 524f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5259f1463b8SLokesh Vutla help 5269f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5279f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5289f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5299f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5309f1463b8SLokesh Vutla 53104e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 532b8e594faSSuman Anna tristate 533b8e594faSSuman Anna depends on TI_PRUSS 534b8e594faSSuman Anna default TI_PRUSS 53504e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 53604e2d1e0SGrzegorz Jaszczyk help 53704e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 53804e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 53904e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 54004e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 54104e2d1e0SGrzegorz Jaszczyk 5426b7ce892SAnup Patelconfig RISCV_INTC 543d8fb1307SConor Dooley bool 5446b7ce892SAnup Patel depends on RISCV 545832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5466b7ce892SAnup Patel 5472333df5aSAnup Patelconfig RISCV_APLIC 5482333df5aSAnup Patel bool 5492333df5aSAnup Patel depends on RISCV 5502333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 5512333df5aSAnup Patel 552ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 553ca8df97fSAnup Patel bool 554ca8df97fSAnup Patel depends on RISCV_APLIC 555ca8df97fSAnup Patel select GENERIC_MSI_IRQ 556ca8df97fSAnup Patel default RISCV_APLIC 557ca8df97fSAnup Patel 55821a8f8a0SAnup Patelconfig RISCV_IMSIC 55921a8f8a0SAnup Patel bool 56021a8f8a0SAnup Patel depends on RISCV 56121a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 56221a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 56321a8f8a0SAnup Patel select GENERIC_MSI_IRQ 56421a8f8a0SAnup Patel 5655c5a71d0SAnup Patelconfig RISCV_IMSIC_PCI 5665c5a71d0SAnup Patel bool 5675c5a71d0SAnup Patel depends on RISCV_IMSIC 5685c5a71d0SAnup Patel depends on PCI 5695c5a71d0SAnup Patel depends on PCI_MSI 5705c5a71d0SAnup Patel default RISCV_IMSIC 5715c5a71d0SAnup Patel 5728237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 573fdb1742aSConor Dooley bool 5748237f8bcSChristoph Hellwig depends on RISCV 575466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 576de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 57701493855SJonathan Neuschäfer 578e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 579e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 580e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 581e4e53503SChanghuang Liang default ARCH_STARFIVE 582e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 583e4e53503SChanghuang Liang help 584e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 585e4e53503SChanghuang Liang SoC. 586e4e53503SChanghuang Liang 587e4e53503SChanghuang Liang If you don't know what to do here, say Y. 588e4e53503SChanghuang Liang 589b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 590b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 591b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 592b74416dbSHyunki Koo help 593b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 594b74416dbSHyunki Koo in Samsung Exynos chips. 595b74416dbSHyunki Koo 596b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 597b2d3e335SHuacai Chen bool 598b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 599b2d3e335SHuacai Chen select IRQ_DOMAIN 60042a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 60170f7b6c0SHuacai Chen select LOONGSON_HTVEC 6028d5356f9SHuacai Chen select LOONGSON_LIOINTC 6038d5356f9SHuacai Chen select LOONGSON_EIOINTC 6048d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6058d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6068d5356f9SHuacai Chen select LOONGSON_PCH_LPC 607b2d3e335SHuacai Chen help 608b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 609b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 61051712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 611b2d3e335SHuacai Chen 612dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 613dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 614dbb15226SJiaxun Yang depends on MACH_LOONGSON64 615dbb15226SJiaxun Yang default y 616dbb15226SJiaxun Yang select IRQ_DOMAIN 617dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 618dbb15226SJiaxun Yang help 619dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 620dbb15226SJiaxun Yang 621dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 622dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 623dd281e1aSHuacai Chen depends on LOONGARCH 624dd281e1aSHuacai Chen depends on MACH_LOONGSON64 625dd281e1aSHuacai Chen default MACH_LOONGSON64 626dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 627dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 628dd281e1aSHuacai Chen help 629dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 630dd281e1aSHuacai Chen 631a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 632a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 633987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 634a93f1d90SJiaxun Yang default y 635a93f1d90SJiaxun Yang select IRQ_DOMAIN 636a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 637a93f1d90SJiaxun Yang help 638a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 639a93f1d90SJiaxun Yang 640818e915fSJiaxun Yangconfig LOONGSON_HTVEC 641987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 642d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 643818e915fSJiaxun Yang default MACH_LOONGSON64 644818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 645818e915fSJiaxun Yang help 646987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 647818e915fSJiaxun Yang 648ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 649ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 650bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 651ef8c01ebSJiaxun Yang default MACH_LOONGSON64 652ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 653ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 654ef8c01ebSJiaxun Yang help 655ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 656ef8c01ebSJiaxun Yang 657632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 658a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 65902308732SHuacai Chen depends on MACH_LOONGSON64 660632dcc2cSJiaxun Yang depends on PCI 661632dcc2cSJiaxun Yang default MACH_LOONGSON64 662632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 663632dcc2cSJiaxun Yang select PCI_MSI 664632dcc2cSJiaxun Yang help 665632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 666632dcc2cSJiaxun Yang 667ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 668ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 669e7ccba77SJianmin Lv depends on LOONGARCH 670ee73f14eSHuacai Chen depends on MACH_LOONGSON64 671e7ccba77SJianmin Lv default MACH_LOONGSON64 672ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 673ee73f14eSHuacai Chen help 674ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 675ee73f14eSHuacai Chen 676ad4c938cSMark-PK Tsaiconfig MST_IRQ 677ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 67861b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 679ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 680ad4c938cSMark-PK Tsai select IRQ_DOMAIN 681ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 682ad4c938cSMark-PK Tsai help 683ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 684ad4c938cSMark-PK Tsai 685fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 686fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 68794bc9420SMarc Zyngier depends on ARCH_WPCM450 688fead4dd4SJonathan Neuschäfer help 689fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 690fead4dd4SJonathan Neuschäfer 691529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 692529ea368SThomas Bogendoerfer bool 693529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 694529ea368SThomas Bogendoerfer select IRQ_DOMAIN 695529ea368SThomas Bogendoerfer 69676cde263SHector Martinconfig APPLE_AIC 69776cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 69876cde263SHector Martin depends on ARM64 6995b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 700c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 70176cde263SHector Martin help 70276cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 70376cde263SHector Martin such as the M1. 70476cde263SHector Martin 70500fa3461SClaudiu Bezneaconfig MCHP_EIC 70600fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 70700fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 70800fa3461SClaudiu Beznea select IRQ_DOMAIN 70900fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 71000fa3461SClaudiu Beznea help 71100fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 71200fa3461SClaudiu Beznea 713f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 714f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 715f7189d93SQin Jian default SOC_SP7021 716f7189d93SQin Jian help 717f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 718f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 719f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 720f7189d93SQin Jian the primary controller on C-Chip. 721f7189d93SQin Jian 72201493855SJonathan Neuschäferendmenu 723