1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 31853a33ceSSuravee Suthikulpanit 3281243e44SRob Herringconfig GIC_NON_BANKED 3381243e44SRob Herring bool 3481243e44SRob Herring 35021f6537SMarc Zyngierconfig ARM_GIC_V3 36021f6537SMarc Zyngier bool 37443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 38e3825ba1SMarc Zyngier select PARTITION_PERCPU 390e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4035727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 41021f6537SMarc Zyngier 4219812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4319812729SMarc Zyngier bool 4413e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4548f71d56SThomas Gleixner select IRQ_MSI_LIB 4629f41139SMarc Zyngier default ARM_GIC_V3 4729f41139SMarc Zyngier 4829f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4929f41139SMarc Zyngier bool 5029f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 513ee80364SArnd Bergmann depends on PCI 523ee80364SArnd Bergmann depends on PCI_MSI 5329f41139SMarc Zyngier default ARM_GIC_V3_ITS 54292ec080SUwe Kleine-König 557afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 567afe031cSBogdan Purcareata bool 577afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata depends on FSL_MC_BUS 597afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 607afe031cSBogdan Purcareata 6144430ec0SRob Herringconfig ARM_NVIC 6244430ec0SRob Herring bool 632d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6444430ec0SRob Herring select GENERIC_IRQ_CHIP 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC 6744430ec0SRob Herring bool 6844430ec0SRob Herring select IRQ_DOMAIN 6944430ec0SRob Herring 7044430ec0SRob Herringconfig ARM_VIC_NR 7144430ec0SRob Herring int 7244430ec0SRob Herring default 4 if ARCH_S5PV210 7344430ec0SRob Herring default 2 7444430ec0SRob Herring depends on ARM_VIC 7544430ec0SRob Herring help 7644430ec0SRob Herring The maximum number of VICs available in the system, for 7744430ec0SRob Herring power management. 7844430ec0SRob Herring 7972e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 8072e257c6SThomas Gleixner bool 8172e257c6SThomas Gleixner 82fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 83fed6d336SThomas Petazzoni bool 84fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 853ee80364SArnd Bergmann select PCI_MSI if PCI 860e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 87fed6d336SThomas Petazzoni 88e6b78f2cSAntoine Tenartconfig ALPINE_MSI 89e6b78f2cSAntoine Tenart bool 903ee80364SArnd Bergmann depends on PCI 913ee80364SArnd Bergmann select PCI_MSI 92e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 93e6b78f2cSAntoine Tenart 941eb77c3bSTalel Shenharconfig AL_FIC 951eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 969869f37aSJean Delvare depends on OF 9735e0cd77SBaoquan He depends on HAS_IOMEM 981eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 991eb77c3bSTalel Shenhar select IRQ_DOMAIN 1001eb77c3bSTalel Shenhar help 1011eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1021eb77c3bSTalel Shenhar 103b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 104b1479ebbSBoris BREZILLON bool 105b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 106b1479ebbSBoris BREZILLON select IRQ_DOMAIN 107b1479ebbSBoris BREZILLON select SPARSE_IRQ 108b1479ebbSBoris BREZILLON 109b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 110b1479ebbSBoris BREZILLON bool 111b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 112b1479ebbSBoris BREZILLON select IRQ_DOMAIN 113b1479ebbSBoris BREZILLON select SPARSE_IRQ 114b1479ebbSBoris BREZILLON 1150509cfdeSRalf Baechleconfig I8259 1160509cfdeSRalf Baechle bool 1170509cfdeSRalf Baechle select IRQ_DOMAIN 1180509cfdeSRalf Baechle 119c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 120c7c42ec2SSimon Arlott bool 121c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 122c7c42ec2SSimon Arlott select IRQ_DOMAIN 1230e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 124c7c42ec2SSimon Arlott 1255f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 126c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 127c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 128c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1295f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1305f7f0317SKevin Cernekee select IRQ_DOMAIN 1310e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1325f7f0317SKevin Cernekee 133a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1343ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1353ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1363ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 137a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 138a4fcbb86SKevin Cernekee select IRQ_DOMAIN 139a4fcbb86SKevin Cernekee 1407f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 14151d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 14251d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 14351d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1447f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1457f646e92SFlorian Fainelli select IRQ_DOMAIN 1467f646e92SFlorian Fainelli 1470fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1480fc3d74cSBartosz Golaszewski bool 1490fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1500fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1510fc3d74cSBartosz Golaszewski 152350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 153be5e5f3aSThomas Gleixner bool 154e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15554a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 156350d71b9SSebastian Hesselbarth 1576ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1586ee532e2SLinus Walleij bool 1596ee532e2SLinus Walleij select IRQ_DOMAIN 1606ee532e2SLinus Walleij select SPARSE_IRQ 1616ee532e2SLinus Walleij 1629a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1639a7c4abdSMaJun bool 1649a7c4abdSMaJun select ARM_GIC_V3 1659a7c4abdSMaJun select ARM_GIC_V3_ITS 1669a7c4abdSMaJun 167b6ef9161SJames Hoganconfig IMGPDC_IRQ 168b6ef9161SJames Hogan bool 169b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 170b6ef9161SJames Hogan select IRQ_DOMAIN 171b6ef9161SJames Hogan 1725b978c10SLinus Walleijconfig IXP4XX_IRQ 1735b978c10SLinus Walleij bool 1745b978c10SLinus Walleij select IRQ_DOMAIN 1755b978c10SLinus Walleij select SPARSE_IRQ 1765b978c10SLinus Walleij 1773e3a7b35SHerve Codinaconfig LAN966X_OIC 1783e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 1793e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 1803e3a7b35SHerve Codina select IRQ_DOMAIN 1813e3a7b35SHerve Codina help 1823e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 1833e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 1843e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 1853e3a7b35SHerve Codina 1863e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 1873e3a7b35SHerve Codina will be called irq-lan966x-oic. 1883e3a7b35SHerve Codina 189da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 190da0abe1aSRichard Fitzgerald tristate 191da0abe1aSRichard Fitzgerald 19267e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 19367e38cf2SRalf Baechle bool 19467e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1950f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 19667e38cf2SRalf Baechle select IRQ_DOMAIN 1970e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 19867e38cf2SRalf Baechle 199afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 200afc98d90SAlexander Shiyan bool 201afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 202afc98d90SAlexander Shiyan select IRQ_DOMAIN 203afc98d90SAlexander Shiyan select SPARSE_IRQ 204afc98d90SAlexander Shiyan default y 205afc98d90SAlexander Shiyan 2069b54470aSStafford Horneconfig OMPIC 2079b54470aSStafford Horne bool 2089b54470aSStafford Horne 2094db8e6d2SStefan Kristianssonconfig OR1K_PIC 2104db8e6d2SStefan Kristiansson bool 2114db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2124db8e6d2SStefan Kristiansson 2138598066cSFelipe Balbiconfig OMAP_IRQCHIP 2148598066cSFelipe Balbi bool 2158598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2168598066cSFelipe Balbi select IRQ_DOMAIN 2178598066cSFelipe Balbi 2189dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2199dbd90f1SSebastian Hesselbarth bool 2209dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2219dbd90f1SSebastian Hesselbarth 222aaa8666aSCristian Birsanconfig PIC32_EVIC 223aaa8666aSCristian Birsan bool 224aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 225aaa8666aSCristian Birsan select IRQ_DOMAIN 226aaa8666aSCristian Birsan 227981b58f6SRich Felkerconfig JCORE_AIC 2283602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2293602ffdeSRich Felker depends on OF 230981b58f6SRich Felker select IRQ_DOMAIN 231981b58f6SRich Felker help 232981b58f6SRich Felker Support for the J-Core integrated AIC. 233981b58f6SRich Felker 234d852e62aSManivannan Sadhasivamconfig RDA_INTC 235d852e62aSManivannan Sadhasivam bool 236d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 237d852e62aSManivannan Sadhasivam 23844358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 23902d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 24044358048SMagnus Damm select IRQ_DOMAIN 24102d7e041SGeert Uytterhoeven help 24202d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 24302d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 24444358048SMagnus Damm 245fbc83b7fSMagnus Dammconfig RENESAS_IRQC 24672d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 24799c221dfSMagnus Damm select GENERIC_IRQ_CHIP 248fbc83b7fSMagnus Damm select IRQ_DOMAIN 24902d7e041SGeert Uytterhoeven help 25002d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 25172d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 252fbc83b7fSMagnus Damm 253a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 25402d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 255a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 25602d7e041SGeert Uytterhoeven help 25702d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 25802d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 259a644ccb8SGeert Uytterhoeven 2603fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2613fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2623fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2633fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2643fed0955SLad Prabhakar help 2653fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2663fed0955SLad Prabhakar for external devices. 2673fed0955SLad Prabhakar 26803ac990eSMichael Walleconfig SL28CPLD_INTC 26903ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 27003ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 27103ac990eSMichael Walle select REGMAP_IRQ 27203ac990eSMichael Walle help 27303ac990eSMichael Walle Interrupt controller driver for the board management controller 27403ac990eSMichael Walle found on the Kontron sl28 CPLD. 27503ac990eSMichael Walle 27607088484SLee Jonesconfig ST_IRQCHIP 27707088484SLee Jones bool 27807088484SLee Jones select REGMAP 27907088484SLee Jones select MFD_SYSCON 28007088484SLee Jones help 28107088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 28207088484SLee Jones 283d421fd6dSSamuel Hollandconfig SUN4I_INTC 284d421fd6dSSamuel Holland bool 285d421fd6dSSamuel Holland 286d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 287d421fd6dSSamuel Holland bool 288d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 289d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 290d421fd6dSSamuel Holland 291d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 292d421fd6dSSamuel Holland bool 293d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 294d421fd6dSSamuel Holland 295b06eb017SChristian Ruppertconfig TB10X_IRQC 296b06eb017SChristian Ruppert bool 297b06eb017SChristian Ruppert select IRQ_DOMAIN 298b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 299b06eb017SChristian Ruppert 300d01f8633SDamien Riegelconfig TS4800_IRQ 301d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 302d01f8633SDamien Riegel select IRQ_DOMAIN 3030df337cfSRichard Weinberger depends on HAS_IOMEM 304d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 305d01f8633SDamien Riegel help 306d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 307d01f8633SDamien Riegel 3082389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3092389d501SLinus Walleij bool 3102389d501SLinus Walleij select IRQ_DOMAIN 3112389d501SLinus Walleij 3122389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3132389d501SLinus Walleij int 3142389d501SLinus Walleij default 4 3152389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 31626a8e96aSMax Filippov 31726a8e96aSMax Filippovconfig XTENSA_MX 31826a8e96aSMax Filippov bool 31926a8e96aSMax Filippov select IRQ_DOMAIN 3200e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 32196ca848eSSricharan R 3220547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 323debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 324fd31000dSJamie Iles depends on OF_ADDRESS 3250547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 326debf69cfSRobert Hancock help 327debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 328debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 329debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3300547dc78SZubair Lutfullah Kakakhel 33196ca848eSSricharan Rconfig IRQ_CROSSBAR 33296ca848eSSricharan R bool 33396ca848eSSricharan R help 334f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 33596ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 33696ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 33796ca848eSSricharan R routed to one of the free irqchip interrupt lines. 33889323f8cSGrygorii Strashko 33989323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 34089323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 34189323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 34289323f8cSGrygorii Strashko help 34389323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 34489323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3458a19b8f1SAndrew Bresticker 3468a19b8f1SAndrew Brestickerconfig MIPS_GIC 3478a19b8f1SAndrew Bresticker bool 3488190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3498190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3508a19b8f1SAndrew Bresticker select MIPS_CM 3518a764482SYoshinori Sato 35244e08e70SPaul Burtonconfig INGENIC_IRQ 35344e08e70SPaul Burton bool 35444e08e70SPaul Burton depends on MACH_INGENIC 35544e08e70SPaul Burton default y 35678c10e55SLinus Torvalds 3579536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3589536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3599536eba0SPaul Cercueil default MACH_INGENIC 3609536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3619536eba0SPaul Cercueil select MFD_SYSCON 3628084499bSYueHaibing select GENERIC_IRQ_CHIP 3639536eba0SPaul Cercueil help 3649536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3659536eba0SPaul Cercueil JZ47xx SoCs. 3669536eba0SPaul Cercueil 3679536eba0SPaul Cercueil If unsure, say N. 3689536eba0SPaul Cercueil 369e324c4dcSShenwei Wangconfig IMX_GPCV2 370e324c4dcSShenwei Wang bool 371e324c4dcSShenwei Wang select IRQ_DOMAIN 372e324c4dcSShenwei Wang help 373e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3747e4ac676SOleksij Rempel 3757e4ac676SOleksij Rempelconfig IRQ_MXS 3767e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3777e4ac676SOleksij Rempel select IRQ_DOMAIN 3787e4ac676SOleksij Rempel select STMP_DEVICE 379c27f29bbSThomas Petazzoni 38019d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 38119d99164SAlexandre Belloni bool 38219d99164SAlexandre Belloni select IRQ_DOMAIN 38319d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 38419d99164SAlexandre Belloni 385a68a63cbSThomas Petazzoniconfig MVEBU_GICP 386cdb23872SThomas Gleixner select IRQ_MSI_LIB 387a68a63cbSThomas Petazzoni bool 388a68a63cbSThomas Petazzoni 389e0de91a9SThomas Petazzoniconfig MVEBU_ICU 390e0de91a9SThomas Petazzoni bool 391e0de91a9SThomas Petazzoni 392c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 393c27f29bbSThomas Petazzoni bool 394e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 39513e7accbSThomas Gleixner select GENERIC_MSI_IRQ 3969e2c986cSMarc Zyngier 397a109893bSThomas Petazzoniconfig MVEBU_PIC 398a109893bSThomas Petazzoni bool 399a109893bSThomas Petazzoni 40061ce8d8dSMiquel Raynalconfig MVEBU_SEI 40161ce8d8dSMiquel Raynal bool 40261ce8d8dSMiquel Raynal 4030dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4040dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4050dcd9f87SRasmus Villemoes select MFD_SYSCON 4060dcd9f87SRasmus Villemoes 407b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 408b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4099c1a7bfcSLukas Bulwahn depends on PCI_MSI 410b8f3ebe6SMinghuan Lian 4119e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4129e2c986cSMarc Zyngier bool 4130efacbbaSLinus Torvalds 414b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4150be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4160be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4170be58e05SAntonio Borneo default y 4180be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 419350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4200be58e05SAntonio Borneo help 4210be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 422b20cf2dcSAntonio Borneo 423e0720416SAlexandre TORGUEconfig STM32_EXTI 424e0720416SAlexandre TORGUE bool 425e0720416SAlexandre TORGUE select IRQ_DOMAIN 4260e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 427f20cc9b0SAgustin Vega-Frias 428f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 429f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 430f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 431f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 432f20cc9b0SAgustin Vega-Frias help 433f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 434f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4355ed34d3aSMasahiro Yamada 4365ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4375ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4385ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4395ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4405ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4415ed34d3aSMasahiro Yamada help 4425ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 443c94fb639SRandy Dunlap 444215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 445a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 446a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 447a947aa00SNeil Armstrong default ARCH_MESON 448215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 449215f4cc0SJerome Brunet help 450215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 451215f4cc0SJerome Brunet 4524235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4534235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4544235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 455969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4564235ff50SMiodrag Dinic select IRQ_DOMAIN 4574235ff50SMiodrag Dinic help 4584235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4594235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4604235ff50SMiodrag Dinic 461f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4624acd8a4bSSaravana Kannan tristate "QCOM PDC" 463f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 464f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 465f55c73aeSArchana Sathyakumar help 466f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 467f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 468f55c73aeSArchana Sathyakumar 469a6199bb5SShawn Guoconfig QCOM_MPM 470a6199bb5SShawn Guo tristate "QCOM MPM" 471a6199bb5SShawn Guo depends on ARCH_QCOM 472fa4dcc88SYueHaibing depends on MAILBOX 473a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 474a6199bb5SShawn Guo help 475a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 476a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 477a6199bb5SShawn Guo 478d8a5f5f7SGuo Renconfig CSKY_MPINTC 479be1abc5bSGuo Ren bool 480d8a5f5f7SGuo Ren depends on CSKY 481d8a5f5f7SGuo Ren help 482d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 483d8a5f5f7SGuo Ren for C-SKY SMP system. 484656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 485d8a5f5f7SGuo Ren controller's register inside CPU. 486d8a5f5f7SGuo Ren 487edff1b48SGuo Renconfig CSKY_APB_INTC 488edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 489edff1b48SGuo Ren depends on CSKY 490edff1b48SGuo Ren help 491edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 492656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 493edff1b48SGuo Ren the controller's register. 494edff1b48SGuo Ren 4950136afa0SLucas Stachconfig IMX_IRQSTEER 4960136afa0SLucas Stach bool "i.MX IRQSTEER support" 4970136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4980136afa0SLucas Stach default ARCH_MXC 4990136afa0SLucas Stach select IRQ_DOMAIN 5000136afa0SLucas Stach help 5010136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5020136afa0SLucas Stach 5032fbb1396SJoakim Zhangconfig IMX_INTMUX 504a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 505a890caebSGeert Uytterhoeven default y if ARCH_MXC 5062fbb1396SJoakim Zhang select IRQ_DOMAIN 5072fbb1396SJoakim Zhang help 5082fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5092fbb1396SJoakim Zhang 51070afdab9SFrank Liconfig IMX_MU_MSI 51170afdab9SFrank Li tristate "i.MX MU used as MSI controller" 51270afdab9SFrank Li depends on OF && HAS_IOMEM 5136c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 51470afdab9SFrank Li default m if ARCH_MXC 51570afdab9SFrank Li select IRQ_DOMAIN 51670afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 51713e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5187b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 51970afdab9SFrank Li help 5206c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5216c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5226c9f7434SGeert Uytterhoeven to make use of this driver. 52370afdab9SFrank Li 52470afdab9SFrank Li If unsure, say N 52570afdab9SFrank Li 5269e543e22SJiaxun Yangconfig LS1X_IRQ 5279e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5289e543e22SJiaxun Yang depends on MACH_LOONGSON32 5299e543e22SJiaxun Yang default y 5309e543e22SJiaxun Yang select IRQ_DOMAIN 5319e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5329e543e22SJiaxun Yang help 5339e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5349e543e22SJiaxun Yang 535cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 536cd844b07SLokesh Vutla bool 537cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 538cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 539cd844b07SLokesh Vutla help 540cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 541cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 542cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 543cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 544cd844b07SLokesh Vutla 5459f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5469f1463b8SLokesh Vutla bool 5479f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5489f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 549f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5509f1463b8SLokesh Vutla help 5519f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5529f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5539f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5549f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5559f1463b8SLokesh Vutla 55604e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 557b8e594faSSuman Anna tristate 558b8e594faSSuman Anna depends on TI_PRUSS 559b8e594faSSuman Anna default TI_PRUSS 56004e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 56104e2d1e0SGrzegorz Jaszczyk help 56204e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 56304e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 56404e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 56504e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 56604e2d1e0SGrzegorz Jaszczyk 5676b7ce892SAnup Patelconfig RISCV_INTC 568d8fb1307SConor Dooley bool 5696b7ce892SAnup Patel depends on RISCV 570832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5716b7ce892SAnup Patel 5722333df5aSAnup Patelconfig RISCV_APLIC 5732333df5aSAnup Patel bool 5742333df5aSAnup Patel depends on RISCV 5752333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 5762333df5aSAnup Patel 577ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 578ca8df97fSAnup Patel bool 579ca8df97fSAnup Patel depends on RISCV_APLIC 580ca8df97fSAnup Patel select GENERIC_MSI_IRQ 581ca8df97fSAnup Patel default RISCV_APLIC 582ca8df97fSAnup Patel 58321a8f8a0SAnup Patelconfig RISCV_IMSIC 58421a8f8a0SAnup Patel bool 58521a8f8a0SAnup Patel depends on RISCV 58621a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 58721a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 58821a8f8a0SAnup Patel select GENERIC_MSI_IRQ 58921a8f8a0SAnup Patel 5905c5a71d0SAnup Patelconfig RISCV_IMSIC_PCI 5915c5a71d0SAnup Patel bool 5925c5a71d0SAnup Patel depends on RISCV_IMSIC 5935c5a71d0SAnup Patel depends on PCI 5945c5a71d0SAnup Patel depends on PCI_MSI 5955c5a71d0SAnup Patel default RISCV_IMSIC 5965c5a71d0SAnup Patel 5978237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 598fdb1742aSConor Dooley bool 5998237f8bcSChristoph Hellwig depends on RISCV 600466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 601de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 60201493855SJonathan Neuschäfer 603e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 604e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 605e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 606e4e53503SChanghuang Liang default ARCH_STARFIVE 607e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 608e4e53503SChanghuang Liang help 609e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 610e4e53503SChanghuang Liang SoC. 611e4e53503SChanghuang Liang 612e4e53503SChanghuang Liang If you don't know what to do here, say Y. 613e4e53503SChanghuang Liang 614b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 615b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 616b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 617b74416dbSHyunki Koo help 618b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 619b74416dbSHyunki Koo in Samsung Exynos chips. 620b74416dbSHyunki Koo 621b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 622b2d3e335SHuacai Chen bool 623b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 624b2d3e335SHuacai Chen select IRQ_DOMAIN 62542a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 62670f7b6c0SHuacai Chen select LOONGSON_HTVEC 6278d5356f9SHuacai Chen select LOONGSON_LIOINTC 6288d5356f9SHuacai Chen select LOONGSON_EIOINTC 6298d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6308d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6318d5356f9SHuacai Chen select LOONGSON_PCH_LPC 632b2d3e335SHuacai Chen help 633b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 634b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 63551712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 636b2d3e335SHuacai Chen 637dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 638dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 639dbb15226SJiaxun Yang depends on MACH_LOONGSON64 640dbb15226SJiaxun Yang default y 641dbb15226SJiaxun Yang select IRQ_DOMAIN 642dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 643dbb15226SJiaxun Yang help 644dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 645dbb15226SJiaxun Yang 646dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 647dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 648dd281e1aSHuacai Chen depends on LOONGARCH 649dd281e1aSHuacai Chen depends on MACH_LOONGSON64 650dd281e1aSHuacai Chen default MACH_LOONGSON64 651dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 652dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 653dd281e1aSHuacai Chen help 654dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 655dd281e1aSHuacai Chen 656a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 657a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 658987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 659a93f1d90SJiaxun Yang default y 660a93f1d90SJiaxun Yang select IRQ_DOMAIN 661a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 662a93f1d90SJiaxun Yang help 663a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 664a93f1d90SJiaxun Yang 665818e915fSJiaxun Yangconfig LOONGSON_HTVEC 666987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 667d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 668818e915fSJiaxun Yang default MACH_LOONGSON64 669818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 670818e915fSJiaxun Yang help 671987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 672818e915fSJiaxun Yang 673ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 674ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 675bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 676ef8c01ebSJiaxun Yang default MACH_LOONGSON64 677ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 678ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 679ef8c01ebSJiaxun Yang help 680ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 681ef8c01ebSJiaxun Yang 682632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 683a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 68402308732SHuacai Chen depends on MACH_LOONGSON64 685632dcc2cSJiaxun Yang depends on PCI 686632dcc2cSJiaxun Yang default MACH_LOONGSON64 687632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 688*0b3af759SHuacai Chen select IRQ_MSI_LIB 689632dcc2cSJiaxun Yang select PCI_MSI 690632dcc2cSJiaxun Yang help 691632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 692632dcc2cSJiaxun Yang 693ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 694ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 695e7ccba77SJianmin Lv depends on LOONGARCH 696ee73f14eSHuacai Chen depends on MACH_LOONGSON64 697e7ccba77SJianmin Lv default MACH_LOONGSON64 698ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 699ee73f14eSHuacai Chen help 700ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 701ee73f14eSHuacai Chen 702ad4c938cSMark-PK Tsaiconfig MST_IRQ 703ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 70461b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 705ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 706ad4c938cSMark-PK Tsai select IRQ_DOMAIN 707ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 708ad4c938cSMark-PK Tsai help 709ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 710ad4c938cSMark-PK Tsai 711fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 712fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 71394bc9420SMarc Zyngier depends on ARCH_WPCM450 714fead4dd4SJonathan Neuschäfer help 715fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 716fead4dd4SJonathan Neuschäfer 717529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 718529ea368SThomas Bogendoerfer bool 719529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 720529ea368SThomas Bogendoerfer select IRQ_DOMAIN 721529ea368SThomas Bogendoerfer 72276cde263SHector Martinconfig APPLE_AIC 72376cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 72476cde263SHector Martin depends on ARM64 7255b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 726c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 72776cde263SHector Martin help 72876cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 72976cde263SHector Martin such as the M1. 73076cde263SHector Martin 73100fa3461SClaudiu Bezneaconfig MCHP_EIC 73200fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 73300fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 73400fa3461SClaudiu Beznea select IRQ_DOMAIN 73500fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 73600fa3461SClaudiu Beznea help 73700fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 73800fa3461SClaudiu Beznea 739f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 740f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 741f7189d93SQin Jian default SOC_SP7021 742f7189d93SQin Jian help 743f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 744f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 745f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 746f7189d93SQin Jian the primary controller on C-Chip. 747f7189d93SQin Jian 74801493855SJonathan Neuschäferendmenu 749