1c94fb639SRandy Dunlapmenu "IRQ chip support" 2c94fb639SRandy Dunlap 3f6e916b8SThomas Petazzoniconfig IRQCHIP 4f6e916b8SThomas Petazzoni def_bool y 5f6e916b8SThomas Petazzoni depends on OF_IRQ 6f6e916b8SThomas Petazzoni 781243e44SRob Herringconfig ARM_GIC 881243e44SRob Herring bool 981243e44SRob Herring select IRQ_DOMAIN 109a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 114f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 120c9e4982SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter select PM_CLK 199c8edddfSJon Hunter 20a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 21a27d21e0SLinus Walleij int 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 293ee80364SArnd Bergmann select PCI_MSI 30853a33ceSSuravee Suthikulpanit 3181243e44SRob Herringconfig GIC_NON_BANKED 3281243e44SRob Herring bool 3381243e44SRob Herring 34021f6537SMarc Zyngierconfig ARM_GIC_V3 35021f6537SMarc Zyngier bool 36021f6537SMarc Zyngier select IRQ_DOMAIN 374f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 40956ae91aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 41021f6537SMarc Zyngier 4219812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4319812729SMarc Zyngier bool 4429f41139SMarc Zyngier select GENERIC_MSI_IRQ_DOMAIN 4529f41139SMarc Zyngier default ARM_GIC_V3 4629f41139SMarc Zyngier 4729f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4829f41139SMarc Zyngier bool 4929f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 503ee80364SArnd Bergmann depends on PCI 513ee80364SArnd Bergmann depends on PCI_MSI 5229f41139SMarc Zyngier default ARM_GIC_V3_ITS 53292ec080SUwe Kleine-König 547afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 557afe031cSBogdan Purcareata bool 567afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 577afe031cSBogdan Purcareata depends on FSL_MC_BUS 587afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 597afe031cSBogdan Purcareata 6044430ec0SRob Herringconfig ARM_NVIC 6144430ec0SRob Herring bool 6244430ec0SRob Herring select IRQ_DOMAIN 632d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6444430ec0SRob Herring select GENERIC_IRQ_CHIP 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC 6744430ec0SRob Herring bool 6844430ec0SRob Herring select IRQ_DOMAIN 694f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 7044430ec0SRob Herring 7144430ec0SRob Herringconfig ARM_VIC_NR 7244430ec0SRob Herring int 7344430ec0SRob Herring default 4 if ARCH_S5PV210 7444430ec0SRob Herring default 2 7544430ec0SRob Herring depends on ARM_VIC 7644430ec0SRob Herring help 7744430ec0SRob Herring The maximum number of VICs available in the system, for 7844430ec0SRob Herring power management. 7944430ec0SRob Herring 80fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 81fed6d336SThomas Petazzoni bool 82fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 833ee80364SArnd Bergmann select PCI_MSI if PCI 84e31793a3SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 85fed6d336SThomas Petazzoni 86e6b78f2cSAntoine Tenartconfig ALPINE_MSI 87e6b78f2cSAntoine Tenart bool 883ee80364SArnd Bergmann depends on PCI 893ee80364SArnd Bergmann select PCI_MSI 90e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 91e6b78f2cSAntoine Tenart 92b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 93b1479ebbSBoris BREZILLON bool 94b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 95b1479ebbSBoris BREZILLON select IRQ_DOMAIN 964f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 97b1479ebbSBoris BREZILLON select SPARSE_IRQ 98b1479ebbSBoris BREZILLON 99b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 100b1479ebbSBoris BREZILLON bool 101b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 102b1479ebbSBoris BREZILLON select IRQ_DOMAIN 1034f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 104b1479ebbSBoris BREZILLON select SPARSE_IRQ 105b1479ebbSBoris BREZILLON 1060509cfdeSRalf Baechleconfig I8259 1070509cfdeSRalf Baechle bool 1080509cfdeSRalf Baechle select IRQ_DOMAIN 1090509cfdeSRalf Baechle 110c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 111c7c42ec2SSimon Arlott bool 112c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 113c7c42ec2SSimon Arlott select IRQ_DOMAIN 114d0ed5e8eSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 115c7c42ec2SSimon Arlott 1165f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 1175f7f0317SKevin Cernekee bool 1185f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1195f7f0317SKevin Cernekee select IRQ_DOMAIN 120b8d9884aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1215f7f0317SKevin Cernekee 122a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 123a4fcbb86SKevin Cernekee bool 124a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 125a4fcbb86SKevin Cernekee select IRQ_DOMAIN 126a4fcbb86SKevin Cernekee 1277f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 1287f646e92SFlorian Fainelli bool 1297f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1307f646e92SFlorian Fainelli select IRQ_DOMAIN 1317f646e92SFlorian Fainelli 132*0145beedSBartosz Golaszewskiconfig DAVINCI_AINTC 133*0145beedSBartosz Golaszewski bool 134*0145beedSBartosz Golaszewski select GENERIC_IRQ_CHIP 135*0145beedSBartosz Golaszewski select IRQ_DOMAIN 136*0145beedSBartosz Golaszewski 137350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 138350d71b9SSebastian Hesselbarth bool 139e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 140350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 141350d71b9SSebastian Hesselbarth 1426ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1436ee532e2SLinus Walleij bool 1446ee532e2SLinus Walleij select IRQ_DOMAIN 1454f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1466ee532e2SLinus Walleij select SPARSE_IRQ 1476ee532e2SLinus Walleij 1489a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1499a7c4abdSMaJun bool 1509a7c4abdSMaJun select ARM_GIC_V3 1519a7c4abdSMaJun select ARM_GIC_V3_ITS 1529a7c4abdSMaJun 153b6ef9161SJames Hoganconfig IMGPDC_IRQ 154b6ef9161SJames Hogan bool 155b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 156b6ef9161SJames Hogan select IRQ_DOMAIN 157b6ef9161SJames Hogan 158da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 159da0abe1aSRichard Fitzgerald tristate 160da0abe1aSRichard Fitzgerald 16167e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 16267e38cf2SRalf Baechle bool 16367e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1643838a547SPaul Burton select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 16567e38cf2SRalf Baechle select IRQ_DOMAIN 1663838a547SPaul Burton select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 16718416e45SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 16867e38cf2SRalf Baechle 169afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 170afc98d90SAlexander Shiyan bool 171afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 172afc98d90SAlexander Shiyan select IRQ_DOMAIN 1734f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 174afc98d90SAlexander Shiyan select SPARSE_IRQ 175afc98d90SAlexander Shiyan default y 176afc98d90SAlexander Shiyan 1779b54470aSStafford Horneconfig OMPIC 1789b54470aSStafford Horne bool 1799b54470aSStafford Horne 1804db8e6d2SStefan Kristianssonconfig OR1K_PIC 1814db8e6d2SStefan Kristiansson bool 1824db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1834db8e6d2SStefan Kristiansson 1848598066cSFelipe Balbiconfig OMAP_IRQCHIP 1858598066cSFelipe Balbi bool 1868598066cSFelipe Balbi select GENERIC_IRQ_CHIP 1878598066cSFelipe Balbi select IRQ_DOMAIN 1888598066cSFelipe Balbi 1899dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 1909dbd90f1SSebastian Hesselbarth bool 1919dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 1924f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1939dbd90f1SSebastian Hesselbarth 194aaa8666aSCristian Birsanconfig PIC32_EVIC 195aaa8666aSCristian Birsan bool 196aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 197aaa8666aSCristian Birsan select IRQ_DOMAIN 198aaa8666aSCristian Birsan 199981b58f6SRich Felkerconfig JCORE_AIC 2003602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2013602ffdeSRich Felker depends on OF 202981b58f6SRich Felker select IRQ_DOMAIN 203981b58f6SRich Felker help 204981b58f6SRich Felker Support for the J-Core integrated AIC. 205981b58f6SRich Felker 206d852e62aSManivannan Sadhasivamconfig RDA_INTC 207d852e62aSManivannan Sadhasivam bool 208d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 209d852e62aSManivannan Sadhasivam 21044358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 21144358048SMagnus Damm bool 21244358048SMagnus Damm select IRQ_DOMAIN 21344358048SMagnus Damm 214fbc83b7fSMagnus Dammconfig RENESAS_IRQC 215fbc83b7fSMagnus Damm bool 21699c221dfSMagnus Damm select GENERIC_IRQ_CHIP 217fbc83b7fSMagnus Damm select IRQ_DOMAIN 218fbc83b7fSMagnus Damm 21907088484SLee Jonesconfig ST_IRQCHIP 22007088484SLee Jones bool 22107088484SLee Jones select REGMAP 22207088484SLee Jones select MFD_SYSCON 22307088484SLee Jones help 22407088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 22507088484SLee Jones 2264bba6689SMans Rullgardconfig TANGO_IRQ 2274bba6689SMans Rullgard bool 2284bba6689SMans Rullgard select IRQ_DOMAIN 2294bba6689SMans Rullgard select GENERIC_IRQ_CHIP 2304bba6689SMans Rullgard 231b06eb017SChristian Ruppertconfig TB10X_IRQC 232b06eb017SChristian Ruppert bool 233b06eb017SChristian Ruppert select IRQ_DOMAIN 234b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 235b06eb017SChristian Ruppert 236d01f8633SDamien Riegelconfig TS4800_IRQ 237d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 238d01f8633SDamien Riegel select IRQ_DOMAIN 2390df337cfSRichard Weinberger depends on HAS_IOMEM 240d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 241d01f8633SDamien Riegel help 242d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 243d01f8633SDamien Riegel 2442389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2452389d501SLinus Walleij bool 2462389d501SLinus Walleij select IRQ_DOMAIN 2472389d501SLinus Walleij 2482389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2492389d501SLinus Walleij int 2502389d501SLinus Walleij default 4 2512389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 25226a8e96aSMax Filippov 25326a8e96aSMax Filippovconfig XTENSA_MX 25426a8e96aSMax Filippov bool 25526a8e96aSMax Filippov select IRQ_DOMAIN 25650091212SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 25796ca848eSSricharan R 2580547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 2590547dc78SZubair Lutfullah Kakakhel bool 2600547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 2610547dc78SZubair Lutfullah Kakakhel 26296ca848eSSricharan Rconfig IRQ_CROSSBAR 26396ca848eSSricharan R bool 26496ca848eSSricharan R help 265f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 26696ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 26796ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 26896ca848eSSricharan R routed to one of the free irqchip interrupt lines. 26989323f8cSGrygorii Strashko 27089323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 27189323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 27289323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 27389323f8cSGrygorii Strashko help 27489323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 27589323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 2768a19b8f1SAndrew Bresticker 2778a19b8f1SAndrew Brestickerconfig MIPS_GIC 2788a19b8f1SAndrew Bresticker bool 279bb11cff3SQais Yousef select GENERIC_IRQ_IPI 2802af70a96SQais Yousef select IRQ_DOMAIN_HIERARCHY 2818a19b8f1SAndrew Bresticker select MIPS_CM 2828a764482SYoshinori Sato 28344e08e70SPaul Burtonconfig INGENIC_IRQ 28444e08e70SPaul Burton bool 28544e08e70SPaul Burton depends on MACH_INGENIC 28644e08e70SPaul Burton default y 28778c10e55SLinus Torvalds 2888a764482SYoshinori Satoconfig RENESAS_H8300H_INTC 2898a764482SYoshinori Sato bool 2908a764482SYoshinori Sato select IRQ_DOMAIN 2918a764482SYoshinori Sato 2928a764482SYoshinori Satoconfig RENESAS_H8S_INTC 2938a764482SYoshinori Sato bool 2948a764482SYoshinori Sato select IRQ_DOMAIN 295e324c4dcSShenwei Wang 296e324c4dcSShenwei Wangconfig IMX_GPCV2 297e324c4dcSShenwei Wang bool 298e324c4dcSShenwei Wang select IRQ_DOMAIN 299e324c4dcSShenwei Wang help 300e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3017e4ac676SOleksij Rempel 3027e4ac676SOleksij Rempelconfig IRQ_MXS 3037e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3047e4ac676SOleksij Rempel select IRQ_DOMAIN 3057e4ac676SOleksij Rempel select STMP_DEVICE 306c27f29bbSThomas Petazzoni 30719d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 30819d99164SAlexandre Belloni bool 30919d99164SAlexandre Belloni select IRQ_DOMAIN 31019d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 31119d99164SAlexandre Belloni 312a68a63cbSThomas Petazzoniconfig MVEBU_GICP 313a68a63cbSThomas Petazzoni bool 314a68a63cbSThomas Petazzoni 315e0de91a9SThomas Petazzoniconfig MVEBU_ICU 316e0de91a9SThomas Petazzoni bool 317e0de91a9SThomas Petazzoni 318c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 319c27f29bbSThomas Petazzoni bool 320fa23b9d1SArnd Bergmann select GENERIC_MSI_IRQ_DOMAIN 3219e2c986cSMarc Zyngier 322a109893bSThomas Petazzoniconfig MVEBU_PIC 323a109893bSThomas Petazzoni bool 324a109893bSThomas Petazzoni 32561ce8d8dSMiquel Raynalconfig MVEBU_SEI 32661ce8d8dSMiquel Raynal bool 32761ce8d8dSMiquel Raynal 328b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 329b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 330b8f3ebe6SMinghuan Lian depends on PCI && PCI_MSI 331b8f3ebe6SMinghuan Lian 3329e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3339e2c986cSMarc Zyngier bool 3340efacbbaSLinus Torvalds 33544df427cSNoam Camusconfig EZNPS_GIC 33644df427cSNoam Camus bool "NPS400 Global Interrupt Manager (GIM)" 337ffd565e3SArnd Bergmann depends on ARC || (COMPILE_TEST && !64BIT) 33844df427cSNoam Camus select IRQ_DOMAIN 33944df427cSNoam Camus help 34044df427cSNoam Camus Support the EZchip NPS400 global interrupt controller 341e0720416SAlexandre TORGUE 342e0720416SAlexandre TORGUEconfig STM32_EXTI 343e0720416SAlexandre TORGUE bool 344e0720416SAlexandre TORGUE select IRQ_DOMAIN 3450e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 346f20cc9b0SAgustin Vega-Frias 347f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 348f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 349f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 350f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN 351f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 352f20cc9b0SAgustin Vega-Frias help 353f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 354f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 3555ed34d3aSMasahiro Yamada 3565ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 3575ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 3585ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 3595ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 3605ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 3615ed34d3aSMasahiro Yamada help 3625ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 363c94fb639SRandy Dunlap 364215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 365215f4cc0SJerome Brunet bool "Meson GPIO Interrupt Multiplexer" 366d9ee91c1SThomas Gleixner depends on ARCH_MESON 367215f4cc0SJerome Brunet select IRQ_DOMAIN 368215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 369215f4cc0SJerome Brunet help 370215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 371215f4cc0SJerome Brunet 3724235ff50SMiodrag Dinicconfig GOLDFISH_PIC 3734235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 3744235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 3754235ff50SMiodrag Dinic select IRQ_DOMAIN 3764235ff50SMiodrag Dinic help 3774235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 3784235ff50SMiodrag Dinic for Goldfish based virtual platforms. 3794235ff50SMiodrag Dinic 380f55c73aeSArchana Sathyakumarconfig QCOM_PDC 381f55c73aeSArchana Sathyakumar bool "QCOM PDC" 382f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 383f55c73aeSArchana Sathyakumar select IRQ_DOMAIN 384f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 385f55c73aeSArchana Sathyakumar help 386f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 387f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 388f55c73aeSArchana Sathyakumar 389d8a5f5f7SGuo Renconfig CSKY_MPINTC 390d8a5f5f7SGuo Ren bool "C-SKY Multi Processor Interrupt Controller" 391d8a5f5f7SGuo Ren depends on CSKY 392d8a5f5f7SGuo Ren help 393d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 394d8a5f5f7SGuo Ren for C-SKY SMP system. 395d8a5f5f7SGuo Ren In fact it's not mmio map in hw and it use ld/st to visit the 396d8a5f5f7SGuo Ren controller's register inside CPU. 397d8a5f5f7SGuo Ren 398edff1b48SGuo Renconfig CSKY_APB_INTC 399edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 400edff1b48SGuo Ren depends on CSKY 401edff1b48SGuo Ren help 402edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 403edff1b48SGuo Ren by C-SKY single core SOC system. It use mmio map apb-bus to visit 404edff1b48SGuo Ren the controller's register. 405edff1b48SGuo Ren 4060136afa0SLucas Stachconfig IMX_IRQSTEER 4070136afa0SLucas Stach bool "i.MX IRQSTEER support" 4080136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4090136afa0SLucas Stach default ARCH_MXC 4100136afa0SLucas Stach select IRQ_DOMAIN 4110136afa0SLucas Stach help 4120136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4130136afa0SLucas Stach 414c94fb639SRandy Dunlapendmenu 4158237f8bcSChristoph Hellwig 4168237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 4178237f8bcSChristoph Hellwig bool "SiFive Platform-Level Interrupt Controller" 4188237f8bcSChristoph Hellwig depends on RISCV 4198237f8bcSChristoph Hellwig help 4208237f8bcSChristoph Hellwig This enables support for the PLIC chip found in SiFive (and 4218237f8bcSChristoph Hellwig potentially other) RISC-V systems. The PLIC controls devices 4228237f8bcSChristoph Hellwig interrupts and connects them to each core's local interrupt 4238237f8bcSChristoph Hellwig controller. Aside from timer and software interrupts, all other 4248237f8bcSChristoph Hellwig interrupt sources are subordinate to the PLIC. 4258237f8bcSChristoph Hellwig 4268237f8bcSChristoph Hellwig If you don't know what to do here, say Y. 427