1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 31853a33ceSSuravee Suthikulpanit 3281243e44SRob Herringconfig GIC_NON_BANKED 3381243e44SRob Herring bool 3481243e44SRob Herring 35021f6537SMarc Zyngierconfig ARM_GIC_V3 36021f6537SMarc Zyngier bool 37443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 38e3825ba1SMarc Zyngier select PARTITION_PERCPU 390e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4035727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 41021f6537SMarc Zyngier 4219812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4319812729SMarc Zyngier bool 4413e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4548f71d56SThomas Gleixner select IRQ_MSI_LIB 4629f41139SMarc Zyngier default ARM_GIC_V3 4729f41139SMarc Zyngier 4829f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4929f41139SMarc Zyngier bool 5029f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 513ee80364SArnd Bergmann depends on PCI 523ee80364SArnd Bergmann depends on PCI_MSI 5329f41139SMarc Zyngier default ARM_GIC_V3_ITS 54292ec080SUwe Kleine-König 557afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 567afe031cSBogdan Purcareata bool 577afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata depends on FSL_MC_BUS 597afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 607afe031cSBogdan Purcareata 6144430ec0SRob Herringconfig ARM_NVIC 6244430ec0SRob Herring bool 632d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6444430ec0SRob Herring select GENERIC_IRQ_CHIP 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC 6744430ec0SRob Herring bool 6844430ec0SRob Herring select IRQ_DOMAIN 6944430ec0SRob Herring 7044430ec0SRob Herringconfig ARM_VIC_NR 7144430ec0SRob Herring int 7244430ec0SRob Herring default 4 if ARCH_S5PV210 7344430ec0SRob Herring default 2 7444430ec0SRob Herring depends on ARM_VIC 7544430ec0SRob Herring help 7644430ec0SRob Herring The maximum number of VICs available in the system, for 7744430ec0SRob Herring power management. 7844430ec0SRob Herring 7972e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 8072e257c6SThomas Gleixner bool 8172e257c6SThomas Gleixner 82fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 83fed6d336SThomas Petazzoni bool 84fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 853ee80364SArnd Bergmann select PCI_MSI if PCI 860e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 87fed6d336SThomas Petazzoni 88e6b78f2cSAntoine Tenartconfig ALPINE_MSI 89e6b78f2cSAntoine Tenart bool 903ee80364SArnd Bergmann depends on PCI 913ee80364SArnd Bergmann select PCI_MSI 92e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 93e6b78f2cSAntoine Tenart 941eb77c3bSTalel Shenharconfig AL_FIC 951eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 969869f37aSJean Delvare depends on OF 9735e0cd77SBaoquan He depends on HAS_IOMEM 981eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 991eb77c3bSTalel Shenhar select IRQ_DOMAIN 1001eb77c3bSTalel Shenhar help 1011eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1021eb77c3bSTalel Shenhar 103b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 104b1479ebbSBoris BREZILLON bool 105b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 106b1479ebbSBoris BREZILLON select IRQ_DOMAIN 107b1479ebbSBoris BREZILLON select SPARSE_IRQ 108b1479ebbSBoris BREZILLON 109b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 110b1479ebbSBoris BREZILLON bool 111b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 112b1479ebbSBoris BREZILLON select IRQ_DOMAIN 113b1479ebbSBoris BREZILLON select SPARSE_IRQ 114b1479ebbSBoris BREZILLON 1150509cfdeSRalf Baechleconfig I8259 1160509cfdeSRalf Baechle bool 1170509cfdeSRalf Baechle select IRQ_DOMAIN 1180509cfdeSRalf Baechle 119c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 120c7c42ec2SSimon Arlott bool 121c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 122c7c42ec2SSimon Arlott select IRQ_DOMAIN 1230e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 124c7c42ec2SSimon Arlott 1255f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 126c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 127c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 128c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1295f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1305f7f0317SKevin Cernekee select IRQ_DOMAIN 1310e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1325f7f0317SKevin Cernekee 133a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1343ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1353ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1363ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 137a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 138a4fcbb86SKevin Cernekee select IRQ_DOMAIN 139a4fcbb86SKevin Cernekee 1407f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 14151d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 14251d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 14351d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1447f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1457f646e92SFlorian Fainelli select IRQ_DOMAIN 1467f646e92SFlorian Fainelli 1470fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1480fc3d74cSBartosz Golaszewski bool 1490fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1500fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1510fc3d74cSBartosz Golaszewski 152350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 153be5e5f3aSThomas Gleixner bool 154e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15554a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 156350d71b9SSebastian Hesselbarth 1576ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1586ee532e2SLinus Walleij bool 1596ee532e2SLinus Walleij select IRQ_DOMAIN 1606ee532e2SLinus Walleij select SPARSE_IRQ 1616ee532e2SLinus Walleij 1629a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1639a7c4abdSMaJun bool 1649a7c4abdSMaJun select ARM_GIC_V3 1659a7c4abdSMaJun select ARM_GIC_V3_ITS 1669a7c4abdSMaJun 167b6ef9161SJames Hoganconfig IMGPDC_IRQ 168b6ef9161SJames Hogan bool 169b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 170b6ef9161SJames Hogan select IRQ_DOMAIN 171b6ef9161SJames Hogan 1725b978c10SLinus Walleijconfig IXP4XX_IRQ 1735b978c10SLinus Walleij bool 1745b978c10SLinus Walleij select IRQ_DOMAIN 1755b978c10SLinus Walleij select SPARSE_IRQ 1765b978c10SLinus Walleij 1773e3a7b35SHerve Codinaconfig LAN966X_OIC 1783e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 1793e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 1803e3a7b35SHerve Codina select IRQ_DOMAIN 1813e3a7b35SHerve Codina help 1823e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 1833e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 1843e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 1853e3a7b35SHerve Codina 1863e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 1873e3a7b35SHerve Codina will be called irq-lan966x-oic. 1883e3a7b35SHerve Codina 189da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 190da0abe1aSRichard Fitzgerald tristate 191da0abe1aSRichard Fitzgerald 19267e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 19367e38cf2SRalf Baechle bool 19467e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1950f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 19667e38cf2SRalf Baechle select IRQ_DOMAIN 1970e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 19867e38cf2SRalf Baechle 199afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 200afc98d90SAlexander Shiyan bool 201afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 202afc98d90SAlexander Shiyan select IRQ_DOMAIN 203afc98d90SAlexander Shiyan select SPARSE_IRQ 204afc98d90SAlexander Shiyan default y 205afc98d90SAlexander Shiyan 2069b54470aSStafford Horneconfig OMPIC 2079b54470aSStafford Horne bool 2089b54470aSStafford Horne 2094db8e6d2SStefan Kristianssonconfig OR1K_PIC 2104db8e6d2SStefan Kristiansson bool 2114db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2124db8e6d2SStefan Kristiansson 2138598066cSFelipe Balbiconfig OMAP_IRQCHIP 2148598066cSFelipe Balbi bool 2158598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2168598066cSFelipe Balbi select IRQ_DOMAIN 2178598066cSFelipe Balbi 2189dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2199dbd90f1SSebastian Hesselbarth bool 2209dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2219dbd90f1SSebastian Hesselbarth 222aaa8666aSCristian Birsanconfig PIC32_EVIC 223aaa8666aSCristian Birsan bool 224aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 225aaa8666aSCristian Birsan select IRQ_DOMAIN 226aaa8666aSCristian Birsan 227981b58f6SRich Felkerconfig JCORE_AIC 2283602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2293602ffdeSRich Felker depends on OF 230981b58f6SRich Felker select IRQ_DOMAIN 231981b58f6SRich Felker help 232981b58f6SRich Felker Support for the J-Core integrated AIC. 233981b58f6SRich Felker 234d852e62aSManivannan Sadhasivamconfig RDA_INTC 235d852e62aSManivannan Sadhasivam bool 236d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 237d852e62aSManivannan Sadhasivam 23844358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 23902d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 24044358048SMagnus Damm select IRQ_DOMAIN 24102d7e041SGeert Uytterhoeven help 24202d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 24302d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 24444358048SMagnus Damm 245fbc83b7fSMagnus Dammconfig RENESAS_IRQC 24672d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 24799c221dfSMagnus Damm select GENERIC_IRQ_CHIP 248fbc83b7fSMagnus Damm select IRQ_DOMAIN 24902d7e041SGeert Uytterhoeven help 25002d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 25172d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 252fbc83b7fSMagnus Damm 253a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 25402d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 255a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 25602d7e041SGeert Uytterhoeven help 25702d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 25802d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 259a644ccb8SGeert Uytterhoeven 2603fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2613fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2623fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2633fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2643fed0955SLad Prabhakar help 2653fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2663fed0955SLad Prabhakar for external devices. 2673fed0955SLad Prabhakar 2680d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2690d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 2700d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 2710d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 2720d7605e7SFabrizio Castro help 2730d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 2740d7605e7SFabrizio Castro 27503ac990eSMichael Walleconfig SL28CPLD_INTC 27603ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 27703ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 27803ac990eSMichael Walle select REGMAP_IRQ 27903ac990eSMichael Walle help 28003ac990eSMichael Walle Interrupt controller driver for the board management controller 28103ac990eSMichael Walle found on the Kontron sl28 CPLD. 28203ac990eSMichael Walle 28307088484SLee Jonesconfig ST_IRQCHIP 28407088484SLee Jones bool 28507088484SLee Jones select REGMAP 28607088484SLee Jones select MFD_SYSCON 28707088484SLee Jones help 28807088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 28907088484SLee Jones 290d421fd6dSSamuel Hollandconfig SUN4I_INTC 291d421fd6dSSamuel Holland bool 292d421fd6dSSamuel Holland 293d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 294d421fd6dSSamuel Holland bool 295d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 296d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 297d421fd6dSSamuel Holland 298d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 299d421fd6dSSamuel Holland bool 300d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 301d421fd6dSSamuel Holland 302b06eb017SChristian Ruppertconfig TB10X_IRQC 303b06eb017SChristian Ruppert bool 304b06eb017SChristian Ruppert select IRQ_DOMAIN 305b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 306b06eb017SChristian Ruppert 307d01f8633SDamien Riegelconfig TS4800_IRQ 308d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 309d01f8633SDamien Riegel select IRQ_DOMAIN 3100df337cfSRichard Weinberger depends on HAS_IOMEM 311d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 312d01f8633SDamien Riegel help 313d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 314d01f8633SDamien Riegel 3152389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3162389d501SLinus Walleij bool 3172389d501SLinus Walleij select IRQ_DOMAIN 3182389d501SLinus Walleij 3192389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3202389d501SLinus Walleij int 3212389d501SLinus Walleij default 4 3222389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 32326a8e96aSMax Filippov 32426a8e96aSMax Filippovconfig XTENSA_MX 32526a8e96aSMax Filippov bool 32626a8e96aSMax Filippov select IRQ_DOMAIN 3270e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 32896ca848eSSricharan R 3290547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 330debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 331fd31000dSJamie Iles depends on OF_ADDRESS 3320547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 333debf69cfSRobert Hancock help 334debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 335debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 336debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3370547dc78SZubair Lutfullah Kakakhel 33896ca848eSSricharan Rconfig IRQ_CROSSBAR 33996ca848eSSricharan R bool 34096ca848eSSricharan R help 341f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 34296ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 34396ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 34496ca848eSSricharan R routed to one of the free irqchip interrupt lines. 34589323f8cSGrygorii Strashko 34689323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 34789323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 34889323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 34989323f8cSGrygorii Strashko help 35089323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 35189323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3528a19b8f1SAndrew Bresticker 3538a19b8f1SAndrew Brestickerconfig MIPS_GIC 3548a19b8f1SAndrew Bresticker bool 355*0053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3568190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3578190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3588a19b8f1SAndrew Bresticker select MIPS_CM 3598a764482SYoshinori Sato 36044e08e70SPaul Burtonconfig INGENIC_IRQ 36144e08e70SPaul Burton bool 36244e08e70SPaul Burton depends on MACH_INGENIC 36344e08e70SPaul Burton default y 36478c10e55SLinus Torvalds 3659536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3669536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3679536eba0SPaul Cercueil default MACH_INGENIC 3689536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3699536eba0SPaul Cercueil select MFD_SYSCON 3708084499bSYueHaibing select GENERIC_IRQ_CHIP 3719536eba0SPaul Cercueil help 3729536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3739536eba0SPaul Cercueil JZ47xx SoCs. 3749536eba0SPaul Cercueil 3759536eba0SPaul Cercueil If unsure, say N. 3769536eba0SPaul Cercueil 377e324c4dcSShenwei Wangconfig IMX_GPCV2 378e324c4dcSShenwei Wang bool 379e324c4dcSShenwei Wang select IRQ_DOMAIN 380e324c4dcSShenwei Wang help 381e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3827e4ac676SOleksij Rempel 3837e4ac676SOleksij Rempelconfig IRQ_MXS 3847e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3857e4ac676SOleksij Rempel select IRQ_DOMAIN 3867e4ac676SOleksij Rempel select STMP_DEVICE 387c27f29bbSThomas Petazzoni 38819d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 38919d99164SAlexandre Belloni bool 39019d99164SAlexandre Belloni select IRQ_DOMAIN 39119d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 39219d99164SAlexandre Belloni 393a68a63cbSThomas Petazzoniconfig MVEBU_GICP 394cdb23872SThomas Gleixner select IRQ_MSI_LIB 395a68a63cbSThomas Petazzoni bool 396a68a63cbSThomas Petazzoni 397e0de91a9SThomas Petazzoniconfig MVEBU_ICU 398e0de91a9SThomas Petazzoni bool 399e0de91a9SThomas Petazzoni 400c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 401c27f29bbSThomas Petazzoni bool 402e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 40313e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4049e2c986cSMarc Zyngier 405a109893bSThomas Petazzoniconfig MVEBU_PIC 406a109893bSThomas Petazzoni bool 407a109893bSThomas Petazzoni 40861ce8d8dSMiquel Raynalconfig MVEBU_SEI 40961ce8d8dSMiquel Raynal bool 41061ce8d8dSMiquel Raynal 4110dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4120dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4130dcd9f87SRasmus Villemoes select MFD_SYSCON 4140dcd9f87SRasmus Villemoes 415b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 416b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4179c1a7bfcSLukas Bulwahn depends on PCI_MSI 418b8f3ebe6SMinghuan Lian 4199e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4209e2c986cSMarc Zyngier bool 4210efacbbaSLinus Torvalds 422b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4230be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4240be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4250be58e05SAntonio Borneo default y 4260be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 427350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4280be58e05SAntonio Borneo help 4290be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 430b20cf2dcSAntonio Borneo 431e0720416SAlexandre TORGUEconfig STM32_EXTI 432e0720416SAlexandre TORGUE bool 433e0720416SAlexandre TORGUE select IRQ_DOMAIN 4340e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 435f20cc9b0SAgustin Vega-Frias 436f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 437f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 438f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 439f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 440f20cc9b0SAgustin Vega-Frias help 441f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 442f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4435ed34d3aSMasahiro Yamada 4445ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4455ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4465ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4475ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4485ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4495ed34d3aSMasahiro Yamada help 4505ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 451c94fb639SRandy Dunlap 452215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 453a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 454a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 455a947aa00SNeil Armstrong default ARCH_MESON 456215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 457215f4cc0SJerome Brunet help 458215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 459215f4cc0SJerome Brunet 4604235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4614235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4624235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 463969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4644235ff50SMiodrag Dinic select IRQ_DOMAIN 4654235ff50SMiodrag Dinic help 4664235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4674235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4684235ff50SMiodrag Dinic 469f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4704acd8a4bSSaravana Kannan tristate "QCOM PDC" 471f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 472f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 473f55c73aeSArchana Sathyakumar help 474f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 475f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 476f55c73aeSArchana Sathyakumar 477a6199bb5SShawn Guoconfig QCOM_MPM 478a6199bb5SShawn Guo tristate "QCOM MPM" 479a6199bb5SShawn Guo depends on ARCH_QCOM 480fa4dcc88SYueHaibing depends on MAILBOX 481a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 482a6199bb5SShawn Guo help 483a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 484a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 485a6199bb5SShawn Guo 486d8a5f5f7SGuo Renconfig CSKY_MPINTC 487be1abc5bSGuo Ren bool 488d8a5f5f7SGuo Ren depends on CSKY 489d8a5f5f7SGuo Ren help 490d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 491d8a5f5f7SGuo Ren for C-SKY SMP system. 492656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 493d8a5f5f7SGuo Ren controller's register inside CPU. 494d8a5f5f7SGuo Ren 495edff1b48SGuo Renconfig CSKY_APB_INTC 496edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 497edff1b48SGuo Ren depends on CSKY 498edff1b48SGuo Ren help 499edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 500656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 501edff1b48SGuo Ren the controller's register. 502edff1b48SGuo Ren 5030136afa0SLucas Stachconfig IMX_IRQSTEER 5040136afa0SLucas Stach bool "i.MX IRQSTEER support" 5050136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5060136afa0SLucas Stach default ARCH_MXC 5070136afa0SLucas Stach select IRQ_DOMAIN 5080136afa0SLucas Stach help 5090136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5100136afa0SLucas Stach 5112fbb1396SJoakim Zhangconfig IMX_INTMUX 512a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 513a890caebSGeert Uytterhoeven default y if ARCH_MXC 5142fbb1396SJoakim Zhang select IRQ_DOMAIN 5152fbb1396SJoakim Zhang help 5162fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5172fbb1396SJoakim Zhang 51870afdab9SFrank Liconfig IMX_MU_MSI 51970afdab9SFrank Li tristate "i.MX MU used as MSI controller" 52070afdab9SFrank Li depends on OF && HAS_IOMEM 5216c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 52270afdab9SFrank Li default m if ARCH_MXC 52370afdab9SFrank Li select IRQ_DOMAIN 52470afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 52513e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5267b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 52770afdab9SFrank Li help 5286c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5296c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5306c9f7434SGeert Uytterhoeven to make use of this driver. 53170afdab9SFrank Li 53270afdab9SFrank Li If unsure, say N 53370afdab9SFrank Li 5349e543e22SJiaxun Yangconfig LS1X_IRQ 5359e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5369e543e22SJiaxun Yang depends on MACH_LOONGSON32 5379e543e22SJiaxun Yang default y 5389e543e22SJiaxun Yang select IRQ_DOMAIN 5399e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5409e543e22SJiaxun Yang help 5419e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5429e543e22SJiaxun Yang 543cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 544cd844b07SLokesh Vutla bool 545cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 546cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 547cd844b07SLokesh Vutla help 548cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 549cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 550cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 551cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 552cd844b07SLokesh Vutla 5539f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 5549f1463b8SLokesh Vutla bool 5559f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 5569f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 557f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5589f1463b8SLokesh Vutla help 5599f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5609f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5619f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5629f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5639f1463b8SLokesh Vutla 56404e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 565b8e594faSSuman Anna tristate 566b8e594faSSuman Anna depends on TI_PRUSS 567b8e594faSSuman Anna default TI_PRUSS 56804e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 56904e2d1e0SGrzegorz Jaszczyk help 57004e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 57104e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 57204e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 57304e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 57404e2d1e0SGrzegorz Jaszczyk 5756b7ce892SAnup Patelconfig RISCV_INTC 576d8fb1307SConor Dooley bool 5776b7ce892SAnup Patel depends on RISCV 578832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 5796b7ce892SAnup Patel 5802333df5aSAnup Patelconfig RISCV_APLIC 5812333df5aSAnup Patel bool 5822333df5aSAnup Patel depends on RISCV 5832333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 5842333df5aSAnup Patel 585ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 586ca8df97fSAnup Patel bool 587ca8df97fSAnup Patel depends on RISCV_APLIC 588ca8df97fSAnup Patel select GENERIC_MSI_IRQ 589ca8df97fSAnup Patel default RISCV_APLIC 590ca8df97fSAnup Patel 59121a8f8a0SAnup Patelconfig RISCV_IMSIC 59221a8f8a0SAnup Patel bool 59321a8f8a0SAnup Patel depends on RISCV 59421a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 59521a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 59621a8f8a0SAnup Patel select GENERIC_MSI_IRQ 59721a8f8a0SAnup Patel 5985c5a71d0SAnup Patelconfig RISCV_IMSIC_PCI 5995c5a71d0SAnup Patel bool 6005c5a71d0SAnup Patel depends on RISCV_IMSIC 6015c5a71d0SAnup Patel depends on PCI 6025c5a71d0SAnup Patel depends on PCI_MSI 6035c5a71d0SAnup Patel default RISCV_IMSIC 6045c5a71d0SAnup Patel 6058237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 606fdb1742aSConor Dooley bool 6078237f8bcSChristoph Hellwig depends on RISCV 608466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 609de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 61001493855SJonathan Neuschäfer 611e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 612e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 613e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 614e4e53503SChanghuang Liang default ARCH_STARFIVE 615e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 616e4e53503SChanghuang Liang help 617e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 618e4e53503SChanghuang Liang SoC. 619e4e53503SChanghuang Liang 620e4e53503SChanghuang Liang If you don't know what to do here, say Y. 621e4e53503SChanghuang Liang 622b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 623b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 624b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 625b74416dbSHyunki Koo help 626b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 627b74416dbSHyunki Koo in Samsung Exynos chips. 628b74416dbSHyunki Koo 629b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 630b2d3e335SHuacai Chen bool 631b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 632b2d3e335SHuacai Chen select IRQ_DOMAIN 63342a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 63470f7b6c0SHuacai Chen select LOONGSON_HTVEC 6358d5356f9SHuacai Chen select LOONGSON_LIOINTC 6368d5356f9SHuacai Chen select LOONGSON_EIOINTC 6378d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6388d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6398d5356f9SHuacai Chen select LOONGSON_PCH_LPC 640b2d3e335SHuacai Chen help 641b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 642b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 64351712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 644b2d3e335SHuacai Chen 645dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 646dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 647dbb15226SJiaxun Yang depends on MACH_LOONGSON64 648dbb15226SJiaxun Yang default y 649dbb15226SJiaxun Yang select IRQ_DOMAIN 650dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 651dbb15226SJiaxun Yang help 652dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 653dbb15226SJiaxun Yang 654dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 655dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 656dd281e1aSHuacai Chen depends on LOONGARCH 657dd281e1aSHuacai Chen depends on MACH_LOONGSON64 658dd281e1aSHuacai Chen default MACH_LOONGSON64 659dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 660dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 661dd281e1aSHuacai Chen help 662dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 663dd281e1aSHuacai Chen 664a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 665a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 666987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 667a93f1d90SJiaxun Yang default y 668a93f1d90SJiaxun Yang select IRQ_DOMAIN 669a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 670a93f1d90SJiaxun Yang help 671a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 672a93f1d90SJiaxun Yang 673818e915fSJiaxun Yangconfig LOONGSON_HTVEC 674987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 675d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 676818e915fSJiaxun Yang default MACH_LOONGSON64 677818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 678818e915fSJiaxun Yang help 679987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 680818e915fSJiaxun Yang 681ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 682ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 683bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 684ef8c01ebSJiaxun Yang default MACH_LOONGSON64 685ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 686ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 687ef8c01ebSJiaxun Yang help 688ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 689ef8c01ebSJiaxun Yang 690632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 691a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 69202308732SHuacai Chen depends on MACH_LOONGSON64 693632dcc2cSJiaxun Yang depends on PCI 694632dcc2cSJiaxun Yang default MACH_LOONGSON64 695632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 6960b3af759SHuacai Chen select IRQ_MSI_LIB 697632dcc2cSJiaxun Yang select PCI_MSI 698632dcc2cSJiaxun Yang help 699632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 700632dcc2cSJiaxun Yang 701ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 702ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 703e7ccba77SJianmin Lv depends on LOONGARCH 704ee73f14eSHuacai Chen depends on MACH_LOONGSON64 705e7ccba77SJianmin Lv default MACH_LOONGSON64 706ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 707ee73f14eSHuacai Chen help 708ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 709ee73f14eSHuacai Chen 710ad4c938cSMark-PK Tsaiconfig MST_IRQ 711ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 71261b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 713ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 714ad4c938cSMark-PK Tsai select IRQ_DOMAIN 715ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 716ad4c938cSMark-PK Tsai help 717ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 718ad4c938cSMark-PK Tsai 719fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 720fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 72194bc9420SMarc Zyngier depends on ARCH_WPCM450 722fead4dd4SJonathan Neuschäfer help 723fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 724fead4dd4SJonathan Neuschäfer 725529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 726529ea368SThomas Bogendoerfer bool 727529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 728529ea368SThomas Bogendoerfer select IRQ_DOMAIN 729529ea368SThomas Bogendoerfer 73076cde263SHector Martinconfig APPLE_AIC 73176cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 73276cde263SHector Martin depends on ARM64 7335b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 734c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 73576cde263SHector Martin help 73676cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 73776cde263SHector Martin such as the M1. 73876cde263SHector Martin 73900fa3461SClaudiu Bezneaconfig MCHP_EIC 74000fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 74100fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 74200fa3461SClaudiu Beznea select IRQ_DOMAIN 74300fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 74400fa3461SClaudiu Beznea help 74500fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 74600fa3461SClaudiu Beznea 747f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 748f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 749f7189d93SQin Jian default SOC_SP7021 750f7189d93SQin Jian help 751f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 752f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 753f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 754f7189d93SQin Jian the primary controller on C-Chip. 755f7189d93SQin Jian 75601493855SJonathan Neuschäferendmenu 757