1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Hyper-V stub IOMMU driver. 5 * 6 * Copyright (C) 2019, Microsoft, Inc. 7 * 8 * Author : Lan Tianyu <Tianyu.Lan@microsoft.com> 9 */ 10 11 #include <linux/types.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/iommu.h> 15 #include <linux/module.h> 16 17 #include <asm/apic.h> 18 #include <asm/cpu.h> 19 #include <asm/hw_irq.h> 20 #include <asm/io_apic.h> 21 #include <asm/irq_remapping.h> 22 #include <asm/hypervisor.h> 23 #include <asm/mshyperv.h> 24 25 #include "../irq_remapping.h" 26 27 /* 28 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt 29 * Redirection Table. Hyper-V exposes one single IO-APIC and so define 30 * 24 IO APIC remmapping entries. 31 */ 32 #define IOAPIC_REMAPPING_ENTRY 24 33 34 static cpumask_t ioapic_max_cpumask = { CPU_BITS_NONE }; 35 static struct irq_domain *ioapic_ir_domain; 36 37 static int hyperv_ir_set_affinity(struct irq_data *data, 38 const struct cpumask *mask, bool force) 39 { 40 struct irq_data *parent = data->parent_data; 41 struct irq_cfg *cfg = irqd_cfg(data); 42 int ret; 43 44 /* Return error If new irq affinity is out of ioapic_max_cpumask. */ 45 if (!cpumask_subset(mask, &ioapic_max_cpumask)) 46 return -EINVAL; 47 48 ret = parent->chip->irq_set_affinity(parent, mask, force); 49 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 50 return ret; 51 52 vector_schedule_cleanup(cfg); 53 54 return 0; 55 } 56 57 static struct irq_chip hyperv_ir_chip = { 58 .name = "HYPERV-IR", 59 .irq_ack = apic_ack_irq, 60 .irq_set_affinity = hyperv_ir_set_affinity, 61 }; 62 63 static int hyperv_irq_remapping_alloc(struct irq_domain *domain, 64 unsigned int virq, unsigned int nr_irqs, 65 void *arg) 66 { 67 struct irq_alloc_info *info = arg; 68 struct irq_data *irq_data; 69 int ret = 0; 70 71 if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1) 72 return -EINVAL; 73 74 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 75 if (ret < 0) 76 return ret; 77 78 irq_data = irq_domain_get_irq_data(domain, virq); 79 if (!irq_data) { 80 irq_domain_free_irqs_common(domain, virq, nr_irqs); 81 return -EINVAL; 82 } 83 84 irq_data->chip = &hyperv_ir_chip; 85 86 /* 87 * Hypver-V IO APIC irq affinity should be in the scope of 88 * ioapic_max_cpumask because no irq remapping support. 89 */ 90 irq_data_update_affinity(irq_data, &ioapic_max_cpumask); 91 92 return 0; 93 } 94 95 static void hyperv_irq_remapping_free(struct irq_domain *domain, 96 unsigned int virq, unsigned int nr_irqs) 97 { 98 irq_domain_free_irqs_common(domain, virq, nr_irqs); 99 } 100 101 static int hyperv_irq_remapping_select(struct irq_domain *d, 102 struct irq_fwspec *fwspec, 103 enum irq_domain_bus_token bus_token) 104 { 105 /* Claim the only I/O APIC emulated by Hyper-V */ 106 return x86_fwspec_is_ioapic(fwspec); 107 } 108 109 static const struct irq_domain_ops hyperv_ir_domain_ops = { 110 .select = hyperv_irq_remapping_select, 111 .alloc = hyperv_irq_remapping_alloc, 112 .free = hyperv_irq_remapping_free, 113 }; 114 115 static const struct irq_domain_ops hyperv_root_ir_domain_ops; 116 static int __init hyperv_prepare_irq_remapping(void) 117 { 118 struct fwnode_handle *fn; 119 int i; 120 const char *name; 121 const struct irq_domain_ops *ops; 122 123 /* 124 * For a Hyper-V root partition, ms_hyperv_msi_ext_dest_id() 125 * will always return false. 126 */ 127 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV) || 128 x86_init.hyper.msi_ext_dest_id()) 129 return -ENODEV; 130 131 if (hv_root_partition()) { 132 name = "HYPERV-ROOT-IR"; 133 ops = &hyperv_root_ir_domain_ops; 134 } else { 135 name = "HYPERV-IR"; 136 ops = &hyperv_ir_domain_ops; 137 } 138 139 fn = irq_domain_alloc_named_id_fwnode(name, 0); 140 if (!fn) 141 return -ENOMEM; 142 143 ioapic_ir_domain = 144 irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 145 0, IOAPIC_REMAPPING_ENTRY, fn, ops, NULL); 146 147 if (!ioapic_ir_domain) { 148 irq_domain_free_fwnode(fn); 149 return -ENOMEM; 150 } 151 152 if (hv_root_partition()) 153 return 0; /* The rest is only relevant to guests */ 154 155 /* 156 * Hyper-V doesn't provide irq remapping function for 157 * IO-APIC and so IO-APIC only accepts 8-bit APIC ID. 158 * Cpu's APIC ID is read from ACPI MADT table and APIC IDs 159 * in the MADT table on Hyper-v are sorted monotonic increasingly. 160 * APIC ID reflects cpu topology. There maybe some APIC ID 161 * gaps when cpu number in a socket is not power of two. Prepare 162 * max cpu affinity for IOAPIC irqs. Scan cpu 0-255 and set cpu 163 * into ioapic_max_cpumask if its APIC ID is less than 256. 164 */ 165 for (i = min_t(unsigned int, nr_cpu_ids - 1, 255); i >= 0; i--) 166 if (cpu_possible(i) && cpu_physical_id(i) < 256) 167 cpumask_set_cpu(i, &ioapic_max_cpumask); 168 169 return 0; 170 } 171 172 static int __init hyperv_enable_irq_remapping(void) 173 { 174 if (x2apic_supported()) 175 return IRQ_REMAP_X2APIC_MODE; 176 return IRQ_REMAP_XAPIC_MODE; 177 } 178 179 struct irq_remap_ops hyperv_irq_remap_ops = { 180 .prepare = hyperv_prepare_irq_remapping, 181 .enable = hyperv_enable_irq_remapping, 182 }; 183 184 /* IRQ remapping domain when Linux runs as the root partition */ 185 struct hyperv_root_ir_data { 186 u8 ioapic_id; 187 bool is_level; 188 struct hv_interrupt_entry entry; 189 }; 190 191 static void 192 hyperv_root_ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) 193 { 194 struct hyperv_root_ir_data *data = irq_data->chip_data; 195 struct hv_interrupt_entry entry; 196 const struct cpumask *affinity; 197 struct IO_APIC_route_entry e; 198 struct irq_cfg *cfg; 199 int cpu, ioapic_id; 200 u32 vector; 201 202 cfg = irqd_cfg(irq_data); 203 affinity = irq_data_get_effective_affinity_mask(irq_data); 204 cpu = cpumask_first_and(affinity, cpu_online_mask); 205 206 vector = cfg->vector; 207 ioapic_id = data->ioapic_id; 208 209 if (data->entry.source == HV_DEVICE_TYPE_IOAPIC 210 && data->entry.ioapic_rte.as_uint64) { 211 entry = data->entry; 212 213 (void)hv_unmap_ioapic_interrupt(ioapic_id, &entry); 214 215 data->entry.ioapic_rte.as_uint64 = 0; 216 data->entry.source = 0; /* Invalid source */ 217 } 218 219 220 if (hv_map_ioapic_interrupt(ioapic_id, data->is_level, cpu, 221 vector, &entry)) 222 return; 223 224 data->entry = entry; 225 226 /* Turn it into an IO_APIC_route_entry, and generate MSI MSG. */ 227 e.w1 = entry.ioapic_rte.low_uint32; 228 e.w2 = entry.ioapic_rte.high_uint32; 229 230 memset(msg, 0, sizeof(*msg)); 231 msg->arch_data.vector = e.vector; 232 msg->arch_data.delivery_mode = e.delivery_mode; 233 msg->arch_addr_lo.dest_mode_logical = e.dest_mode_logical; 234 msg->arch_addr_lo.dmar_format = e.ir_format; 235 msg->arch_addr_lo.dmar_index_0_14 = e.ir_index_0_14; 236 } 237 238 static int hyperv_root_ir_set_affinity(struct irq_data *data, 239 const struct cpumask *mask, bool force) 240 { 241 struct irq_data *parent = data->parent_data; 242 struct irq_cfg *cfg = irqd_cfg(data); 243 int ret; 244 245 ret = parent->chip->irq_set_affinity(parent, mask, force); 246 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 247 return ret; 248 249 vector_schedule_cleanup(cfg); 250 251 return 0; 252 } 253 254 static struct irq_chip hyperv_root_ir_chip = { 255 .name = "HYPERV-ROOT-IR", 256 .irq_ack = apic_ack_irq, 257 .irq_set_affinity = hyperv_root_ir_set_affinity, 258 .irq_compose_msi_msg = hyperv_root_ir_compose_msi_msg, 259 }; 260 261 static int hyperv_root_irq_remapping_alloc(struct irq_domain *domain, 262 unsigned int virq, unsigned int nr_irqs, 263 void *arg) 264 { 265 struct irq_alloc_info *info = arg; 266 struct irq_data *irq_data; 267 struct hyperv_root_ir_data *data; 268 int ret = 0; 269 270 if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1) 271 return -EINVAL; 272 273 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 274 if (ret < 0) 275 return ret; 276 277 data = kzalloc_obj(*data); 278 if (!data) { 279 irq_domain_free_irqs_common(domain, virq, nr_irqs); 280 return -ENOMEM; 281 } 282 283 irq_data = irq_domain_get_irq_data(domain, virq); 284 if (!irq_data) { 285 kfree(data); 286 irq_domain_free_irqs_common(domain, virq, nr_irqs); 287 return -EINVAL; 288 } 289 290 data->ioapic_id = info->devid; 291 data->is_level = info->ioapic.is_level; 292 293 irq_data->chip = &hyperv_root_ir_chip; 294 irq_data->chip_data = data; 295 296 return 0; 297 } 298 299 static void hyperv_root_irq_remapping_free(struct irq_domain *domain, 300 unsigned int virq, unsigned int nr_irqs) 301 { 302 struct irq_data *irq_data; 303 struct hyperv_root_ir_data *data; 304 struct hv_interrupt_entry *e; 305 int i; 306 307 for (i = 0; i < nr_irqs; i++) { 308 irq_data = irq_domain_get_irq_data(domain, virq + i); 309 310 if (irq_data && irq_data->chip_data) { 311 data = irq_data->chip_data; 312 e = &data->entry; 313 314 if (e->source == HV_DEVICE_TYPE_IOAPIC && 315 e->ioapic_rte.as_uint64) 316 (void)hv_unmap_ioapic_interrupt(data->ioapic_id, 317 &data->entry); 318 319 kfree(data); 320 } 321 } 322 323 irq_domain_free_irqs_common(domain, virq, nr_irqs); 324 } 325 326 static const struct irq_domain_ops hyperv_root_ir_domain_ops = { 327 .select = hyperv_irq_remapping_select, 328 .alloc = hyperv_root_irq_remapping_alloc, 329 .free = hyperv_root_irq_remapping_free, 330 }; 331