1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver 4 * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7 #include <dt-bindings/interconnect/qcom,sdm660.h> 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 18 #include "icc-rpm.h" 19 20 enum { 21 SDM660_MASTER_IPA = 1, 22 SDM660_MASTER_CNOC_A2NOC, 23 SDM660_MASTER_SDCC_1, 24 SDM660_MASTER_SDCC_2, 25 SDM660_MASTER_BLSP_1, 26 SDM660_MASTER_BLSP_2, 27 SDM660_MASTER_UFS, 28 SDM660_MASTER_USB_HS, 29 SDM660_MASTER_USB3, 30 SDM660_MASTER_CRYPTO_C0, 31 SDM660_MASTER_GNOC_BIMC, 32 SDM660_MASTER_OXILI, 33 SDM660_MASTER_MNOC_BIMC, 34 SDM660_MASTER_SNOC_BIMC, 35 SDM660_MASTER_PIMEM, 36 SDM660_MASTER_SNOC_CNOC, 37 SDM660_MASTER_QDSS_DAP, 38 SDM660_MASTER_APPS_PROC, 39 SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 40 SDM660_MASTER_CNOC_MNOC_CFG, 41 SDM660_MASTER_CPP, 42 SDM660_MASTER_JPEG, 43 SDM660_MASTER_MDP_P0, 44 SDM660_MASTER_MDP_P1, 45 SDM660_MASTER_VENUS, 46 SDM660_MASTER_VFE, 47 SDM660_MASTER_QDSS_ETR, 48 SDM660_MASTER_QDSS_BAM, 49 SDM660_MASTER_SNOC_CFG, 50 SDM660_MASTER_BIMC_SNOC, 51 SDM660_MASTER_A2NOC_SNOC, 52 SDM660_MASTER_GNOC_SNOC, 53 54 SDM660_SLAVE_A2NOC_SNOC, 55 SDM660_SLAVE_EBI, 56 SDM660_SLAVE_HMSS_L3, 57 SDM660_SLAVE_BIMC_SNOC, 58 SDM660_SLAVE_CNOC_A2NOC, 59 SDM660_SLAVE_MPM, 60 SDM660_SLAVE_PMIC_ARB, 61 SDM660_SLAVE_TLMM_NORTH, 62 SDM660_SLAVE_TCSR, 63 SDM660_SLAVE_PIMEM_CFG, 64 SDM660_SLAVE_IMEM_CFG, 65 SDM660_SLAVE_MESSAGE_RAM, 66 SDM660_SLAVE_GLM, 67 SDM660_SLAVE_BIMC_CFG, 68 SDM660_SLAVE_PRNG, 69 SDM660_SLAVE_SPDM, 70 SDM660_SLAVE_QDSS_CFG, 71 SDM660_SLAVE_CNOC_MNOC_CFG, 72 SDM660_SLAVE_SNOC_CFG, 73 SDM660_SLAVE_QM_CFG, 74 SDM660_SLAVE_CLK_CTL, 75 SDM660_SLAVE_MSS_CFG, 76 SDM660_SLAVE_TLMM_SOUTH, 77 SDM660_SLAVE_UFS_CFG, 78 SDM660_SLAVE_A2NOC_CFG, 79 SDM660_SLAVE_A2NOC_SMMU_CFG, 80 SDM660_SLAVE_GPUSS_CFG, 81 SDM660_SLAVE_AHB2PHY, 82 SDM660_SLAVE_BLSP_1, 83 SDM660_SLAVE_SDCC_1, 84 SDM660_SLAVE_SDCC_2, 85 SDM660_SLAVE_TLMM_CENTER, 86 SDM660_SLAVE_BLSP_2, 87 SDM660_SLAVE_PDM, 88 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 89 SDM660_SLAVE_USB_HS, 90 SDM660_SLAVE_USB3_0, 91 SDM660_SLAVE_SRVC_CNOC, 92 SDM660_SLAVE_GNOC_BIMC, 93 SDM660_SLAVE_GNOC_SNOC, 94 SDM660_SLAVE_CAMERA_CFG, 95 SDM660_SLAVE_CAMERA_THROTTLE_CFG, 96 SDM660_SLAVE_MISC_CFG, 97 SDM660_SLAVE_VENUS_THROTTLE_CFG, 98 SDM660_SLAVE_VENUS_CFG, 99 SDM660_SLAVE_MMSS_CLK_XPU_CFG, 100 SDM660_SLAVE_MMSS_CLK_CFG, 101 SDM660_SLAVE_MNOC_MPU_CFG, 102 SDM660_SLAVE_DISPLAY_CFG, 103 SDM660_SLAVE_CSI_PHY_CFG, 104 SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 105 SDM660_SLAVE_SMMU_CFG, 106 SDM660_SLAVE_MNOC_BIMC, 107 SDM660_SLAVE_SRVC_MNOC, 108 SDM660_SLAVE_HMSS, 109 SDM660_SLAVE_LPASS, 110 SDM660_SLAVE_WLAN, 111 SDM660_SLAVE_CDSP, 112 SDM660_SLAVE_IPA, 113 SDM660_SLAVE_SNOC_BIMC, 114 SDM660_SLAVE_SNOC_CNOC, 115 SDM660_SLAVE_IMEM, 116 SDM660_SLAVE_PIMEM, 117 SDM660_SLAVE_QDSS_STM, 118 SDM660_SLAVE_SRVC_SNOC, 119 120 SDM660_A2NOC, 121 SDM660_BIMC, 122 SDM660_CNOC, 123 SDM660_GNOC, 124 SDM660_MNOC, 125 SDM660_SNOC, 126 }; 127 128 static const char * const mm_intf_clocks[] = { 129 "iface", 130 }; 131 132 static const char * const a2noc_intf_clocks[] = { 133 "ipa", 134 "ufs_axi", 135 "aggre2_ufs_axi", 136 "aggre2_usb3_axi", 137 "cfg_noc_usb2_axi", 138 }; 139 140 static const u16 mas_ipa_links[] = { 141 SDM660_SLAVE_A2NOC_SNOC 142 }; 143 144 static struct qcom_icc_node mas_ipa = { 145 .name = "mas_ipa", 146 .id = SDM660_MASTER_IPA, 147 .buswidth = 8, 148 .mas_rpm_id = 59, 149 .slv_rpm_id = -1, 150 .qos.ap_owned = true, 151 .qos.qos_mode = NOC_QOS_MODE_FIXED, 152 .qos.areq_prio = 1, 153 .qos.prio_level = 1, 154 .qos.qos_port = 3, 155 .num_links = ARRAY_SIZE(mas_ipa_links), 156 .links = mas_ipa_links, 157 }; 158 159 static const u16 mas_cnoc_a2noc_links[] = { 160 SDM660_SLAVE_A2NOC_SNOC 161 }; 162 163 static struct qcom_icc_node mas_cnoc_a2noc = { 164 .name = "mas_cnoc_a2noc", 165 .id = SDM660_MASTER_CNOC_A2NOC, 166 .buswidth = 8, 167 .mas_rpm_id = 146, 168 .slv_rpm_id = -1, 169 .qos.ap_owned = true, 170 .qos.qos_mode = NOC_QOS_MODE_INVALID, 171 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links), 172 .links = mas_cnoc_a2noc_links, 173 }; 174 175 static const u16 mas_sdcc_1_links[] = { 176 SDM660_SLAVE_A2NOC_SNOC 177 }; 178 179 static struct qcom_icc_node mas_sdcc_1 = { 180 .name = "mas_sdcc_1", 181 .id = SDM660_MASTER_SDCC_1, 182 .buswidth = 8, 183 .mas_rpm_id = 33, 184 .slv_rpm_id = -1, 185 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 186 .links = mas_sdcc_1_links, 187 }; 188 189 static const u16 mas_sdcc_2_links[] = { 190 SDM660_SLAVE_A2NOC_SNOC 191 }; 192 193 static struct qcom_icc_node mas_sdcc_2 = { 194 .name = "mas_sdcc_2", 195 .id = SDM660_MASTER_SDCC_2, 196 .buswidth = 8, 197 .mas_rpm_id = 35, 198 .slv_rpm_id = -1, 199 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 200 .links = mas_sdcc_2_links, 201 }; 202 203 static const u16 mas_blsp_1_links[] = { 204 SDM660_SLAVE_A2NOC_SNOC 205 }; 206 207 static struct qcom_icc_node mas_blsp_1 = { 208 .name = "mas_blsp_1", 209 .id = SDM660_MASTER_BLSP_1, 210 .buswidth = 4, 211 .mas_rpm_id = 41, 212 .slv_rpm_id = -1, 213 .num_links = ARRAY_SIZE(mas_blsp_1_links), 214 .links = mas_blsp_1_links, 215 }; 216 217 static const u16 mas_blsp_2_links[] = { 218 SDM660_SLAVE_A2NOC_SNOC 219 }; 220 221 static struct qcom_icc_node mas_blsp_2 = { 222 .name = "mas_blsp_2", 223 .id = SDM660_MASTER_BLSP_2, 224 .buswidth = 4, 225 .mas_rpm_id = 39, 226 .slv_rpm_id = -1, 227 .num_links = ARRAY_SIZE(mas_blsp_2_links), 228 .links = mas_blsp_2_links, 229 }; 230 231 static const u16 mas_ufs_links[] = { 232 SDM660_SLAVE_A2NOC_SNOC 233 }; 234 235 static struct qcom_icc_node mas_ufs = { 236 .name = "mas_ufs", 237 .id = SDM660_MASTER_UFS, 238 .buswidth = 8, 239 .mas_rpm_id = 68, 240 .slv_rpm_id = -1, 241 .qos.ap_owned = true, 242 .qos.qos_mode = NOC_QOS_MODE_FIXED, 243 .qos.areq_prio = 1, 244 .qos.prio_level = 1, 245 .qos.qos_port = 4, 246 .num_links = ARRAY_SIZE(mas_ufs_links), 247 .links = mas_ufs_links, 248 }; 249 250 static const u16 mas_usb_hs_links[] = { 251 SDM660_SLAVE_A2NOC_SNOC 252 }; 253 254 static struct qcom_icc_node mas_usb_hs = { 255 .name = "mas_usb_hs", 256 .id = SDM660_MASTER_USB_HS, 257 .buswidth = 8, 258 .mas_rpm_id = 42, 259 .slv_rpm_id = -1, 260 .qos.ap_owned = true, 261 .qos.qos_mode = NOC_QOS_MODE_FIXED, 262 .qos.areq_prio = 1, 263 .qos.prio_level = 1, 264 .qos.qos_port = 1, 265 .num_links = ARRAY_SIZE(mas_usb_hs_links), 266 .links = mas_usb_hs_links, 267 }; 268 269 static const u16 mas_usb3_links[] = { 270 SDM660_SLAVE_A2NOC_SNOC 271 }; 272 273 static struct qcom_icc_node mas_usb3 = { 274 .name = "mas_usb3", 275 .id = SDM660_MASTER_USB3, 276 .buswidth = 8, 277 .mas_rpm_id = 32, 278 .slv_rpm_id = -1, 279 .qos.ap_owned = true, 280 .qos.qos_mode = NOC_QOS_MODE_FIXED, 281 .qos.areq_prio = 1, 282 .qos.prio_level = 1, 283 .qos.qos_port = 2, 284 .num_links = ARRAY_SIZE(mas_usb3_links), 285 .links = mas_usb3_links, 286 }; 287 288 static const u16 mas_crypto_links[] = { 289 SDM660_SLAVE_A2NOC_SNOC 290 }; 291 292 static struct qcom_icc_node mas_crypto = { 293 .name = "mas_crypto", 294 .id = SDM660_MASTER_CRYPTO_C0, 295 .buswidth = 8, 296 .mas_rpm_id = 23, 297 .slv_rpm_id = -1, 298 .qos.ap_owned = true, 299 .qos.qos_mode = NOC_QOS_MODE_FIXED, 300 .qos.areq_prio = 1, 301 .qos.prio_level = 1, 302 .qos.qos_port = 11, 303 .num_links = ARRAY_SIZE(mas_crypto_links), 304 .links = mas_crypto_links, 305 }; 306 307 static const u16 mas_gnoc_bimc_links[] = { 308 SDM660_SLAVE_EBI 309 }; 310 311 static struct qcom_icc_node mas_gnoc_bimc = { 312 .name = "mas_gnoc_bimc", 313 .id = SDM660_MASTER_GNOC_BIMC, 314 .buswidth = 4, 315 .mas_rpm_id = 144, 316 .slv_rpm_id = -1, 317 .qos.ap_owned = true, 318 .qos.qos_mode = NOC_QOS_MODE_FIXED, 319 .qos.areq_prio = 0, 320 .qos.prio_level = 0, 321 .qos.qos_port = 0, 322 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links), 323 .links = mas_gnoc_bimc_links, 324 }; 325 326 static const u16 mas_oxili_links[] = { 327 SDM660_SLAVE_HMSS_L3, 328 SDM660_SLAVE_EBI, 329 SDM660_SLAVE_BIMC_SNOC 330 }; 331 332 static struct qcom_icc_node mas_oxili = { 333 .name = "mas_oxili", 334 .id = SDM660_MASTER_OXILI, 335 .buswidth = 4, 336 .mas_rpm_id = 6, 337 .slv_rpm_id = -1, 338 .qos.ap_owned = true, 339 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 340 .qos.areq_prio = 0, 341 .qos.prio_level = 0, 342 .qos.qos_port = 1, 343 .num_links = ARRAY_SIZE(mas_oxili_links), 344 .links = mas_oxili_links, 345 }; 346 347 static const u16 mas_mnoc_bimc_links[] = { 348 SDM660_SLAVE_HMSS_L3, 349 SDM660_SLAVE_EBI, 350 SDM660_SLAVE_BIMC_SNOC 351 }; 352 353 static struct qcom_icc_node mas_mnoc_bimc = { 354 .name = "mas_mnoc_bimc", 355 .id = SDM660_MASTER_MNOC_BIMC, 356 .buswidth = 4, 357 .mas_rpm_id = 2, 358 .slv_rpm_id = -1, 359 .qos.ap_owned = true, 360 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 361 .qos.areq_prio = 0, 362 .qos.prio_level = 0, 363 .qos.qos_port = 2, 364 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links), 365 .links = mas_mnoc_bimc_links, 366 }; 367 368 static const u16 mas_snoc_bimc_links[] = { 369 SDM660_SLAVE_HMSS_L3, 370 SDM660_SLAVE_EBI 371 }; 372 373 static struct qcom_icc_node mas_snoc_bimc = { 374 .name = "mas_snoc_bimc", 375 .id = SDM660_MASTER_SNOC_BIMC, 376 .buswidth = 4, 377 .mas_rpm_id = 3, 378 .slv_rpm_id = -1, 379 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 380 .links = mas_snoc_bimc_links, 381 }; 382 383 static const u16 mas_pimem_links[] = { 384 SDM660_SLAVE_HMSS_L3, 385 SDM660_SLAVE_EBI 386 }; 387 388 static struct qcom_icc_node mas_pimem = { 389 .name = "mas_pimem", 390 .id = SDM660_MASTER_PIMEM, 391 .buswidth = 4, 392 .mas_rpm_id = 113, 393 .slv_rpm_id = -1, 394 .qos.ap_owned = true, 395 .qos.qos_mode = NOC_QOS_MODE_FIXED, 396 .qos.areq_prio = 1, 397 .qos.prio_level = 1, 398 .qos.qos_port = 4, 399 .num_links = ARRAY_SIZE(mas_pimem_links), 400 .links = mas_pimem_links, 401 }; 402 403 static const u16 mas_snoc_cnoc_links[] = { 404 SDM660_SLAVE_CLK_CTL, 405 SDM660_SLAVE_QDSS_CFG, 406 SDM660_SLAVE_QM_CFG, 407 SDM660_SLAVE_SRVC_CNOC, 408 SDM660_SLAVE_UFS_CFG, 409 SDM660_SLAVE_TCSR, 410 SDM660_SLAVE_A2NOC_SMMU_CFG, 411 SDM660_SLAVE_SNOC_CFG, 412 SDM660_SLAVE_TLMM_SOUTH, 413 SDM660_SLAVE_MPM, 414 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 415 SDM660_SLAVE_SDCC_2, 416 SDM660_SLAVE_SDCC_1, 417 SDM660_SLAVE_SPDM, 418 SDM660_SLAVE_PMIC_ARB, 419 SDM660_SLAVE_PRNG, 420 SDM660_SLAVE_MSS_CFG, 421 SDM660_SLAVE_GPUSS_CFG, 422 SDM660_SLAVE_IMEM_CFG, 423 SDM660_SLAVE_USB3_0, 424 SDM660_SLAVE_A2NOC_CFG, 425 SDM660_SLAVE_TLMM_NORTH, 426 SDM660_SLAVE_USB_HS, 427 SDM660_SLAVE_PDM, 428 SDM660_SLAVE_TLMM_CENTER, 429 SDM660_SLAVE_AHB2PHY, 430 SDM660_SLAVE_BLSP_2, 431 SDM660_SLAVE_BLSP_1, 432 SDM660_SLAVE_PIMEM_CFG, 433 SDM660_SLAVE_GLM, 434 SDM660_SLAVE_MESSAGE_RAM, 435 SDM660_SLAVE_BIMC_CFG, 436 SDM660_SLAVE_CNOC_MNOC_CFG 437 }; 438 439 static struct qcom_icc_node mas_snoc_cnoc = { 440 .name = "mas_snoc_cnoc", 441 .id = SDM660_MASTER_SNOC_CNOC, 442 .buswidth = 8, 443 .mas_rpm_id = 52, 444 .slv_rpm_id = -1, 445 .qos.ap_owned = true, 446 .qos.qos_mode = NOC_QOS_MODE_INVALID, 447 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 448 .links = mas_snoc_cnoc_links, 449 }; 450 451 static const u16 mas_qdss_dap_links[] = { 452 SDM660_SLAVE_CLK_CTL, 453 SDM660_SLAVE_QDSS_CFG, 454 SDM660_SLAVE_QM_CFG, 455 SDM660_SLAVE_SRVC_CNOC, 456 SDM660_SLAVE_UFS_CFG, 457 SDM660_SLAVE_TCSR, 458 SDM660_SLAVE_A2NOC_SMMU_CFG, 459 SDM660_SLAVE_SNOC_CFG, 460 SDM660_SLAVE_TLMM_SOUTH, 461 SDM660_SLAVE_MPM, 462 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 463 SDM660_SLAVE_SDCC_2, 464 SDM660_SLAVE_SDCC_1, 465 SDM660_SLAVE_SPDM, 466 SDM660_SLAVE_PMIC_ARB, 467 SDM660_SLAVE_PRNG, 468 SDM660_SLAVE_MSS_CFG, 469 SDM660_SLAVE_GPUSS_CFG, 470 SDM660_SLAVE_IMEM_CFG, 471 SDM660_SLAVE_USB3_0, 472 SDM660_SLAVE_A2NOC_CFG, 473 SDM660_SLAVE_TLMM_NORTH, 474 SDM660_SLAVE_USB_HS, 475 SDM660_SLAVE_PDM, 476 SDM660_SLAVE_TLMM_CENTER, 477 SDM660_SLAVE_AHB2PHY, 478 SDM660_SLAVE_BLSP_2, 479 SDM660_SLAVE_BLSP_1, 480 SDM660_SLAVE_PIMEM_CFG, 481 SDM660_SLAVE_GLM, 482 SDM660_SLAVE_MESSAGE_RAM, 483 SDM660_SLAVE_CNOC_A2NOC, 484 SDM660_SLAVE_BIMC_CFG, 485 SDM660_SLAVE_CNOC_MNOC_CFG 486 }; 487 488 static struct qcom_icc_node mas_qdss_dap = { 489 .name = "mas_qdss_dap", 490 .id = SDM660_MASTER_QDSS_DAP, 491 .buswidth = 8, 492 .mas_rpm_id = 49, 493 .slv_rpm_id = -1, 494 .qos.ap_owned = true, 495 .qos.qos_mode = NOC_QOS_MODE_INVALID, 496 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 497 .links = mas_qdss_dap_links, 498 }; 499 500 static const u16 mas_apss_proc_links[] = { 501 SDM660_SLAVE_GNOC_SNOC, 502 SDM660_SLAVE_GNOC_BIMC 503 }; 504 505 static struct qcom_icc_node mas_apss_proc = { 506 .name = "mas_apss_proc", 507 .id = SDM660_MASTER_APPS_PROC, 508 .buswidth = 16, 509 .mas_rpm_id = 0, 510 .slv_rpm_id = -1, 511 .qos.ap_owned = true, 512 .qos.qos_mode = NOC_QOS_MODE_INVALID, 513 .num_links = ARRAY_SIZE(mas_apss_proc_links), 514 .links = mas_apss_proc_links, 515 }; 516 517 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { 518 SDM660_SLAVE_VENUS_THROTTLE_CFG, 519 SDM660_SLAVE_VENUS_CFG, 520 SDM660_SLAVE_CAMERA_THROTTLE_CFG, 521 SDM660_SLAVE_SMMU_CFG, 522 SDM660_SLAVE_CAMERA_CFG, 523 SDM660_SLAVE_CSI_PHY_CFG, 524 SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 525 SDM660_SLAVE_DISPLAY_CFG, 526 SDM660_SLAVE_MMSS_CLK_CFG, 527 SDM660_SLAVE_MNOC_MPU_CFG, 528 SDM660_SLAVE_MISC_CFG, 529 SDM660_SLAVE_MMSS_CLK_XPU_CFG 530 }; 531 532 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { 533 .name = "mas_cnoc_mnoc_mmss_cfg", 534 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 535 .buswidth = 8, 536 .mas_rpm_id = 4, 537 .slv_rpm_id = -1, 538 .qos.ap_owned = true, 539 .qos.qos_mode = NOC_QOS_MODE_INVALID, 540 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), 541 .links = mas_cnoc_mnoc_mmss_cfg_links, 542 }; 543 544 static const u16 mas_cnoc_mnoc_cfg_links[] = { 545 SDM660_SLAVE_SRVC_MNOC 546 }; 547 548 static struct qcom_icc_node mas_cnoc_mnoc_cfg = { 549 .name = "mas_cnoc_mnoc_cfg", 550 .id = SDM660_MASTER_CNOC_MNOC_CFG, 551 .buswidth = 4, 552 .mas_rpm_id = 5, 553 .slv_rpm_id = -1, 554 .qos.ap_owned = true, 555 .qos.qos_mode = NOC_QOS_MODE_INVALID, 556 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), 557 .links = mas_cnoc_mnoc_cfg_links, 558 }; 559 560 static const u16 mas_cpp_links[] = { 561 SDM660_SLAVE_MNOC_BIMC 562 }; 563 564 static struct qcom_icc_node mas_cpp = { 565 .name = "mas_cpp", 566 .id = SDM660_MASTER_CPP, 567 .buswidth = 16, 568 .mas_rpm_id = 115, 569 .slv_rpm_id = -1, 570 .qos.ap_owned = true, 571 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 572 .qos.areq_prio = 0, 573 .qos.prio_level = 0, 574 .qos.qos_port = 4, 575 .num_links = ARRAY_SIZE(mas_cpp_links), 576 .links = mas_cpp_links, 577 }; 578 579 static const u16 mas_jpeg_links[] = { 580 SDM660_SLAVE_MNOC_BIMC 581 }; 582 583 static struct qcom_icc_node mas_jpeg = { 584 .name = "mas_jpeg", 585 .id = SDM660_MASTER_JPEG, 586 .buswidth = 16, 587 .mas_rpm_id = 7, 588 .slv_rpm_id = -1, 589 .qos.ap_owned = true, 590 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 591 .qos.areq_prio = 0, 592 .qos.prio_level = 0, 593 .qos.qos_port = 6, 594 .num_links = ARRAY_SIZE(mas_jpeg_links), 595 .links = mas_jpeg_links, 596 }; 597 598 static const u16 mas_mdp_p0_links[] = { 599 SDM660_SLAVE_MNOC_BIMC 600 }; 601 602 static struct qcom_icc_node mas_mdp_p0 = { 603 .name = "mas_mdp_p0", 604 .id = SDM660_MASTER_MDP_P0, 605 .buswidth = 16, 606 .mas_rpm_id = 8, 607 .slv_rpm_id = -1, 608 .qos.ap_owned = true, 609 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 610 .qos.areq_prio = 0, 611 .qos.prio_level = 0, 612 .qos.qos_port = 0, 613 .num_links = ARRAY_SIZE(mas_mdp_p0_links), 614 .links = mas_mdp_p0_links, 615 }; 616 617 static const u16 mas_mdp_p1_links[] = { 618 SDM660_SLAVE_MNOC_BIMC 619 }; 620 621 static struct qcom_icc_node mas_mdp_p1 = { 622 .name = "mas_mdp_p1", 623 .id = SDM660_MASTER_MDP_P1, 624 .buswidth = 16, 625 .mas_rpm_id = 61, 626 .slv_rpm_id = -1, 627 .qos.ap_owned = true, 628 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 629 .qos.areq_prio = 0, 630 .qos.prio_level = 0, 631 .qos.qos_port = 1, 632 .num_links = ARRAY_SIZE(mas_mdp_p1_links), 633 .links = mas_mdp_p1_links, 634 }; 635 636 static const u16 mas_venus_links[] = { 637 SDM660_SLAVE_MNOC_BIMC 638 }; 639 640 static struct qcom_icc_node mas_venus = { 641 .name = "mas_venus", 642 .id = SDM660_MASTER_VENUS, 643 .buswidth = 16, 644 .mas_rpm_id = 9, 645 .slv_rpm_id = -1, 646 .qos.ap_owned = true, 647 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 648 .qos.areq_prio = 0, 649 .qos.prio_level = 0, 650 .qos.qos_port = 1, 651 .num_links = ARRAY_SIZE(mas_venus_links), 652 .links = mas_venus_links, 653 }; 654 655 static const u16 mas_vfe_links[] = { 656 SDM660_SLAVE_MNOC_BIMC 657 }; 658 659 static struct qcom_icc_node mas_vfe = { 660 .name = "mas_vfe", 661 .id = SDM660_MASTER_VFE, 662 .buswidth = 16, 663 .mas_rpm_id = 11, 664 .slv_rpm_id = -1, 665 .qos.ap_owned = true, 666 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 667 .qos.areq_prio = 0, 668 .qos.prio_level = 0, 669 .qos.qos_port = 5, 670 .num_links = ARRAY_SIZE(mas_vfe_links), 671 .links = mas_vfe_links, 672 }; 673 674 static const u16 mas_qdss_etr_links[] = { 675 SDM660_SLAVE_PIMEM, 676 SDM660_SLAVE_IMEM, 677 SDM660_SLAVE_SNOC_CNOC, 678 SDM660_SLAVE_SNOC_BIMC 679 }; 680 681 static struct qcom_icc_node mas_qdss_etr = { 682 .name = "mas_qdss_etr", 683 .id = SDM660_MASTER_QDSS_ETR, 684 .buswidth = 8, 685 .mas_rpm_id = 31, 686 .slv_rpm_id = -1, 687 .qos.ap_owned = true, 688 .qos.qos_mode = NOC_QOS_MODE_FIXED, 689 .qos.areq_prio = 1, 690 .qos.prio_level = 1, 691 .qos.qos_port = 1, 692 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 693 .links = mas_qdss_etr_links, 694 }; 695 696 static const u16 mas_qdss_bam_links[] = { 697 SDM660_SLAVE_PIMEM, 698 SDM660_SLAVE_IMEM, 699 SDM660_SLAVE_SNOC_CNOC, 700 SDM660_SLAVE_SNOC_BIMC 701 }; 702 703 static struct qcom_icc_node mas_qdss_bam = { 704 .name = "mas_qdss_bam", 705 .id = SDM660_MASTER_QDSS_BAM, 706 .buswidth = 4, 707 .mas_rpm_id = 19, 708 .slv_rpm_id = -1, 709 .qos.ap_owned = true, 710 .qos.qos_mode = NOC_QOS_MODE_FIXED, 711 .qos.areq_prio = 1, 712 .qos.prio_level = 1, 713 .qos.qos_port = 0, 714 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 715 .links = mas_qdss_bam_links, 716 }; 717 718 static const u16 mas_snoc_cfg_links[] = { 719 SDM660_SLAVE_SRVC_SNOC 720 }; 721 722 static struct qcom_icc_node mas_snoc_cfg = { 723 .name = "mas_snoc_cfg", 724 .id = SDM660_MASTER_SNOC_CFG, 725 .buswidth = 4, 726 .mas_rpm_id = 20, 727 .slv_rpm_id = -1, 728 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 729 .links = mas_snoc_cfg_links, 730 }; 731 732 static const u16 mas_bimc_snoc_links[] = { 733 SDM660_SLAVE_PIMEM, 734 SDM660_SLAVE_IPA, 735 SDM660_SLAVE_QDSS_STM, 736 SDM660_SLAVE_LPASS, 737 SDM660_SLAVE_HMSS, 738 SDM660_SLAVE_CDSP, 739 SDM660_SLAVE_SNOC_CNOC, 740 SDM660_SLAVE_WLAN, 741 SDM660_SLAVE_IMEM 742 }; 743 744 static struct qcom_icc_node mas_bimc_snoc = { 745 .name = "mas_bimc_snoc", 746 .id = SDM660_MASTER_BIMC_SNOC, 747 .buswidth = 8, 748 .mas_rpm_id = 21, 749 .slv_rpm_id = -1, 750 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 751 .links = mas_bimc_snoc_links, 752 }; 753 754 static const u16 mas_gnoc_snoc_links[] = { 755 SDM660_SLAVE_PIMEM, 756 SDM660_SLAVE_IPA, 757 SDM660_SLAVE_QDSS_STM, 758 SDM660_SLAVE_LPASS, 759 SDM660_SLAVE_HMSS, 760 SDM660_SLAVE_CDSP, 761 SDM660_SLAVE_SNOC_CNOC, 762 SDM660_SLAVE_WLAN, 763 SDM660_SLAVE_IMEM 764 }; 765 766 static struct qcom_icc_node mas_gnoc_snoc = { 767 .name = "mas_gnoc_snoc", 768 .id = SDM660_MASTER_GNOC_SNOC, 769 .buswidth = 8, 770 .mas_rpm_id = 150, 771 .slv_rpm_id = -1, 772 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links), 773 .links = mas_gnoc_snoc_links, 774 }; 775 776 static const u16 mas_a2noc_snoc_links[] = { 777 SDM660_SLAVE_PIMEM, 778 SDM660_SLAVE_IPA, 779 SDM660_SLAVE_QDSS_STM, 780 SDM660_SLAVE_LPASS, 781 SDM660_SLAVE_HMSS, 782 SDM660_SLAVE_SNOC_BIMC, 783 SDM660_SLAVE_CDSP, 784 SDM660_SLAVE_SNOC_CNOC, 785 SDM660_SLAVE_WLAN, 786 SDM660_SLAVE_IMEM 787 }; 788 789 static struct qcom_icc_node mas_a2noc_snoc = { 790 .name = "mas_a2noc_snoc", 791 .id = SDM660_MASTER_A2NOC_SNOC, 792 .buswidth = 16, 793 .mas_rpm_id = 112, 794 .slv_rpm_id = -1, 795 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), 796 .links = mas_a2noc_snoc_links, 797 }; 798 799 static const u16 slv_a2noc_snoc_links[] = { 800 SDM660_MASTER_A2NOC_SNOC 801 }; 802 803 static struct qcom_icc_node slv_a2noc_snoc = { 804 .name = "slv_a2noc_snoc", 805 .id = SDM660_SLAVE_A2NOC_SNOC, 806 .buswidth = 16, 807 .mas_rpm_id = -1, 808 .slv_rpm_id = 143, 809 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), 810 .links = slv_a2noc_snoc_links, 811 }; 812 813 static struct qcom_icc_node slv_ebi = { 814 .name = "slv_ebi", 815 .id = SDM660_SLAVE_EBI, 816 .buswidth = 4, 817 .mas_rpm_id = -1, 818 .slv_rpm_id = 0, 819 }; 820 821 static struct qcom_icc_node slv_hmss_l3 = { 822 .name = "slv_hmss_l3", 823 .id = SDM660_SLAVE_HMSS_L3, 824 .buswidth = 4, 825 .mas_rpm_id = -1, 826 .slv_rpm_id = 160, 827 }; 828 829 static const u16 slv_bimc_snoc_links[] = { 830 SDM660_MASTER_BIMC_SNOC 831 }; 832 833 static struct qcom_icc_node slv_bimc_snoc = { 834 .name = "slv_bimc_snoc", 835 .id = SDM660_SLAVE_BIMC_SNOC, 836 .buswidth = 4, 837 .mas_rpm_id = -1, 838 .slv_rpm_id = 2, 839 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 840 .links = slv_bimc_snoc_links, 841 }; 842 843 static const u16 slv_cnoc_a2noc_links[] = { 844 SDM660_MASTER_CNOC_A2NOC 845 }; 846 847 static struct qcom_icc_node slv_cnoc_a2noc = { 848 .name = "slv_cnoc_a2noc", 849 .id = SDM660_SLAVE_CNOC_A2NOC, 850 .buswidth = 8, 851 .mas_rpm_id = -1, 852 .slv_rpm_id = 208, 853 .qos.ap_owned = true, 854 .qos.qos_mode = NOC_QOS_MODE_INVALID, 855 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links), 856 .links = slv_cnoc_a2noc_links, 857 }; 858 859 static struct qcom_icc_node slv_mpm = { 860 .name = "slv_mpm", 861 .id = SDM660_SLAVE_MPM, 862 .buswidth = 4, 863 .mas_rpm_id = -1, 864 .slv_rpm_id = 62, 865 .qos.ap_owned = true, 866 .qos.qos_mode = NOC_QOS_MODE_INVALID, 867 }; 868 869 static struct qcom_icc_node slv_pmic_arb = { 870 .name = "slv_pmic_arb", 871 .id = SDM660_SLAVE_PMIC_ARB, 872 .buswidth = 4, 873 .mas_rpm_id = -1, 874 .slv_rpm_id = 59, 875 .qos.ap_owned = true, 876 .qos.qos_mode = NOC_QOS_MODE_INVALID, 877 }; 878 879 static struct qcom_icc_node slv_tlmm_north = { 880 .name = "slv_tlmm_north", 881 .id = SDM660_SLAVE_TLMM_NORTH, 882 .buswidth = 8, 883 .mas_rpm_id = -1, 884 .slv_rpm_id = 214, 885 .qos.ap_owned = true, 886 .qos.qos_mode = NOC_QOS_MODE_INVALID, 887 }; 888 889 static struct qcom_icc_node slv_tcsr = { 890 .name = "slv_tcsr", 891 .id = SDM660_SLAVE_TCSR, 892 .buswidth = 4, 893 .mas_rpm_id = -1, 894 .slv_rpm_id = 50, 895 .qos.ap_owned = true, 896 .qos.qos_mode = NOC_QOS_MODE_INVALID, 897 }; 898 899 static struct qcom_icc_node slv_pimem_cfg = { 900 .name = "slv_pimem_cfg", 901 .id = SDM660_SLAVE_PIMEM_CFG, 902 .buswidth = 4, 903 .mas_rpm_id = -1, 904 .slv_rpm_id = 167, 905 .qos.ap_owned = true, 906 .qos.qos_mode = NOC_QOS_MODE_INVALID, 907 }; 908 909 static struct qcom_icc_node slv_imem_cfg = { 910 .name = "slv_imem_cfg", 911 .id = SDM660_SLAVE_IMEM_CFG, 912 .buswidth = 4, 913 .mas_rpm_id = -1, 914 .slv_rpm_id = 54, 915 .qos.ap_owned = true, 916 .qos.qos_mode = NOC_QOS_MODE_INVALID, 917 }; 918 919 static struct qcom_icc_node slv_message_ram = { 920 .name = "slv_message_ram", 921 .id = SDM660_SLAVE_MESSAGE_RAM, 922 .buswidth = 4, 923 .mas_rpm_id = -1, 924 .slv_rpm_id = 55, 925 .qos.ap_owned = true, 926 .qos.qos_mode = NOC_QOS_MODE_INVALID, 927 }; 928 929 static struct qcom_icc_node slv_glm = { 930 .name = "slv_glm", 931 .id = SDM660_SLAVE_GLM, 932 .buswidth = 4, 933 .mas_rpm_id = -1, 934 .slv_rpm_id = 209, 935 .qos.ap_owned = true, 936 .qos.qos_mode = NOC_QOS_MODE_INVALID, 937 }; 938 939 static struct qcom_icc_node slv_bimc_cfg = { 940 .name = "slv_bimc_cfg", 941 .id = SDM660_SLAVE_BIMC_CFG, 942 .buswidth = 4, 943 .mas_rpm_id = -1, 944 .slv_rpm_id = 56, 945 .qos.ap_owned = true, 946 .qos.qos_mode = NOC_QOS_MODE_INVALID, 947 }; 948 949 static struct qcom_icc_node slv_prng = { 950 .name = "slv_prng", 951 .id = SDM660_SLAVE_PRNG, 952 .buswidth = 4, 953 .mas_rpm_id = -1, 954 .slv_rpm_id = 44, 955 .qos.ap_owned = true, 956 .qos.qos_mode = NOC_QOS_MODE_INVALID, 957 }; 958 959 static struct qcom_icc_node slv_spdm = { 960 .name = "slv_spdm", 961 .id = SDM660_SLAVE_SPDM, 962 .buswidth = 4, 963 .mas_rpm_id = -1, 964 .slv_rpm_id = 60, 965 .qos.ap_owned = true, 966 .qos.qos_mode = NOC_QOS_MODE_INVALID, 967 }; 968 969 static struct qcom_icc_node slv_qdss_cfg = { 970 .name = "slv_qdss_cfg", 971 .id = SDM660_SLAVE_QDSS_CFG, 972 .buswidth = 4, 973 .mas_rpm_id = -1, 974 .slv_rpm_id = 63, 975 .qos.ap_owned = true, 976 .qos.qos_mode = NOC_QOS_MODE_INVALID, 977 }; 978 979 static const u16 slv_cnoc_mnoc_cfg_links[] = { 980 SDM660_MASTER_CNOC_MNOC_CFG 981 }; 982 983 static struct qcom_icc_node slv_cnoc_mnoc_cfg = { 984 .name = "slv_cnoc_mnoc_cfg", 985 .id = SDM660_SLAVE_CNOC_MNOC_CFG, 986 .buswidth = 4, 987 .mas_rpm_id = -1, 988 .slv_rpm_id = 66, 989 .qos.ap_owned = true, 990 .qos.qos_mode = NOC_QOS_MODE_INVALID, 991 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), 992 .links = slv_cnoc_mnoc_cfg_links, 993 }; 994 995 static struct qcom_icc_node slv_snoc_cfg = { 996 .name = "slv_snoc_cfg", 997 .id = SDM660_SLAVE_SNOC_CFG, 998 .buswidth = 4, 999 .mas_rpm_id = -1, 1000 .slv_rpm_id = 70, 1001 .qos.ap_owned = true, 1002 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1003 }; 1004 1005 static struct qcom_icc_node slv_qm_cfg = { 1006 .name = "slv_qm_cfg", 1007 .id = SDM660_SLAVE_QM_CFG, 1008 .buswidth = 4, 1009 .mas_rpm_id = -1, 1010 .slv_rpm_id = 212, 1011 .qos.ap_owned = true, 1012 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1013 }; 1014 1015 static struct qcom_icc_node slv_clk_ctl = { 1016 .name = "slv_clk_ctl", 1017 .id = SDM660_SLAVE_CLK_CTL, 1018 .buswidth = 4, 1019 .mas_rpm_id = -1, 1020 .slv_rpm_id = 47, 1021 .qos.ap_owned = true, 1022 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1023 }; 1024 1025 static struct qcom_icc_node slv_mss_cfg = { 1026 .name = "slv_mss_cfg", 1027 .id = SDM660_SLAVE_MSS_CFG, 1028 .buswidth = 4, 1029 .mas_rpm_id = -1, 1030 .slv_rpm_id = 48, 1031 .qos.ap_owned = true, 1032 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1033 }; 1034 1035 static struct qcom_icc_node slv_tlmm_south = { 1036 .name = "slv_tlmm_south", 1037 .id = SDM660_SLAVE_TLMM_SOUTH, 1038 .buswidth = 4, 1039 .mas_rpm_id = -1, 1040 .slv_rpm_id = 217, 1041 .qos.ap_owned = true, 1042 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1043 }; 1044 1045 static struct qcom_icc_node slv_ufs_cfg = { 1046 .name = "slv_ufs_cfg", 1047 .id = SDM660_SLAVE_UFS_CFG, 1048 .buswidth = 4, 1049 .mas_rpm_id = -1, 1050 .slv_rpm_id = 92, 1051 .qos.ap_owned = true, 1052 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1053 }; 1054 1055 static struct qcom_icc_node slv_a2noc_cfg = { 1056 .name = "slv_a2noc_cfg", 1057 .id = SDM660_SLAVE_A2NOC_CFG, 1058 .buswidth = 4, 1059 .mas_rpm_id = -1, 1060 .slv_rpm_id = 150, 1061 .qos.ap_owned = true, 1062 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1063 }; 1064 1065 static struct qcom_icc_node slv_a2noc_smmu_cfg = { 1066 .name = "slv_a2noc_smmu_cfg", 1067 .id = SDM660_SLAVE_A2NOC_SMMU_CFG, 1068 .buswidth = 8, 1069 .mas_rpm_id = -1, 1070 .slv_rpm_id = 152, 1071 .qos.ap_owned = true, 1072 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1073 }; 1074 1075 static struct qcom_icc_node slv_gpuss_cfg = { 1076 .name = "slv_gpuss_cfg", 1077 .id = SDM660_SLAVE_GPUSS_CFG, 1078 .buswidth = 8, 1079 .mas_rpm_id = -1, 1080 .slv_rpm_id = 11, 1081 .qos.ap_owned = true, 1082 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1083 }; 1084 1085 static struct qcom_icc_node slv_ahb2phy = { 1086 .name = "slv_ahb2phy", 1087 .id = SDM660_SLAVE_AHB2PHY, 1088 .buswidth = 4, 1089 .mas_rpm_id = -1, 1090 .slv_rpm_id = 163, 1091 .qos.ap_owned = true, 1092 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1093 }; 1094 1095 static struct qcom_icc_node slv_blsp_1 = { 1096 .name = "slv_blsp_1", 1097 .id = SDM660_SLAVE_BLSP_1, 1098 .buswidth = 4, 1099 .mas_rpm_id = -1, 1100 .slv_rpm_id = 39, 1101 .qos.ap_owned = true, 1102 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1103 }; 1104 1105 static struct qcom_icc_node slv_sdcc_1 = { 1106 .name = "slv_sdcc_1", 1107 .id = SDM660_SLAVE_SDCC_1, 1108 .buswidth = 4, 1109 .mas_rpm_id = -1, 1110 .slv_rpm_id = 31, 1111 .qos.ap_owned = true, 1112 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1113 }; 1114 1115 static struct qcom_icc_node slv_sdcc_2 = { 1116 .name = "slv_sdcc_2", 1117 .id = SDM660_SLAVE_SDCC_2, 1118 .buswidth = 4, 1119 .mas_rpm_id = -1, 1120 .slv_rpm_id = 33, 1121 .qos.ap_owned = true, 1122 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1123 }; 1124 1125 static struct qcom_icc_node slv_tlmm_center = { 1126 .name = "slv_tlmm_center", 1127 .id = SDM660_SLAVE_TLMM_CENTER, 1128 .buswidth = 4, 1129 .mas_rpm_id = -1, 1130 .slv_rpm_id = 218, 1131 .qos.ap_owned = true, 1132 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1133 }; 1134 1135 static struct qcom_icc_node slv_blsp_2 = { 1136 .name = "slv_blsp_2", 1137 .id = SDM660_SLAVE_BLSP_2, 1138 .buswidth = 4, 1139 .mas_rpm_id = -1, 1140 .slv_rpm_id = 37, 1141 .qos.ap_owned = true, 1142 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1143 }; 1144 1145 static struct qcom_icc_node slv_pdm = { 1146 .name = "slv_pdm", 1147 .id = SDM660_SLAVE_PDM, 1148 .buswidth = 4, 1149 .mas_rpm_id = -1, 1150 .slv_rpm_id = 41, 1151 .qos.ap_owned = true, 1152 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1153 }; 1154 1155 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { 1156 SDM660_MASTER_CNOC_MNOC_MMSS_CFG 1157 }; 1158 1159 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { 1160 .name = "slv_cnoc_mnoc_mmss_cfg", 1161 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 1162 .buswidth = 8, 1163 .mas_rpm_id = -1, 1164 .slv_rpm_id = 58, 1165 .qos.ap_owned = true, 1166 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1167 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), 1168 .links = slv_cnoc_mnoc_mmss_cfg_links, 1169 }; 1170 1171 static struct qcom_icc_node slv_usb_hs = { 1172 .name = "slv_usb_hs", 1173 .id = SDM660_SLAVE_USB_HS, 1174 .buswidth = 4, 1175 .mas_rpm_id = -1, 1176 .slv_rpm_id = 40, 1177 .qos.ap_owned = true, 1178 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1179 }; 1180 1181 static struct qcom_icc_node slv_usb3_0 = { 1182 .name = "slv_usb3_0", 1183 .id = SDM660_SLAVE_USB3_0, 1184 .buswidth = 4, 1185 .mas_rpm_id = -1, 1186 .slv_rpm_id = 22, 1187 .qos.ap_owned = true, 1188 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1189 }; 1190 1191 static struct qcom_icc_node slv_srvc_cnoc = { 1192 .name = "slv_srvc_cnoc", 1193 .id = SDM660_SLAVE_SRVC_CNOC, 1194 .buswidth = 4, 1195 .mas_rpm_id = -1, 1196 .slv_rpm_id = 76, 1197 .qos.ap_owned = true, 1198 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1199 }; 1200 1201 static const u16 slv_gnoc_bimc_links[] = { 1202 SDM660_MASTER_GNOC_BIMC 1203 }; 1204 1205 static struct qcom_icc_node slv_gnoc_bimc = { 1206 .name = "slv_gnoc_bimc", 1207 .id = SDM660_SLAVE_GNOC_BIMC, 1208 .buswidth = 16, 1209 .mas_rpm_id = -1, 1210 .slv_rpm_id = 210, 1211 .qos.ap_owned = true, 1212 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1213 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links), 1214 .links = slv_gnoc_bimc_links, 1215 }; 1216 1217 static const u16 slv_gnoc_snoc_links[] = { 1218 SDM660_MASTER_GNOC_SNOC 1219 }; 1220 1221 static struct qcom_icc_node slv_gnoc_snoc = { 1222 .name = "slv_gnoc_snoc", 1223 .id = SDM660_SLAVE_GNOC_SNOC, 1224 .buswidth = 8, 1225 .mas_rpm_id = -1, 1226 .slv_rpm_id = 211, 1227 .qos.ap_owned = true, 1228 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1229 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links), 1230 .links = slv_gnoc_snoc_links, 1231 }; 1232 1233 static struct qcom_icc_node slv_camera_cfg = { 1234 .name = "slv_camera_cfg", 1235 .id = SDM660_SLAVE_CAMERA_CFG, 1236 .buswidth = 4, 1237 .mas_rpm_id = -1, 1238 .slv_rpm_id = 3, 1239 .qos.ap_owned = true, 1240 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1241 }; 1242 1243 static struct qcom_icc_node slv_camera_throttle_cfg = { 1244 .name = "slv_camera_throttle_cfg", 1245 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG, 1246 .buswidth = 4, 1247 .mas_rpm_id = -1, 1248 .slv_rpm_id = 154, 1249 .qos.ap_owned = true, 1250 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1251 }; 1252 1253 static struct qcom_icc_node slv_misc_cfg = { 1254 .name = "slv_misc_cfg", 1255 .id = SDM660_SLAVE_MISC_CFG, 1256 .buswidth = 4, 1257 .mas_rpm_id = -1, 1258 .slv_rpm_id = 8, 1259 .qos.ap_owned = true, 1260 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1261 }; 1262 1263 static struct qcom_icc_node slv_venus_throttle_cfg = { 1264 .name = "slv_venus_throttle_cfg", 1265 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG, 1266 .buswidth = 4, 1267 .mas_rpm_id = -1, 1268 .slv_rpm_id = 178, 1269 .qos.ap_owned = true, 1270 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1271 }; 1272 1273 static struct qcom_icc_node slv_venus_cfg = { 1274 .name = "slv_venus_cfg", 1275 .id = SDM660_SLAVE_VENUS_CFG, 1276 .buswidth = 4, 1277 .mas_rpm_id = -1, 1278 .slv_rpm_id = 10, 1279 .qos.ap_owned = true, 1280 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1281 }; 1282 1283 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = { 1284 .name = "slv_mmss_clk_xpu_cfg", 1285 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG, 1286 .buswidth = 4, 1287 .mas_rpm_id = -1, 1288 .slv_rpm_id = 13, 1289 .qos.ap_owned = true, 1290 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1291 }; 1292 1293 static struct qcom_icc_node slv_mmss_clk_cfg = { 1294 .name = "slv_mmss_clk_cfg", 1295 .id = SDM660_SLAVE_MMSS_CLK_CFG, 1296 .buswidth = 4, 1297 .mas_rpm_id = -1, 1298 .slv_rpm_id = 12, 1299 .qos.ap_owned = true, 1300 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1301 }; 1302 1303 static struct qcom_icc_node slv_mnoc_mpu_cfg = { 1304 .name = "slv_mnoc_mpu_cfg", 1305 .id = SDM660_SLAVE_MNOC_MPU_CFG, 1306 .buswidth = 4, 1307 .mas_rpm_id = -1, 1308 .slv_rpm_id = 14, 1309 .qos.ap_owned = true, 1310 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1311 }; 1312 1313 static struct qcom_icc_node slv_display_cfg = { 1314 .name = "slv_display_cfg", 1315 .id = SDM660_SLAVE_DISPLAY_CFG, 1316 .buswidth = 4, 1317 .mas_rpm_id = -1, 1318 .slv_rpm_id = 4, 1319 .qos.ap_owned = true, 1320 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1321 }; 1322 1323 static struct qcom_icc_node slv_csi_phy_cfg = { 1324 .name = "slv_csi_phy_cfg", 1325 .id = SDM660_SLAVE_CSI_PHY_CFG, 1326 .buswidth = 4, 1327 .mas_rpm_id = -1, 1328 .slv_rpm_id = 224, 1329 .qos.ap_owned = true, 1330 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1331 }; 1332 1333 static struct qcom_icc_node slv_display_throttle_cfg = { 1334 .name = "slv_display_throttle_cfg", 1335 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 1336 .buswidth = 4, 1337 .mas_rpm_id = -1, 1338 .slv_rpm_id = 156, 1339 .qos.ap_owned = true, 1340 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1341 }; 1342 1343 static struct qcom_icc_node slv_smmu_cfg = { 1344 .name = "slv_smmu_cfg", 1345 .id = SDM660_SLAVE_SMMU_CFG, 1346 .buswidth = 8, 1347 .mas_rpm_id = -1, 1348 .slv_rpm_id = 205, 1349 .qos.ap_owned = true, 1350 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1351 }; 1352 1353 static const u16 slv_mnoc_bimc_links[] = { 1354 SDM660_MASTER_MNOC_BIMC 1355 }; 1356 1357 static struct qcom_icc_node slv_mnoc_bimc = { 1358 .name = "slv_mnoc_bimc", 1359 .id = SDM660_SLAVE_MNOC_BIMC, 1360 .buswidth = 16, 1361 .mas_rpm_id = -1, 1362 .slv_rpm_id = 16, 1363 .qos.ap_owned = true, 1364 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1365 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), 1366 .links = slv_mnoc_bimc_links, 1367 }; 1368 1369 static struct qcom_icc_node slv_srvc_mnoc = { 1370 .name = "slv_srvc_mnoc", 1371 .id = SDM660_SLAVE_SRVC_MNOC, 1372 .buswidth = 8, 1373 .mas_rpm_id = -1, 1374 .slv_rpm_id = 17, 1375 .qos.ap_owned = true, 1376 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1377 }; 1378 1379 static struct qcom_icc_node slv_hmss = { 1380 .name = "slv_hmss", 1381 .id = SDM660_SLAVE_HMSS, 1382 .buswidth = 8, 1383 .mas_rpm_id = -1, 1384 .slv_rpm_id = 20, 1385 .qos.ap_owned = true, 1386 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1387 }; 1388 1389 static struct qcom_icc_node slv_lpass = { 1390 .name = "slv_lpass", 1391 .id = SDM660_SLAVE_LPASS, 1392 .buswidth = 4, 1393 .mas_rpm_id = -1, 1394 .slv_rpm_id = 21, 1395 .qos.ap_owned = true, 1396 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1397 }; 1398 1399 static struct qcom_icc_node slv_wlan = { 1400 .name = "slv_wlan", 1401 .id = SDM660_SLAVE_WLAN, 1402 .buswidth = 4, 1403 .mas_rpm_id = -1, 1404 .slv_rpm_id = 206, 1405 }; 1406 1407 static struct qcom_icc_node slv_cdsp = { 1408 .name = "slv_cdsp", 1409 .id = SDM660_SLAVE_CDSP, 1410 .buswidth = 4, 1411 .mas_rpm_id = -1, 1412 .slv_rpm_id = 221, 1413 .qos.ap_owned = true, 1414 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1415 }; 1416 1417 static struct qcom_icc_node slv_ipa = { 1418 .name = "slv_ipa", 1419 .id = SDM660_SLAVE_IPA, 1420 .buswidth = 4, 1421 .mas_rpm_id = -1, 1422 .slv_rpm_id = 183, 1423 .qos.ap_owned = true, 1424 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1425 }; 1426 1427 static const u16 slv_snoc_bimc_links[] = { 1428 SDM660_MASTER_SNOC_BIMC 1429 }; 1430 1431 static struct qcom_icc_node slv_snoc_bimc = { 1432 .name = "slv_snoc_bimc", 1433 .id = SDM660_SLAVE_SNOC_BIMC, 1434 .buswidth = 16, 1435 .mas_rpm_id = -1, 1436 .slv_rpm_id = 24, 1437 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1438 .links = slv_snoc_bimc_links, 1439 }; 1440 1441 static const u16 slv_snoc_cnoc_links[] = { 1442 SDM660_MASTER_SNOC_CNOC 1443 }; 1444 1445 static struct qcom_icc_node slv_snoc_cnoc = { 1446 .name = "slv_snoc_cnoc", 1447 .id = SDM660_SLAVE_SNOC_CNOC, 1448 .buswidth = 8, 1449 .mas_rpm_id = -1, 1450 .slv_rpm_id = 25, 1451 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1452 .links = slv_snoc_cnoc_links, 1453 }; 1454 1455 static struct qcom_icc_node slv_imem = { 1456 .name = "slv_imem", 1457 .id = SDM660_SLAVE_IMEM, 1458 .buswidth = 8, 1459 .mas_rpm_id = -1, 1460 .slv_rpm_id = 26, 1461 }; 1462 1463 static struct qcom_icc_node slv_pimem = { 1464 .name = "slv_pimem", 1465 .id = SDM660_SLAVE_PIMEM, 1466 .buswidth = 8, 1467 .mas_rpm_id = -1, 1468 .slv_rpm_id = 166, 1469 }; 1470 1471 static struct qcom_icc_node slv_qdss_stm = { 1472 .name = "slv_qdss_stm", 1473 .id = SDM660_SLAVE_QDSS_STM, 1474 .buswidth = 4, 1475 .mas_rpm_id = -1, 1476 .slv_rpm_id = 30, 1477 }; 1478 1479 static struct qcom_icc_node slv_srvc_snoc = { 1480 .name = "slv_srvc_snoc", 1481 .id = SDM660_SLAVE_SRVC_SNOC, 1482 .buswidth = 16, 1483 .mas_rpm_id = -1, 1484 .slv_rpm_id = 29, 1485 }; 1486 1487 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = { 1488 [MASTER_IPA] = &mas_ipa, 1489 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc, 1490 [MASTER_SDCC_1] = &mas_sdcc_1, 1491 [MASTER_SDCC_2] = &mas_sdcc_2, 1492 [MASTER_BLSP_1] = &mas_blsp_1, 1493 [MASTER_BLSP_2] = &mas_blsp_2, 1494 [MASTER_UFS] = &mas_ufs, 1495 [MASTER_USB_HS] = &mas_usb_hs, 1496 [MASTER_USB3] = &mas_usb3, 1497 [MASTER_CRYPTO_C0] = &mas_crypto, 1498 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, 1499 }; 1500 1501 static const struct regmap_config sdm660_a2noc_regmap_config = { 1502 .reg_bits = 32, 1503 .reg_stride = 4, 1504 .val_bits = 32, 1505 .max_register = 0x20000, 1506 .fast_io = true, 1507 }; 1508 1509 static const struct qcom_icc_desc sdm660_a2noc = { 1510 .type = QCOM_ICC_NOC, 1511 .nodes = sdm660_a2noc_nodes, 1512 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), 1513 .bus_clk_desc = &aggre2_clk, 1514 .intf_clocks = a2noc_intf_clocks, 1515 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks), 1516 .regmap_cfg = &sdm660_a2noc_regmap_config, 1517 }; 1518 1519 static struct qcom_icc_node * const sdm660_bimc_nodes[] = { 1520 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc, 1521 [MASTER_OXILI] = &mas_oxili, 1522 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, 1523 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1524 [MASTER_PIMEM] = &mas_pimem, 1525 [SLAVE_EBI] = &slv_ebi, 1526 [SLAVE_HMSS_L3] = &slv_hmss_l3, 1527 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1528 }; 1529 1530 static const struct regmap_config sdm660_bimc_regmap_config = { 1531 .reg_bits = 32, 1532 .reg_stride = 4, 1533 .val_bits = 32, 1534 .max_register = 0x80000, 1535 .fast_io = true, 1536 }; 1537 1538 static const struct qcom_icc_desc sdm660_bimc = { 1539 .type = QCOM_ICC_BIMC, 1540 .nodes = sdm660_bimc_nodes, 1541 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), 1542 .bus_clk_desc = &bimc_clk, 1543 .regmap_cfg = &sdm660_bimc_regmap_config, 1544 }; 1545 1546 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { 1547 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1548 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1549 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc, 1550 [SLAVE_MPM] = &slv_mpm, 1551 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1552 [SLAVE_TLMM_NORTH] = &slv_tlmm_north, 1553 [SLAVE_TCSR] = &slv_tcsr, 1554 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1555 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1556 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1557 [SLAVE_GLM] = &slv_glm, 1558 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1559 [SLAVE_PRNG] = &slv_prng, 1560 [SLAVE_SPDM] = &slv_spdm, 1561 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1562 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, 1563 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1564 [SLAVE_QM_CFG] = &slv_qm_cfg, 1565 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1566 [SLAVE_MSS_CFG] = &slv_mss_cfg, 1567 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south, 1568 [SLAVE_UFS_CFG] = &slv_ufs_cfg, 1569 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, 1570 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, 1571 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg, 1572 [SLAVE_AHB2PHY] = &slv_ahb2phy, 1573 [SLAVE_BLSP_1] = &slv_blsp_1, 1574 [SLAVE_SDCC_1] = &slv_sdcc_1, 1575 [SLAVE_SDCC_2] = &slv_sdcc_2, 1576 [SLAVE_TLMM_CENTER] = &slv_tlmm_center, 1577 [SLAVE_BLSP_2] = &slv_blsp_2, 1578 [SLAVE_PDM] = &slv_pdm, 1579 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, 1580 [SLAVE_USB_HS] = &slv_usb_hs, 1581 [SLAVE_USB3_0] = &slv_usb3_0, 1582 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc, 1583 }; 1584 1585 static const struct regmap_config sdm660_cnoc_regmap_config = { 1586 .reg_bits = 32, 1587 .reg_stride = 4, 1588 .val_bits = 32, 1589 .max_register = 0x10000, 1590 .fast_io = true, 1591 }; 1592 1593 static const struct qcom_icc_desc sdm660_cnoc = { 1594 .type = QCOM_ICC_NOC, 1595 .nodes = sdm660_cnoc_nodes, 1596 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), 1597 .bus_clk_desc = &bus_2_clk, 1598 .regmap_cfg = &sdm660_cnoc_regmap_config, 1599 }; 1600 1601 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = { 1602 [MASTER_APSS_PROC] = &mas_apss_proc, 1603 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc, 1604 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc, 1605 }; 1606 1607 static const struct regmap_config sdm660_gnoc_regmap_config = { 1608 .reg_bits = 32, 1609 .reg_stride = 4, 1610 .val_bits = 32, 1611 .max_register = 0xe000, 1612 .fast_io = true, 1613 }; 1614 1615 static const struct qcom_icc_desc sdm660_gnoc = { 1616 .type = QCOM_ICC_NOC, 1617 .nodes = sdm660_gnoc_nodes, 1618 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes), 1619 .regmap_cfg = &sdm660_gnoc_regmap_config, 1620 }; 1621 1622 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = { 1623 [MASTER_CPP] = &mas_cpp, 1624 [MASTER_JPEG] = &mas_jpeg, 1625 [MASTER_MDP_P0] = &mas_mdp_p0, 1626 [MASTER_MDP_P1] = &mas_mdp_p1, 1627 [MASTER_VENUS] = &mas_venus, 1628 [MASTER_VFE] = &mas_vfe, 1629 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, 1630 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, 1631 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1632 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, 1633 [SLAVE_MISC_CFG] = &slv_misc_cfg, 1634 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1635 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1636 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, 1637 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, 1638 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, 1639 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1640 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg, 1641 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1642 [SLAVE_SMMU_CFG] = &slv_smmu_cfg, 1643 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc, 1644 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, 1645 }; 1646 1647 static const struct regmap_config sdm660_mnoc_regmap_config = { 1648 .reg_bits = 32, 1649 .reg_stride = 4, 1650 .val_bits = 32, 1651 .max_register = 0x10000, 1652 .fast_io = true, 1653 }; 1654 1655 static const struct qcom_icc_desc sdm660_mnoc = { 1656 .type = QCOM_ICC_NOC, 1657 .nodes = sdm660_mnoc_nodes, 1658 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), 1659 .bus_clk_desc = &mmaxi_0_clk, 1660 .intf_clocks = mm_intf_clocks, 1661 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), 1662 .regmap_cfg = &sdm660_mnoc_regmap_config, 1663 }; 1664 1665 static struct qcom_icc_node * const sdm660_snoc_nodes[] = { 1666 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1667 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1668 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1669 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1670 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, 1671 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc, 1672 [SLAVE_HMSS] = &slv_hmss, 1673 [SLAVE_LPASS] = &slv_lpass, 1674 [SLAVE_WLAN] = &slv_wlan, 1675 [SLAVE_CDSP] = &slv_cdsp, 1676 [SLAVE_IPA] = &slv_ipa, 1677 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1678 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1679 [SLAVE_IMEM] = &slv_imem, 1680 [SLAVE_PIMEM] = &slv_pimem, 1681 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1682 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, 1683 }; 1684 1685 static const struct regmap_config sdm660_snoc_regmap_config = { 1686 .reg_bits = 32, 1687 .reg_stride = 4, 1688 .val_bits = 32, 1689 .max_register = 0x20000, 1690 .fast_io = true, 1691 }; 1692 1693 static const struct qcom_icc_desc sdm660_snoc = { 1694 .type = QCOM_ICC_NOC, 1695 .nodes = sdm660_snoc_nodes, 1696 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), 1697 .bus_clk_desc = &bus_1_clk, 1698 .regmap_cfg = &sdm660_snoc_regmap_config, 1699 }; 1700 1701 static const struct of_device_id sdm660_noc_of_match[] = { 1702 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc }, 1703 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc }, 1704 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc }, 1705 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc }, 1706 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc }, 1707 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc }, 1708 { }, 1709 }; 1710 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match); 1711 1712 static struct platform_driver sdm660_noc_driver = { 1713 .probe = qnoc_probe, 1714 .remove = qnoc_remove, 1715 .driver = { 1716 .name = "qnoc-sdm660", 1717 .of_match_table = sdm660_noc_of_match, 1718 }, 1719 }; 1720 module_platform_driver(sdm660_noc_driver); 1721 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver"); 1722 MODULE_LICENSE("GPL v2"); 1723