xref: /linux/drivers/interconnect/qcom/sdm660.c (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
4  * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5  */
6 
7 #include <dt-bindings/interconnect/qcom,sdm660.h>
8 #include <linux/device.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/io.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 
17 #include "icc-rpm.h"
18 
19 enum {
20 	SDM660_MASTER_IPA = 1,
21 	SDM660_MASTER_CNOC_A2NOC,
22 	SDM660_MASTER_SDCC_1,
23 	SDM660_MASTER_SDCC_2,
24 	SDM660_MASTER_BLSP_1,
25 	SDM660_MASTER_BLSP_2,
26 	SDM660_MASTER_UFS,
27 	SDM660_MASTER_USB_HS,
28 	SDM660_MASTER_USB3,
29 	SDM660_MASTER_CRYPTO_C0,
30 	SDM660_MASTER_GNOC_BIMC,
31 	SDM660_MASTER_OXILI,
32 	SDM660_MASTER_MNOC_BIMC,
33 	SDM660_MASTER_SNOC_BIMC,
34 	SDM660_MASTER_PIMEM,
35 	SDM660_MASTER_SNOC_CNOC,
36 	SDM660_MASTER_QDSS_DAP,
37 	SDM660_MASTER_APPS_PROC,
38 	SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
39 	SDM660_MASTER_CNOC_MNOC_CFG,
40 	SDM660_MASTER_CPP,
41 	SDM660_MASTER_JPEG,
42 	SDM660_MASTER_MDP_P0,
43 	SDM660_MASTER_MDP_P1,
44 	SDM660_MASTER_VENUS,
45 	SDM660_MASTER_VFE,
46 	SDM660_MASTER_QDSS_ETR,
47 	SDM660_MASTER_QDSS_BAM,
48 	SDM660_MASTER_SNOC_CFG,
49 	SDM660_MASTER_BIMC_SNOC,
50 	SDM660_MASTER_A2NOC_SNOC,
51 	SDM660_MASTER_GNOC_SNOC,
52 
53 	SDM660_SLAVE_A2NOC_SNOC,
54 	SDM660_SLAVE_EBI,
55 	SDM660_SLAVE_HMSS_L3,
56 	SDM660_SLAVE_BIMC_SNOC,
57 	SDM660_SLAVE_CNOC_A2NOC,
58 	SDM660_SLAVE_MPM,
59 	SDM660_SLAVE_PMIC_ARB,
60 	SDM660_SLAVE_TLMM_NORTH,
61 	SDM660_SLAVE_TCSR,
62 	SDM660_SLAVE_PIMEM_CFG,
63 	SDM660_SLAVE_IMEM_CFG,
64 	SDM660_SLAVE_MESSAGE_RAM,
65 	SDM660_SLAVE_GLM,
66 	SDM660_SLAVE_BIMC_CFG,
67 	SDM660_SLAVE_PRNG,
68 	SDM660_SLAVE_SPDM,
69 	SDM660_SLAVE_QDSS_CFG,
70 	SDM660_SLAVE_CNOC_MNOC_CFG,
71 	SDM660_SLAVE_SNOC_CFG,
72 	SDM660_SLAVE_QM_CFG,
73 	SDM660_SLAVE_CLK_CTL,
74 	SDM660_SLAVE_MSS_CFG,
75 	SDM660_SLAVE_TLMM_SOUTH,
76 	SDM660_SLAVE_UFS_CFG,
77 	SDM660_SLAVE_A2NOC_CFG,
78 	SDM660_SLAVE_A2NOC_SMMU_CFG,
79 	SDM660_SLAVE_GPUSS_CFG,
80 	SDM660_SLAVE_AHB2PHY,
81 	SDM660_SLAVE_BLSP_1,
82 	SDM660_SLAVE_SDCC_1,
83 	SDM660_SLAVE_SDCC_2,
84 	SDM660_SLAVE_TLMM_CENTER,
85 	SDM660_SLAVE_BLSP_2,
86 	SDM660_SLAVE_PDM,
87 	SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
88 	SDM660_SLAVE_USB_HS,
89 	SDM660_SLAVE_USB3_0,
90 	SDM660_SLAVE_SRVC_CNOC,
91 	SDM660_SLAVE_GNOC_BIMC,
92 	SDM660_SLAVE_GNOC_SNOC,
93 	SDM660_SLAVE_CAMERA_CFG,
94 	SDM660_SLAVE_CAMERA_THROTTLE_CFG,
95 	SDM660_SLAVE_MISC_CFG,
96 	SDM660_SLAVE_VENUS_THROTTLE_CFG,
97 	SDM660_SLAVE_VENUS_CFG,
98 	SDM660_SLAVE_MMSS_CLK_XPU_CFG,
99 	SDM660_SLAVE_MMSS_CLK_CFG,
100 	SDM660_SLAVE_MNOC_MPU_CFG,
101 	SDM660_SLAVE_DISPLAY_CFG,
102 	SDM660_SLAVE_CSI_PHY_CFG,
103 	SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
104 	SDM660_SLAVE_SMMU_CFG,
105 	SDM660_SLAVE_MNOC_BIMC,
106 	SDM660_SLAVE_SRVC_MNOC,
107 	SDM660_SLAVE_HMSS,
108 	SDM660_SLAVE_LPASS,
109 	SDM660_SLAVE_WLAN,
110 	SDM660_SLAVE_CDSP,
111 	SDM660_SLAVE_IPA,
112 	SDM660_SLAVE_SNOC_BIMC,
113 	SDM660_SLAVE_SNOC_CNOC,
114 	SDM660_SLAVE_IMEM,
115 	SDM660_SLAVE_PIMEM,
116 	SDM660_SLAVE_QDSS_STM,
117 	SDM660_SLAVE_SRVC_SNOC,
118 
119 	SDM660_A2NOC,
120 	SDM660_BIMC,
121 	SDM660_CNOC,
122 	SDM660_GNOC,
123 	SDM660_MNOC,
124 	SDM660_SNOC,
125 };
126 
127 static const char * const mm_intf_clocks[] = {
128 	"iface",
129 };
130 
131 static const char * const a2noc_intf_clocks[] = {
132 	"ipa",
133 	"ufs_axi",
134 	"aggre2_ufs_axi",
135 	"aggre2_usb3_axi",
136 	"cfg_noc_usb2_axi",
137 };
138 
139 static const u16 mas_ipa_links[] = {
140 	SDM660_SLAVE_A2NOC_SNOC
141 };
142 
143 static struct qcom_icc_node mas_ipa = {
144 	.name = "mas_ipa",
145 	.id = SDM660_MASTER_IPA,
146 	.buswidth = 8,
147 	.mas_rpm_id = 59,
148 	.slv_rpm_id = -1,
149 	.qos.ap_owned = true,
150 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
151 	.qos.areq_prio = 1,
152 	.qos.prio_level = 1,
153 	.qos.qos_port = 3,
154 	.num_links = ARRAY_SIZE(mas_ipa_links),
155 	.links = mas_ipa_links,
156 };
157 
158 static const u16 mas_cnoc_a2noc_links[] = {
159 	SDM660_SLAVE_A2NOC_SNOC
160 };
161 
162 static struct qcom_icc_node mas_cnoc_a2noc = {
163 	.name = "mas_cnoc_a2noc",
164 	.id = SDM660_MASTER_CNOC_A2NOC,
165 	.buswidth = 8,
166 	.mas_rpm_id = 146,
167 	.slv_rpm_id = -1,
168 	.qos.ap_owned = true,
169 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
170 	.num_links = ARRAY_SIZE(mas_cnoc_a2noc_links),
171 	.links = mas_cnoc_a2noc_links,
172 };
173 
174 static const u16 mas_sdcc_1_links[] = {
175 	SDM660_SLAVE_A2NOC_SNOC
176 };
177 
178 static struct qcom_icc_node mas_sdcc_1 = {
179 	.name = "mas_sdcc_1",
180 	.id = SDM660_MASTER_SDCC_1,
181 	.buswidth = 8,
182 	.mas_rpm_id = 33,
183 	.slv_rpm_id = -1,
184 	.num_links = ARRAY_SIZE(mas_sdcc_1_links),
185 	.links = mas_sdcc_1_links,
186 };
187 
188 static const u16 mas_sdcc_2_links[] = {
189 	SDM660_SLAVE_A2NOC_SNOC
190 };
191 
192 static struct qcom_icc_node mas_sdcc_2 = {
193 	.name = "mas_sdcc_2",
194 	.id = SDM660_MASTER_SDCC_2,
195 	.buswidth = 8,
196 	.mas_rpm_id = 35,
197 	.slv_rpm_id = -1,
198 	.num_links = ARRAY_SIZE(mas_sdcc_2_links),
199 	.links = mas_sdcc_2_links,
200 };
201 
202 static const u16 mas_blsp_1_links[] = {
203 	SDM660_SLAVE_A2NOC_SNOC
204 };
205 
206 static struct qcom_icc_node mas_blsp_1 = {
207 	.name = "mas_blsp_1",
208 	.id = SDM660_MASTER_BLSP_1,
209 	.buswidth = 4,
210 	.mas_rpm_id = 41,
211 	.slv_rpm_id = -1,
212 	.num_links = ARRAY_SIZE(mas_blsp_1_links),
213 	.links = mas_blsp_1_links,
214 };
215 
216 static const u16 mas_blsp_2_links[] = {
217 	SDM660_SLAVE_A2NOC_SNOC
218 };
219 
220 static struct qcom_icc_node mas_blsp_2 = {
221 	.name = "mas_blsp_2",
222 	.id = SDM660_MASTER_BLSP_2,
223 	.buswidth = 4,
224 	.mas_rpm_id = 39,
225 	.slv_rpm_id = -1,
226 	.num_links = ARRAY_SIZE(mas_blsp_2_links),
227 	.links = mas_blsp_2_links,
228 };
229 
230 static const u16 mas_ufs_links[] = {
231 	SDM660_SLAVE_A2NOC_SNOC
232 };
233 
234 static struct qcom_icc_node mas_ufs = {
235 	.name = "mas_ufs",
236 	.id = SDM660_MASTER_UFS,
237 	.buswidth = 8,
238 	.mas_rpm_id = 68,
239 	.slv_rpm_id = -1,
240 	.qos.ap_owned = true,
241 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
242 	.qos.areq_prio = 1,
243 	.qos.prio_level = 1,
244 	.qos.qos_port = 4,
245 	.num_links = ARRAY_SIZE(mas_ufs_links),
246 	.links = mas_ufs_links,
247 };
248 
249 static const u16 mas_usb_hs_links[] = {
250 	SDM660_SLAVE_A2NOC_SNOC
251 };
252 
253 static struct qcom_icc_node mas_usb_hs = {
254 	.name = "mas_usb_hs",
255 	.id = SDM660_MASTER_USB_HS,
256 	.buswidth = 8,
257 	.mas_rpm_id = 42,
258 	.slv_rpm_id = -1,
259 	.qos.ap_owned = true,
260 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
261 	.qos.areq_prio = 1,
262 	.qos.prio_level = 1,
263 	.qos.qos_port = 1,
264 	.num_links = ARRAY_SIZE(mas_usb_hs_links),
265 	.links = mas_usb_hs_links,
266 };
267 
268 static const u16 mas_usb3_links[] = {
269 	SDM660_SLAVE_A2NOC_SNOC
270 };
271 
272 static struct qcom_icc_node mas_usb3 = {
273 	.name = "mas_usb3",
274 	.id = SDM660_MASTER_USB3,
275 	.buswidth = 8,
276 	.mas_rpm_id = 32,
277 	.slv_rpm_id = -1,
278 	.qos.ap_owned = true,
279 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
280 	.qos.areq_prio = 1,
281 	.qos.prio_level = 1,
282 	.qos.qos_port = 2,
283 	.num_links = ARRAY_SIZE(mas_usb3_links),
284 	.links = mas_usb3_links,
285 };
286 
287 static const u16 mas_crypto_links[] = {
288 	SDM660_SLAVE_A2NOC_SNOC
289 };
290 
291 static struct qcom_icc_node mas_crypto = {
292 	.name = "mas_crypto",
293 	.id = SDM660_MASTER_CRYPTO_C0,
294 	.buswidth = 8,
295 	.mas_rpm_id = 23,
296 	.slv_rpm_id = -1,
297 	.qos.ap_owned = true,
298 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
299 	.qos.areq_prio = 1,
300 	.qos.prio_level = 1,
301 	.qos.qos_port = 11,
302 	.num_links = ARRAY_SIZE(mas_crypto_links),
303 	.links = mas_crypto_links,
304 };
305 
306 static const u16 mas_gnoc_bimc_links[] = {
307 	SDM660_SLAVE_EBI
308 };
309 
310 static struct qcom_icc_node mas_gnoc_bimc = {
311 	.name = "mas_gnoc_bimc",
312 	.id = SDM660_MASTER_GNOC_BIMC,
313 	.buswidth = 4,
314 	.mas_rpm_id = 144,
315 	.slv_rpm_id = -1,
316 	.qos.ap_owned = true,
317 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
318 	.qos.areq_prio = 0,
319 	.qos.prio_level = 0,
320 	.qos.qos_port = 0,
321 	.num_links = ARRAY_SIZE(mas_gnoc_bimc_links),
322 	.links = mas_gnoc_bimc_links,
323 };
324 
325 static const u16 mas_oxili_links[] = {
326 	SDM660_SLAVE_HMSS_L3,
327 	SDM660_SLAVE_EBI,
328 	SDM660_SLAVE_BIMC_SNOC
329 };
330 
331 static struct qcom_icc_node mas_oxili = {
332 	.name = "mas_oxili",
333 	.id = SDM660_MASTER_OXILI,
334 	.buswidth = 4,
335 	.mas_rpm_id = 6,
336 	.slv_rpm_id = -1,
337 	.qos.ap_owned = true,
338 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
339 	.qos.areq_prio = 0,
340 	.qos.prio_level = 0,
341 	.qos.qos_port = 1,
342 	.num_links = ARRAY_SIZE(mas_oxili_links),
343 	.links = mas_oxili_links,
344 };
345 
346 static const u16 mas_mnoc_bimc_links[] = {
347 	SDM660_SLAVE_HMSS_L3,
348 	SDM660_SLAVE_EBI,
349 	SDM660_SLAVE_BIMC_SNOC
350 };
351 
352 static struct qcom_icc_node mas_mnoc_bimc = {
353 	.name = "mas_mnoc_bimc",
354 	.id = SDM660_MASTER_MNOC_BIMC,
355 	.buswidth = 4,
356 	.mas_rpm_id = 2,
357 	.slv_rpm_id = -1,
358 	.qos.ap_owned = true,
359 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
360 	.qos.areq_prio = 0,
361 	.qos.prio_level = 0,
362 	.qos.qos_port = 2,
363 	.num_links = ARRAY_SIZE(mas_mnoc_bimc_links),
364 	.links = mas_mnoc_bimc_links,
365 };
366 
367 static const u16 mas_snoc_bimc_links[] = {
368 	SDM660_SLAVE_HMSS_L3,
369 	SDM660_SLAVE_EBI
370 };
371 
372 static struct qcom_icc_node mas_snoc_bimc = {
373 	.name = "mas_snoc_bimc",
374 	.id = SDM660_MASTER_SNOC_BIMC,
375 	.buswidth = 4,
376 	.mas_rpm_id = 3,
377 	.slv_rpm_id = -1,
378 	.num_links = ARRAY_SIZE(mas_snoc_bimc_links),
379 	.links = mas_snoc_bimc_links,
380 };
381 
382 static const u16 mas_pimem_links[] = {
383 	SDM660_SLAVE_HMSS_L3,
384 	SDM660_SLAVE_EBI
385 };
386 
387 static struct qcom_icc_node mas_pimem = {
388 	.name = "mas_pimem",
389 	.id = SDM660_MASTER_PIMEM,
390 	.buswidth = 4,
391 	.mas_rpm_id = 113,
392 	.slv_rpm_id = -1,
393 	.qos.ap_owned = true,
394 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
395 	.qos.areq_prio = 1,
396 	.qos.prio_level = 1,
397 	.qos.qos_port = 4,
398 	.num_links = ARRAY_SIZE(mas_pimem_links),
399 	.links = mas_pimem_links,
400 };
401 
402 static const u16 mas_snoc_cnoc_links[] = {
403 	SDM660_SLAVE_CLK_CTL,
404 	SDM660_SLAVE_QDSS_CFG,
405 	SDM660_SLAVE_QM_CFG,
406 	SDM660_SLAVE_SRVC_CNOC,
407 	SDM660_SLAVE_UFS_CFG,
408 	SDM660_SLAVE_TCSR,
409 	SDM660_SLAVE_A2NOC_SMMU_CFG,
410 	SDM660_SLAVE_SNOC_CFG,
411 	SDM660_SLAVE_TLMM_SOUTH,
412 	SDM660_SLAVE_MPM,
413 	SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
414 	SDM660_SLAVE_SDCC_2,
415 	SDM660_SLAVE_SDCC_1,
416 	SDM660_SLAVE_SPDM,
417 	SDM660_SLAVE_PMIC_ARB,
418 	SDM660_SLAVE_PRNG,
419 	SDM660_SLAVE_MSS_CFG,
420 	SDM660_SLAVE_GPUSS_CFG,
421 	SDM660_SLAVE_IMEM_CFG,
422 	SDM660_SLAVE_USB3_0,
423 	SDM660_SLAVE_A2NOC_CFG,
424 	SDM660_SLAVE_TLMM_NORTH,
425 	SDM660_SLAVE_USB_HS,
426 	SDM660_SLAVE_PDM,
427 	SDM660_SLAVE_TLMM_CENTER,
428 	SDM660_SLAVE_AHB2PHY,
429 	SDM660_SLAVE_BLSP_2,
430 	SDM660_SLAVE_BLSP_1,
431 	SDM660_SLAVE_PIMEM_CFG,
432 	SDM660_SLAVE_GLM,
433 	SDM660_SLAVE_MESSAGE_RAM,
434 	SDM660_SLAVE_BIMC_CFG,
435 	SDM660_SLAVE_CNOC_MNOC_CFG
436 };
437 
438 static struct qcom_icc_node mas_snoc_cnoc = {
439 	.name = "mas_snoc_cnoc",
440 	.id = SDM660_MASTER_SNOC_CNOC,
441 	.buswidth = 8,
442 	.mas_rpm_id = 52,
443 	.slv_rpm_id = -1,
444 	.qos.ap_owned = true,
445 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
446 	.num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
447 	.links = mas_snoc_cnoc_links,
448 };
449 
450 static const u16 mas_qdss_dap_links[] = {
451 	SDM660_SLAVE_CLK_CTL,
452 	SDM660_SLAVE_QDSS_CFG,
453 	SDM660_SLAVE_QM_CFG,
454 	SDM660_SLAVE_SRVC_CNOC,
455 	SDM660_SLAVE_UFS_CFG,
456 	SDM660_SLAVE_TCSR,
457 	SDM660_SLAVE_A2NOC_SMMU_CFG,
458 	SDM660_SLAVE_SNOC_CFG,
459 	SDM660_SLAVE_TLMM_SOUTH,
460 	SDM660_SLAVE_MPM,
461 	SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
462 	SDM660_SLAVE_SDCC_2,
463 	SDM660_SLAVE_SDCC_1,
464 	SDM660_SLAVE_SPDM,
465 	SDM660_SLAVE_PMIC_ARB,
466 	SDM660_SLAVE_PRNG,
467 	SDM660_SLAVE_MSS_CFG,
468 	SDM660_SLAVE_GPUSS_CFG,
469 	SDM660_SLAVE_IMEM_CFG,
470 	SDM660_SLAVE_USB3_0,
471 	SDM660_SLAVE_A2NOC_CFG,
472 	SDM660_SLAVE_TLMM_NORTH,
473 	SDM660_SLAVE_USB_HS,
474 	SDM660_SLAVE_PDM,
475 	SDM660_SLAVE_TLMM_CENTER,
476 	SDM660_SLAVE_AHB2PHY,
477 	SDM660_SLAVE_BLSP_2,
478 	SDM660_SLAVE_BLSP_1,
479 	SDM660_SLAVE_PIMEM_CFG,
480 	SDM660_SLAVE_GLM,
481 	SDM660_SLAVE_MESSAGE_RAM,
482 	SDM660_SLAVE_CNOC_A2NOC,
483 	SDM660_SLAVE_BIMC_CFG,
484 	SDM660_SLAVE_CNOC_MNOC_CFG
485 };
486 
487 static struct qcom_icc_node mas_qdss_dap = {
488 	.name = "mas_qdss_dap",
489 	.id = SDM660_MASTER_QDSS_DAP,
490 	.buswidth = 8,
491 	.mas_rpm_id = 49,
492 	.slv_rpm_id = -1,
493 	.qos.ap_owned = true,
494 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
495 	.num_links = ARRAY_SIZE(mas_qdss_dap_links),
496 	.links = mas_qdss_dap_links,
497 };
498 
499 static const u16 mas_apss_proc_links[] = {
500 	SDM660_SLAVE_GNOC_SNOC,
501 	SDM660_SLAVE_GNOC_BIMC
502 };
503 
504 static struct qcom_icc_node mas_apss_proc = {
505 	.name = "mas_apss_proc",
506 	.id = SDM660_MASTER_APPS_PROC,
507 	.buswidth = 16,
508 	.mas_rpm_id = 0,
509 	.slv_rpm_id = -1,
510 	.qos.ap_owned = true,
511 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
512 	.num_links = ARRAY_SIZE(mas_apss_proc_links),
513 	.links = mas_apss_proc_links,
514 };
515 
516 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
517 	SDM660_SLAVE_VENUS_THROTTLE_CFG,
518 	SDM660_SLAVE_VENUS_CFG,
519 	SDM660_SLAVE_CAMERA_THROTTLE_CFG,
520 	SDM660_SLAVE_SMMU_CFG,
521 	SDM660_SLAVE_CAMERA_CFG,
522 	SDM660_SLAVE_CSI_PHY_CFG,
523 	SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
524 	SDM660_SLAVE_DISPLAY_CFG,
525 	SDM660_SLAVE_MMSS_CLK_CFG,
526 	SDM660_SLAVE_MNOC_MPU_CFG,
527 	SDM660_SLAVE_MISC_CFG,
528 	SDM660_SLAVE_MMSS_CLK_XPU_CFG
529 };
530 
531 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
532 	.name = "mas_cnoc_mnoc_mmss_cfg",
533 	.id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
534 	.buswidth = 8,
535 	.mas_rpm_id = 4,
536 	.slv_rpm_id = -1,
537 	.qos.ap_owned = true,
538 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
539 	.num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
540 	.links = mas_cnoc_mnoc_mmss_cfg_links,
541 };
542 
543 static const u16 mas_cnoc_mnoc_cfg_links[] = {
544 	SDM660_SLAVE_SRVC_MNOC
545 };
546 
547 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
548 	.name = "mas_cnoc_mnoc_cfg",
549 	.id = SDM660_MASTER_CNOC_MNOC_CFG,
550 	.buswidth = 4,
551 	.mas_rpm_id = 5,
552 	.slv_rpm_id = -1,
553 	.qos.ap_owned = true,
554 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
555 	.num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
556 	.links = mas_cnoc_mnoc_cfg_links,
557 };
558 
559 static const u16 mas_cpp_links[] = {
560 	SDM660_SLAVE_MNOC_BIMC
561 };
562 
563 static struct qcom_icc_node mas_cpp = {
564 	.name = "mas_cpp",
565 	.id = SDM660_MASTER_CPP,
566 	.buswidth = 16,
567 	.mas_rpm_id = 115,
568 	.slv_rpm_id = -1,
569 	.qos.ap_owned = true,
570 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
571 	.qos.areq_prio = 0,
572 	.qos.prio_level = 0,
573 	.qos.qos_port = 4,
574 	.num_links = ARRAY_SIZE(mas_cpp_links),
575 	.links = mas_cpp_links,
576 };
577 
578 static const u16 mas_jpeg_links[] = {
579 	SDM660_SLAVE_MNOC_BIMC
580 };
581 
582 static struct qcom_icc_node mas_jpeg = {
583 	.name = "mas_jpeg",
584 	.id = SDM660_MASTER_JPEG,
585 	.buswidth = 16,
586 	.mas_rpm_id = 7,
587 	.slv_rpm_id = -1,
588 	.qos.ap_owned = true,
589 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
590 	.qos.areq_prio = 0,
591 	.qos.prio_level = 0,
592 	.qos.qos_port = 6,
593 	.num_links = ARRAY_SIZE(mas_jpeg_links),
594 	.links = mas_jpeg_links,
595 };
596 
597 static const u16 mas_mdp_p0_links[] = {
598 	SDM660_SLAVE_MNOC_BIMC
599 };
600 
601 static struct qcom_icc_node mas_mdp_p0 = {
602 	.name = "mas_mdp_p0",
603 	.id = SDM660_MASTER_MDP_P0,
604 	.buswidth = 16,
605 	.ib_coeff = 50,
606 	.mas_rpm_id = 8,
607 	.slv_rpm_id = -1,
608 	.qos.ap_owned = true,
609 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
610 	.qos.areq_prio = 0,
611 	.qos.prio_level = 0,
612 	.qos.qos_port = 0,
613 	.num_links = ARRAY_SIZE(mas_mdp_p0_links),
614 	.links = mas_mdp_p0_links,
615 };
616 
617 static const u16 mas_mdp_p1_links[] = {
618 	SDM660_SLAVE_MNOC_BIMC
619 };
620 
621 static struct qcom_icc_node mas_mdp_p1 = {
622 	.name = "mas_mdp_p1",
623 	.id = SDM660_MASTER_MDP_P1,
624 	.buswidth = 16,
625 	.ib_coeff = 50,
626 	.mas_rpm_id = 61,
627 	.slv_rpm_id = -1,
628 	.qos.ap_owned = true,
629 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
630 	.qos.areq_prio = 0,
631 	.qos.prio_level = 0,
632 	.qos.qos_port = 1,
633 	.num_links = ARRAY_SIZE(mas_mdp_p1_links),
634 	.links = mas_mdp_p1_links,
635 };
636 
637 static const u16 mas_venus_links[] = {
638 	SDM660_SLAVE_MNOC_BIMC
639 };
640 
641 static struct qcom_icc_node mas_venus = {
642 	.name = "mas_venus",
643 	.id = SDM660_MASTER_VENUS,
644 	.buswidth = 16,
645 	.mas_rpm_id = 9,
646 	.slv_rpm_id = -1,
647 	.qos.ap_owned = true,
648 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
649 	.qos.areq_prio = 0,
650 	.qos.prio_level = 0,
651 	.qos.qos_port = 1,
652 	.num_links = ARRAY_SIZE(mas_venus_links),
653 	.links = mas_venus_links,
654 };
655 
656 static const u16 mas_vfe_links[] = {
657 	SDM660_SLAVE_MNOC_BIMC
658 };
659 
660 static struct qcom_icc_node mas_vfe = {
661 	.name = "mas_vfe",
662 	.id = SDM660_MASTER_VFE,
663 	.buswidth = 16,
664 	.mas_rpm_id = 11,
665 	.slv_rpm_id = -1,
666 	.qos.ap_owned = true,
667 	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
668 	.qos.areq_prio = 0,
669 	.qos.prio_level = 0,
670 	.qos.qos_port = 5,
671 	.num_links = ARRAY_SIZE(mas_vfe_links),
672 	.links = mas_vfe_links,
673 };
674 
675 static const u16 mas_qdss_etr_links[] = {
676 	SDM660_SLAVE_PIMEM,
677 	SDM660_SLAVE_IMEM,
678 	SDM660_SLAVE_SNOC_CNOC,
679 	SDM660_SLAVE_SNOC_BIMC
680 };
681 
682 static struct qcom_icc_node mas_qdss_etr = {
683 	.name = "mas_qdss_etr",
684 	.id = SDM660_MASTER_QDSS_ETR,
685 	.buswidth = 8,
686 	.mas_rpm_id = 31,
687 	.slv_rpm_id = -1,
688 	.qos.ap_owned = true,
689 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
690 	.qos.areq_prio = 1,
691 	.qos.prio_level = 1,
692 	.qos.qos_port = 1,
693 	.num_links = ARRAY_SIZE(mas_qdss_etr_links),
694 	.links = mas_qdss_etr_links,
695 };
696 
697 static const u16 mas_qdss_bam_links[] = {
698 	SDM660_SLAVE_PIMEM,
699 	SDM660_SLAVE_IMEM,
700 	SDM660_SLAVE_SNOC_CNOC,
701 	SDM660_SLAVE_SNOC_BIMC
702 };
703 
704 static struct qcom_icc_node mas_qdss_bam = {
705 	.name = "mas_qdss_bam",
706 	.id = SDM660_MASTER_QDSS_BAM,
707 	.buswidth = 4,
708 	.mas_rpm_id = 19,
709 	.slv_rpm_id = -1,
710 	.qos.ap_owned = true,
711 	.qos.qos_mode = NOC_QOS_MODE_FIXED,
712 	.qos.areq_prio = 1,
713 	.qos.prio_level = 1,
714 	.qos.qos_port = 0,
715 	.num_links = ARRAY_SIZE(mas_qdss_bam_links),
716 	.links = mas_qdss_bam_links,
717 };
718 
719 static const u16 mas_snoc_cfg_links[] = {
720 	SDM660_SLAVE_SRVC_SNOC
721 };
722 
723 static struct qcom_icc_node mas_snoc_cfg = {
724 	.name = "mas_snoc_cfg",
725 	.id = SDM660_MASTER_SNOC_CFG,
726 	.buswidth = 4,
727 	.mas_rpm_id = 20,
728 	.slv_rpm_id = -1,
729 	.num_links = ARRAY_SIZE(mas_snoc_cfg_links),
730 	.links = mas_snoc_cfg_links,
731 };
732 
733 static const u16 mas_bimc_snoc_links[] = {
734 	SDM660_SLAVE_PIMEM,
735 	SDM660_SLAVE_IPA,
736 	SDM660_SLAVE_QDSS_STM,
737 	SDM660_SLAVE_LPASS,
738 	SDM660_SLAVE_HMSS,
739 	SDM660_SLAVE_CDSP,
740 	SDM660_SLAVE_SNOC_CNOC,
741 	SDM660_SLAVE_WLAN,
742 	SDM660_SLAVE_IMEM
743 };
744 
745 static struct qcom_icc_node mas_bimc_snoc = {
746 	.name = "mas_bimc_snoc",
747 	.id = SDM660_MASTER_BIMC_SNOC,
748 	.buswidth = 8,
749 	.mas_rpm_id = 21,
750 	.slv_rpm_id = -1,
751 	.num_links = ARRAY_SIZE(mas_bimc_snoc_links),
752 	.links = mas_bimc_snoc_links,
753 };
754 
755 static const u16 mas_gnoc_snoc_links[] = {
756 	SDM660_SLAVE_PIMEM,
757 	SDM660_SLAVE_IPA,
758 	SDM660_SLAVE_QDSS_STM,
759 	SDM660_SLAVE_LPASS,
760 	SDM660_SLAVE_HMSS,
761 	SDM660_SLAVE_CDSP,
762 	SDM660_SLAVE_SNOC_CNOC,
763 	SDM660_SLAVE_WLAN,
764 	SDM660_SLAVE_IMEM
765 };
766 
767 static struct qcom_icc_node mas_gnoc_snoc = {
768 	.name = "mas_gnoc_snoc",
769 	.id = SDM660_MASTER_GNOC_SNOC,
770 	.buswidth = 8,
771 	.mas_rpm_id = 150,
772 	.slv_rpm_id = -1,
773 	.num_links = ARRAY_SIZE(mas_gnoc_snoc_links),
774 	.links = mas_gnoc_snoc_links,
775 };
776 
777 static const u16 mas_a2noc_snoc_links[] = {
778 	SDM660_SLAVE_PIMEM,
779 	SDM660_SLAVE_IPA,
780 	SDM660_SLAVE_QDSS_STM,
781 	SDM660_SLAVE_LPASS,
782 	SDM660_SLAVE_HMSS,
783 	SDM660_SLAVE_SNOC_BIMC,
784 	SDM660_SLAVE_CDSP,
785 	SDM660_SLAVE_SNOC_CNOC,
786 	SDM660_SLAVE_WLAN,
787 	SDM660_SLAVE_IMEM
788 };
789 
790 static struct qcom_icc_node mas_a2noc_snoc = {
791 	.name = "mas_a2noc_snoc",
792 	.id = SDM660_MASTER_A2NOC_SNOC,
793 	.buswidth = 16,
794 	.mas_rpm_id = 112,
795 	.slv_rpm_id = -1,
796 	.num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
797 	.links = mas_a2noc_snoc_links,
798 };
799 
800 static const u16 slv_a2noc_snoc_links[] = {
801 	SDM660_MASTER_A2NOC_SNOC
802 };
803 
804 static struct qcom_icc_node slv_a2noc_snoc = {
805 	.name = "slv_a2noc_snoc",
806 	.id = SDM660_SLAVE_A2NOC_SNOC,
807 	.buswidth = 16,
808 	.mas_rpm_id = -1,
809 	.slv_rpm_id = 143,
810 	.num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
811 	.links = slv_a2noc_snoc_links,
812 };
813 
814 static struct qcom_icc_node slv_ebi = {
815 	.name = "slv_ebi",
816 	.id = SDM660_SLAVE_EBI,
817 	.buswidth = 4,
818 	.mas_rpm_id = -1,
819 	.slv_rpm_id = 0,
820 };
821 
822 static struct qcom_icc_node slv_hmss_l3 = {
823 	.name = "slv_hmss_l3",
824 	.id = SDM660_SLAVE_HMSS_L3,
825 	.buswidth = 4,
826 	.mas_rpm_id = -1,
827 	.slv_rpm_id = 160,
828 };
829 
830 static const u16 slv_bimc_snoc_links[] = {
831 	SDM660_MASTER_BIMC_SNOC
832 };
833 
834 static struct qcom_icc_node slv_bimc_snoc = {
835 	.name = "slv_bimc_snoc",
836 	.id = SDM660_SLAVE_BIMC_SNOC,
837 	.buswidth = 4,
838 	.mas_rpm_id = -1,
839 	.slv_rpm_id = 2,
840 	.num_links = ARRAY_SIZE(slv_bimc_snoc_links),
841 	.links = slv_bimc_snoc_links,
842 };
843 
844 static const u16 slv_cnoc_a2noc_links[] = {
845 	SDM660_MASTER_CNOC_A2NOC
846 };
847 
848 static struct qcom_icc_node slv_cnoc_a2noc = {
849 	.name = "slv_cnoc_a2noc",
850 	.id = SDM660_SLAVE_CNOC_A2NOC,
851 	.buswidth = 8,
852 	.mas_rpm_id = -1,
853 	.slv_rpm_id = 208,
854 	.qos.ap_owned = true,
855 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
856 	.num_links = ARRAY_SIZE(slv_cnoc_a2noc_links),
857 	.links = slv_cnoc_a2noc_links,
858 };
859 
860 static struct qcom_icc_node slv_mpm = {
861 	.name = "slv_mpm",
862 	.id = SDM660_SLAVE_MPM,
863 	.buswidth = 4,
864 	.mas_rpm_id = -1,
865 	.slv_rpm_id = 62,
866 	.qos.ap_owned = true,
867 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
868 };
869 
870 static struct qcom_icc_node slv_pmic_arb = {
871 	.name = "slv_pmic_arb",
872 	.id = SDM660_SLAVE_PMIC_ARB,
873 	.buswidth = 4,
874 	.mas_rpm_id = -1,
875 	.slv_rpm_id = 59,
876 	.qos.ap_owned = true,
877 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
878 };
879 
880 static struct qcom_icc_node slv_tlmm_north = {
881 	.name = "slv_tlmm_north",
882 	.id = SDM660_SLAVE_TLMM_NORTH,
883 	.buswidth = 8,
884 	.mas_rpm_id = -1,
885 	.slv_rpm_id = 214,
886 	.qos.ap_owned = true,
887 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
888 };
889 
890 static struct qcom_icc_node slv_tcsr = {
891 	.name = "slv_tcsr",
892 	.id = SDM660_SLAVE_TCSR,
893 	.buswidth = 4,
894 	.mas_rpm_id = -1,
895 	.slv_rpm_id = 50,
896 	.qos.ap_owned = true,
897 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
898 };
899 
900 static struct qcom_icc_node slv_pimem_cfg = {
901 	.name = "slv_pimem_cfg",
902 	.id = SDM660_SLAVE_PIMEM_CFG,
903 	.buswidth = 4,
904 	.mas_rpm_id = -1,
905 	.slv_rpm_id = 167,
906 	.qos.ap_owned = true,
907 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
908 };
909 
910 static struct qcom_icc_node slv_imem_cfg = {
911 	.name = "slv_imem_cfg",
912 	.id = SDM660_SLAVE_IMEM_CFG,
913 	.buswidth = 4,
914 	.mas_rpm_id = -1,
915 	.slv_rpm_id = 54,
916 	.qos.ap_owned = true,
917 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
918 };
919 
920 static struct qcom_icc_node slv_message_ram = {
921 	.name = "slv_message_ram",
922 	.id = SDM660_SLAVE_MESSAGE_RAM,
923 	.buswidth = 4,
924 	.mas_rpm_id = -1,
925 	.slv_rpm_id = 55,
926 	.qos.ap_owned = true,
927 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
928 };
929 
930 static struct qcom_icc_node slv_glm = {
931 	.name = "slv_glm",
932 	.id = SDM660_SLAVE_GLM,
933 	.buswidth = 4,
934 	.mas_rpm_id = -1,
935 	.slv_rpm_id = 209,
936 	.qos.ap_owned = true,
937 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
938 };
939 
940 static struct qcom_icc_node slv_bimc_cfg = {
941 	.name = "slv_bimc_cfg",
942 	.id = SDM660_SLAVE_BIMC_CFG,
943 	.buswidth = 4,
944 	.mas_rpm_id = -1,
945 	.slv_rpm_id = 56,
946 	.qos.ap_owned = true,
947 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
948 };
949 
950 static struct qcom_icc_node slv_prng = {
951 	.name = "slv_prng",
952 	.id = SDM660_SLAVE_PRNG,
953 	.buswidth = 4,
954 	.mas_rpm_id = -1,
955 	.slv_rpm_id = 44,
956 	.qos.ap_owned = true,
957 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
958 };
959 
960 static struct qcom_icc_node slv_spdm = {
961 	.name = "slv_spdm",
962 	.id = SDM660_SLAVE_SPDM,
963 	.buswidth = 4,
964 	.mas_rpm_id = -1,
965 	.slv_rpm_id = 60,
966 	.qos.ap_owned = true,
967 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
968 };
969 
970 static struct qcom_icc_node slv_qdss_cfg = {
971 	.name = "slv_qdss_cfg",
972 	.id = SDM660_SLAVE_QDSS_CFG,
973 	.buswidth = 4,
974 	.mas_rpm_id = -1,
975 	.slv_rpm_id = 63,
976 	.qos.ap_owned = true,
977 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
978 };
979 
980 static const u16 slv_cnoc_mnoc_cfg_links[] = {
981 	SDM660_MASTER_CNOC_MNOC_CFG
982 };
983 
984 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
985 	.name = "slv_cnoc_mnoc_cfg",
986 	.id = SDM660_SLAVE_CNOC_MNOC_CFG,
987 	.buswidth = 4,
988 	.mas_rpm_id = -1,
989 	.slv_rpm_id = 66,
990 	.qos.ap_owned = true,
991 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
992 	.num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
993 	.links = slv_cnoc_mnoc_cfg_links,
994 };
995 
996 static struct qcom_icc_node slv_snoc_cfg = {
997 	.name = "slv_snoc_cfg",
998 	.id = SDM660_SLAVE_SNOC_CFG,
999 	.buswidth = 4,
1000 	.mas_rpm_id = -1,
1001 	.slv_rpm_id = 70,
1002 	.qos.ap_owned = true,
1003 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1004 };
1005 
1006 static struct qcom_icc_node slv_qm_cfg = {
1007 	.name = "slv_qm_cfg",
1008 	.id = SDM660_SLAVE_QM_CFG,
1009 	.buswidth = 4,
1010 	.mas_rpm_id = -1,
1011 	.slv_rpm_id = 212,
1012 	.qos.ap_owned = true,
1013 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1014 };
1015 
1016 static struct qcom_icc_node slv_clk_ctl = {
1017 	.name = "slv_clk_ctl",
1018 	.id = SDM660_SLAVE_CLK_CTL,
1019 	.buswidth = 4,
1020 	.mas_rpm_id = -1,
1021 	.slv_rpm_id = 47,
1022 	.qos.ap_owned = true,
1023 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1024 };
1025 
1026 static struct qcom_icc_node slv_mss_cfg = {
1027 	.name = "slv_mss_cfg",
1028 	.id = SDM660_SLAVE_MSS_CFG,
1029 	.buswidth = 4,
1030 	.mas_rpm_id = -1,
1031 	.slv_rpm_id = 48,
1032 	.qos.ap_owned = true,
1033 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1034 };
1035 
1036 static struct qcom_icc_node slv_tlmm_south = {
1037 	.name = "slv_tlmm_south",
1038 	.id = SDM660_SLAVE_TLMM_SOUTH,
1039 	.buswidth = 4,
1040 	.mas_rpm_id = -1,
1041 	.slv_rpm_id = 217,
1042 	.qos.ap_owned = true,
1043 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1044 };
1045 
1046 static struct qcom_icc_node slv_ufs_cfg = {
1047 	.name = "slv_ufs_cfg",
1048 	.id = SDM660_SLAVE_UFS_CFG,
1049 	.buswidth = 4,
1050 	.mas_rpm_id = -1,
1051 	.slv_rpm_id = 92,
1052 	.qos.ap_owned = true,
1053 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1054 };
1055 
1056 static struct qcom_icc_node slv_a2noc_cfg = {
1057 	.name = "slv_a2noc_cfg",
1058 	.id = SDM660_SLAVE_A2NOC_CFG,
1059 	.buswidth = 4,
1060 	.mas_rpm_id = -1,
1061 	.slv_rpm_id = 150,
1062 	.qos.ap_owned = true,
1063 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1064 };
1065 
1066 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1067 	.name = "slv_a2noc_smmu_cfg",
1068 	.id = SDM660_SLAVE_A2NOC_SMMU_CFG,
1069 	.buswidth = 8,
1070 	.mas_rpm_id = -1,
1071 	.slv_rpm_id = 152,
1072 	.qos.ap_owned = true,
1073 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1074 };
1075 
1076 static struct qcom_icc_node slv_gpuss_cfg = {
1077 	.name = "slv_gpuss_cfg",
1078 	.id = SDM660_SLAVE_GPUSS_CFG,
1079 	.buswidth = 8,
1080 	.mas_rpm_id = -1,
1081 	.slv_rpm_id = 11,
1082 	.qos.ap_owned = true,
1083 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1084 };
1085 
1086 static struct qcom_icc_node slv_ahb2phy = {
1087 	.name = "slv_ahb2phy",
1088 	.id = SDM660_SLAVE_AHB2PHY,
1089 	.buswidth = 4,
1090 	.mas_rpm_id = -1,
1091 	.slv_rpm_id = 163,
1092 	.qos.ap_owned = true,
1093 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1094 };
1095 
1096 static struct qcom_icc_node slv_blsp_1 = {
1097 	.name = "slv_blsp_1",
1098 	.id = SDM660_SLAVE_BLSP_1,
1099 	.buswidth = 4,
1100 	.mas_rpm_id = -1,
1101 	.slv_rpm_id = 39,
1102 	.qos.ap_owned = true,
1103 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1104 };
1105 
1106 static struct qcom_icc_node slv_sdcc_1 = {
1107 	.name = "slv_sdcc_1",
1108 	.id = SDM660_SLAVE_SDCC_1,
1109 	.buswidth = 4,
1110 	.mas_rpm_id = -1,
1111 	.slv_rpm_id = 31,
1112 	.qos.ap_owned = true,
1113 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1114 };
1115 
1116 static struct qcom_icc_node slv_sdcc_2 = {
1117 	.name = "slv_sdcc_2",
1118 	.id = SDM660_SLAVE_SDCC_2,
1119 	.buswidth = 4,
1120 	.mas_rpm_id = -1,
1121 	.slv_rpm_id = 33,
1122 	.qos.ap_owned = true,
1123 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1124 };
1125 
1126 static struct qcom_icc_node slv_tlmm_center = {
1127 	.name = "slv_tlmm_center",
1128 	.id = SDM660_SLAVE_TLMM_CENTER,
1129 	.buswidth = 4,
1130 	.mas_rpm_id = -1,
1131 	.slv_rpm_id = 218,
1132 	.qos.ap_owned = true,
1133 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1134 };
1135 
1136 static struct qcom_icc_node slv_blsp_2 = {
1137 	.name = "slv_blsp_2",
1138 	.id = SDM660_SLAVE_BLSP_2,
1139 	.buswidth = 4,
1140 	.mas_rpm_id = -1,
1141 	.slv_rpm_id = 37,
1142 	.qos.ap_owned = true,
1143 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1144 };
1145 
1146 static struct qcom_icc_node slv_pdm = {
1147 	.name = "slv_pdm",
1148 	.id = SDM660_SLAVE_PDM,
1149 	.buswidth = 4,
1150 	.mas_rpm_id = -1,
1151 	.slv_rpm_id = 41,
1152 	.qos.ap_owned = true,
1153 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1154 };
1155 
1156 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1157 	SDM660_MASTER_CNOC_MNOC_MMSS_CFG
1158 };
1159 
1160 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1161 	.name = "slv_cnoc_mnoc_mmss_cfg",
1162 	.id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
1163 	.buswidth = 8,
1164 	.mas_rpm_id = -1,
1165 	.slv_rpm_id = 58,
1166 	.qos.ap_owned = true,
1167 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1168 	.num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1169 	.links = slv_cnoc_mnoc_mmss_cfg_links,
1170 };
1171 
1172 static struct qcom_icc_node slv_usb_hs = {
1173 	.name = "slv_usb_hs",
1174 	.id = SDM660_SLAVE_USB_HS,
1175 	.buswidth = 4,
1176 	.mas_rpm_id = -1,
1177 	.slv_rpm_id = 40,
1178 	.qos.ap_owned = true,
1179 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1180 };
1181 
1182 static struct qcom_icc_node slv_usb3_0 = {
1183 	.name = "slv_usb3_0",
1184 	.id = SDM660_SLAVE_USB3_0,
1185 	.buswidth = 4,
1186 	.mas_rpm_id = -1,
1187 	.slv_rpm_id = 22,
1188 	.qos.ap_owned = true,
1189 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1190 };
1191 
1192 static struct qcom_icc_node slv_srvc_cnoc = {
1193 	.name = "slv_srvc_cnoc",
1194 	.id = SDM660_SLAVE_SRVC_CNOC,
1195 	.buswidth = 4,
1196 	.mas_rpm_id = -1,
1197 	.slv_rpm_id = 76,
1198 	.qos.ap_owned = true,
1199 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1200 };
1201 
1202 static const u16 slv_gnoc_bimc_links[] = {
1203 	SDM660_MASTER_GNOC_BIMC
1204 };
1205 
1206 static struct qcom_icc_node slv_gnoc_bimc = {
1207 	.name = "slv_gnoc_bimc",
1208 	.id = SDM660_SLAVE_GNOC_BIMC,
1209 	.buswidth = 16,
1210 	.mas_rpm_id = -1,
1211 	.slv_rpm_id = 210,
1212 	.qos.ap_owned = true,
1213 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1214 	.num_links = ARRAY_SIZE(slv_gnoc_bimc_links),
1215 	.links = slv_gnoc_bimc_links,
1216 };
1217 
1218 static const u16 slv_gnoc_snoc_links[] = {
1219 	SDM660_MASTER_GNOC_SNOC
1220 };
1221 
1222 static struct qcom_icc_node slv_gnoc_snoc = {
1223 	.name = "slv_gnoc_snoc",
1224 	.id = SDM660_SLAVE_GNOC_SNOC,
1225 	.buswidth = 8,
1226 	.mas_rpm_id = -1,
1227 	.slv_rpm_id = 211,
1228 	.qos.ap_owned = true,
1229 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1230 	.num_links = ARRAY_SIZE(slv_gnoc_snoc_links),
1231 	.links = slv_gnoc_snoc_links,
1232 };
1233 
1234 static struct qcom_icc_node slv_camera_cfg = {
1235 	.name = "slv_camera_cfg",
1236 	.id = SDM660_SLAVE_CAMERA_CFG,
1237 	.buswidth = 4,
1238 	.mas_rpm_id = -1,
1239 	.slv_rpm_id = 3,
1240 	.qos.ap_owned = true,
1241 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1242 };
1243 
1244 static struct qcom_icc_node slv_camera_throttle_cfg = {
1245 	.name = "slv_camera_throttle_cfg",
1246 	.id = SDM660_SLAVE_CAMERA_THROTTLE_CFG,
1247 	.buswidth = 4,
1248 	.mas_rpm_id = -1,
1249 	.slv_rpm_id = 154,
1250 	.qos.ap_owned = true,
1251 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1252 };
1253 
1254 static struct qcom_icc_node slv_misc_cfg = {
1255 	.name = "slv_misc_cfg",
1256 	.id = SDM660_SLAVE_MISC_CFG,
1257 	.buswidth = 4,
1258 	.mas_rpm_id = -1,
1259 	.slv_rpm_id = 8,
1260 	.qos.ap_owned = true,
1261 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1262 };
1263 
1264 static struct qcom_icc_node slv_venus_throttle_cfg = {
1265 	.name = "slv_venus_throttle_cfg",
1266 	.id = SDM660_SLAVE_VENUS_THROTTLE_CFG,
1267 	.buswidth = 4,
1268 	.mas_rpm_id = -1,
1269 	.slv_rpm_id = 178,
1270 	.qos.ap_owned = true,
1271 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1272 };
1273 
1274 static struct qcom_icc_node slv_venus_cfg = {
1275 	.name = "slv_venus_cfg",
1276 	.id = SDM660_SLAVE_VENUS_CFG,
1277 	.buswidth = 4,
1278 	.mas_rpm_id = -1,
1279 	.slv_rpm_id = 10,
1280 	.qos.ap_owned = true,
1281 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1282 };
1283 
1284 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
1285 	.name = "slv_mmss_clk_xpu_cfg",
1286 	.id = SDM660_SLAVE_MMSS_CLK_XPU_CFG,
1287 	.buswidth = 4,
1288 	.mas_rpm_id = -1,
1289 	.slv_rpm_id = 13,
1290 	.qos.ap_owned = true,
1291 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1292 };
1293 
1294 static struct qcom_icc_node slv_mmss_clk_cfg = {
1295 	.name = "slv_mmss_clk_cfg",
1296 	.id = SDM660_SLAVE_MMSS_CLK_CFG,
1297 	.buswidth = 4,
1298 	.mas_rpm_id = -1,
1299 	.slv_rpm_id = 12,
1300 	.qos.ap_owned = true,
1301 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1302 };
1303 
1304 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1305 	.name = "slv_mnoc_mpu_cfg",
1306 	.id = SDM660_SLAVE_MNOC_MPU_CFG,
1307 	.buswidth = 4,
1308 	.mas_rpm_id = -1,
1309 	.slv_rpm_id = 14,
1310 	.qos.ap_owned = true,
1311 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1312 };
1313 
1314 static struct qcom_icc_node slv_display_cfg = {
1315 	.name = "slv_display_cfg",
1316 	.id = SDM660_SLAVE_DISPLAY_CFG,
1317 	.buswidth = 4,
1318 	.mas_rpm_id = -1,
1319 	.slv_rpm_id = 4,
1320 	.qos.ap_owned = true,
1321 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1322 };
1323 
1324 static struct qcom_icc_node slv_csi_phy_cfg = {
1325 	.name = "slv_csi_phy_cfg",
1326 	.id = SDM660_SLAVE_CSI_PHY_CFG,
1327 	.buswidth = 4,
1328 	.mas_rpm_id = -1,
1329 	.slv_rpm_id = 224,
1330 	.qos.ap_owned = true,
1331 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1332 };
1333 
1334 static struct qcom_icc_node slv_display_throttle_cfg = {
1335 	.name = "slv_display_throttle_cfg",
1336 	.id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
1337 	.buswidth = 4,
1338 	.mas_rpm_id = -1,
1339 	.slv_rpm_id = 156,
1340 	.qos.ap_owned = true,
1341 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1342 };
1343 
1344 static struct qcom_icc_node slv_smmu_cfg = {
1345 	.name = "slv_smmu_cfg",
1346 	.id = SDM660_SLAVE_SMMU_CFG,
1347 	.buswidth = 8,
1348 	.mas_rpm_id = -1,
1349 	.slv_rpm_id = 205,
1350 	.qos.ap_owned = true,
1351 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1352 };
1353 
1354 static const u16 slv_mnoc_bimc_links[] = {
1355 	SDM660_MASTER_MNOC_BIMC
1356 };
1357 
1358 static struct qcom_icc_node slv_mnoc_bimc = {
1359 	.name = "slv_mnoc_bimc",
1360 	.id = SDM660_SLAVE_MNOC_BIMC,
1361 	.buswidth = 16,
1362 	.mas_rpm_id = -1,
1363 	.slv_rpm_id = 16,
1364 	.qos.ap_owned = true,
1365 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1366 	.num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1367 	.links = slv_mnoc_bimc_links,
1368 };
1369 
1370 static struct qcom_icc_node slv_srvc_mnoc = {
1371 	.name = "slv_srvc_mnoc",
1372 	.id = SDM660_SLAVE_SRVC_MNOC,
1373 	.buswidth = 8,
1374 	.mas_rpm_id = -1,
1375 	.slv_rpm_id = 17,
1376 	.qos.ap_owned = true,
1377 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1378 };
1379 
1380 static struct qcom_icc_node slv_hmss = {
1381 	.name = "slv_hmss",
1382 	.id = SDM660_SLAVE_HMSS,
1383 	.buswidth = 8,
1384 	.mas_rpm_id = -1,
1385 	.slv_rpm_id = 20,
1386 	.qos.ap_owned = true,
1387 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1388 };
1389 
1390 static struct qcom_icc_node slv_lpass = {
1391 	.name = "slv_lpass",
1392 	.id = SDM660_SLAVE_LPASS,
1393 	.buswidth = 4,
1394 	.mas_rpm_id = -1,
1395 	.slv_rpm_id = 21,
1396 	.qos.ap_owned = true,
1397 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1398 };
1399 
1400 static struct qcom_icc_node slv_wlan = {
1401 	.name = "slv_wlan",
1402 	.id = SDM660_SLAVE_WLAN,
1403 	.buswidth = 4,
1404 	.mas_rpm_id = -1,
1405 	.slv_rpm_id = 206,
1406 };
1407 
1408 static struct qcom_icc_node slv_cdsp = {
1409 	.name = "slv_cdsp",
1410 	.id = SDM660_SLAVE_CDSP,
1411 	.buswidth = 4,
1412 	.mas_rpm_id = -1,
1413 	.slv_rpm_id = 221,
1414 	.qos.ap_owned = true,
1415 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1416 };
1417 
1418 static struct qcom_icc_node slv_ipa = {
1419 	.name = "slv_ipa",
1420 	.id = SDM660_SLAVE_IPA,
1421 	.buswidth = 4,
1422 	.mas_rpm_id = -1,
1423 	.slv_rpm_id = 183,
1424 	.qos.ap_owned = true,
1425 	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1426 };
1427 
1428 static const u16 slv_snoc_bimc_links[] = {
1429 	SDM660_MASTER_SNOC_BIMC
1430 };
1431 
1432 static struct qcom_icc_node slv_snoc_bimc = {
1433 	.name = "slv_snoc_bimc",
1434 	.id = SDM660_SLAVE_SNOC_BIMC,
1435 	.buswidth = 16,
1436 	.mas_rpm_id = -1,
1437 	.slv_rpm_id = 24,
1438 	.num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1439 	.links = slv_snoc_bimc_links,
1440 };
1441 
1442 static const u16 slv_snoc_cnoc_links[] = {
1443 	SDM660_MASTER_SNOC_CNOC
1444 };
1445 
1446 static struct qcom_icc_node slv_snoc_cnoc = {
1447 	.name = "slv_snoc_cnoc",
1448 	.id = SDM660_SLAVE_SNOC_CNOC,
1449 	.buswidth = 8,
1450 	.mas_rpm_id = -1,
1451 	.slv_rpm_id = 25,
1452 	.num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1453 	.links = slv_snoc_cnoc_links,
1454 };
1455 
1456 static struct qcom_icc_node slv_imem = {
1457 	.name = "slv_imem",
1458 	.id = SDM660_SLAVE_IMEM,
1459 	.buswidth = 8,
1460 	.mas_rpm_id = -1,
1461 	.slv_rpm_id = 26,
1462 };
1463 
1464 static struct qcom_icc_node slv_pimem = {
1465 	.name = "slv_pimem",
1466 	.id = SDM660_SLAVE_PIMEM,
1467 	.buswidth = 8,
1468 	.mas_rpm_id = -1,
1469 	.slv_rpm_id = 166,
1470 };
1471 
1472 static struct qcom_icc_node slv_qdss_stm = {
1473 	.name = "slv_qdss_stm",
1474 	.id = SDM660_SLAVE_QDSS_STM,
1475 	.buswidth = 4,
1476 	.mas_rpm_id = -1,
1477 	.slv_rpm_id = 30,
1478 };
1479 
1480 static struct qcom_icc_node slv_srvc_snoc = {
1481 	.name = "slv_srvc_snoc",
1482 	.id = SDM660_SLAVE_SRVC_SNOC,
1483 	.buswidth = 16,
1484 	.mas_rpm_id = -1,
1485 	.slv_rpm_id = 29,
1486 };
1487 
1488 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = {
1489 	[MASTER_IPA] = &mas_ipa,
1490 	[MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
1491 	[MASTER_SDCC_1] = &mas_sdcc_1,
1492 	[MASTER_SDCC_2] = &mas_sdcc_2,
1493 	[MASTER_BLSP_1] = &mas_blsp_1,
1494 	[MASTER_BLSP_2] = &mas_blsp_2,
1495 	[MASTER_UFS] = &mas_ufs,
1496 	[MASTER_USB_HS] = &mas_usb_hs,
1497 	[MASTER_USB3] = &mas_usb3,
1498 	[MASTER_CRYPTO_C0] = &mas_crypto,
1499 	[SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
1500 };
1501 
1502 static const struct regmap_config sdm660_a2noc_regmap_config = {
1503 	.reg_bits	= 32,
1504 	.reg_stride	= 4,
1505 	.val_bits	= 32,
1506 	.max_register	= 0x20000,
1507 	.fast_io	= true,
1508 };
1509 
1510 static const struct qcom_icc_desc sdm660_a2noc = {
1511 	.type = QCOM_ICC_NOC,
1512 	.nodes = sdm660_a2noc_nodes,
1513 	.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1514 	.bus_clk_desc = &aggre2_clk,
1515 	.intf_clocks = a2noc_intf_clocks,
1516 	.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1517 	.regmap_cfg = &sdm660_a2noc_regmap_config,
1518 };
1519 
1520 static struct qcom_icc_node * const sdm660_bimc_nodes[] = {
1521 	[MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
1522 	[MASTER_OXILI] = &mas_oxili,
1523 	[MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1524 	[MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1525 	[MASTER_PIMEM] = &mas_pimem,
1526 	[SLAVE_EBI] = &slv_ebi,
1527 	[SLAVE_HMSS_L3] = &slv_hmss_l3,
1528 	[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1529 };
1530 
1531 static const struct regmap_config sdm660_bimc_regmap_config = {
1532 	.reg_bits	= 32,
1533 	.reg_stride	= 4,
1534 	.val_bits	= 32,
1535 	.max_register	= 0x80000,
1536 	.fast_io	= true,
1537 };
1538 
1539 static const struct qcom_icc_desc sdm660_bimc = {
1540 	.type = QCOM_ICC_BIMC,
1541 	.nodes = sdm660_bimc_nodes,
1542 	.num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
1543 	.bus_clk_desc = &bimc_clk,
1544 	.regmap_cfg = &sdm660_bimc_regmap_config,
1545 	.ab_coeff = 153,
1546 };
1547 
1548 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = {
1549 	[MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1550 	[MASTER_QDSS_DAP] = &mas_qdss_dap,
1551 	[SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
1552 	[SLAVE_MPM] = &slv_mpm,
1553 	[SLAVE_PMIC_ARB] = &slv_pmic_arb,
1554 	[SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1555 	[SLAVE_TCSR] = &slv_tcsr,
1556 	[SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1557 	[SLAVE_IMEM_CFG] = &slv_imem_cfg,
1558 	[SLAVE_MESSAGE_RAM] = &slv_message_ram,
1559 	[SLAVE_GLM] = &slv_glm,
1560 	[SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1561 	[SLAVE_PRNG] = &slv_prng,
1562 	[SLAVE_SPDM] = &slv_spdm,
1563 	[SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1564 	[SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1565 	[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1566 	[SLAVE_QM_CFG] = &slv_qm_cfg,
1567 	[SLAVE_CLK_CTL] = &slv_clk_ctl,
1568 	[SLAVE_MSS_CFG] = &slv_mss_cfg,
1569 	[SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1570 	[SLAVE_UFS_CFG] = &slv_ufs_cfg,
1571 	[SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1572 	[SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1573 	[SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
1574 	[SLAVE_AHB2PHY] = &slv_ahb2phy,
1575 	[SLAVE_BLSP_1] = &slv_blsp_1,
1576 	[SLAVE_SDCC_1] = &slv_sdcc_1,
1577 	[SLAVE_SDCC_2] = &slv_sdcc_2,
1578 	[SLAVE_TLMM_CENTER] = &slv_tlmm_center,
1579 	[SLAVE_BLSP_2] = &slv_blsp_2,
1580 	[SLAVE_PDM] = &slv_pdm,
1581 	[SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
1582 	[SLAVE_USB_HS] = &slv_usb_hs,
1583 	[SLAVE_USB3_0] = &slv_usb3_0,
1584 	[SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
1585 };
1586 
1587 static const struct regmap_config sdm660_cnoc_regmap_config = {
1588 	.reg_bits	= 32,
1589 	.reg_stride	= 4,
1590 	.val_bits	= 32,
1591 	.max_register	= 0x10000,
1592 	.fast_io	= true,
1593 };
1594 
1595 static const struct qcom_icc_desc sdm660_cnoc = {
1596 	.type = QCOM_ICC_NOC,
1597 	.nodes = sdm660_cnoc_nodes,
1598 	.num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
1599 	.bus_clk_desc = &bus_2_clk,
1600 	.regmap_cfg = &sdm660_cnoc_regmap_config,
1601 };
1602 
1603 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = {
1604 	[MASTER_APSS_PROC] = &mas_apss_proc,
1605 	[SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
1606 	[SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
1607 };
1608 
1609 static const struct regmap_config sdm660_gnoc_regmap_config = {
1610 	.reg_bits	= 32,
1611 	.reg_stride	= 4,
1612 	.val_bits	= 32,
1613 	.max_register	= 0xe000,
1614 	.fast_io	= true,
1615 };
1616 
1617 static const struct qcom_icc_desc sdm660_gnoc = {
1618 	.type = QCOM_ICC_NOC,
1619 	.nodes = sdm660_gnoc_nodes,
1620 	.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1621 	.regmap_cfg = &sdm660_gnoc_regmap_config,
1622 };
1623 
1624 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
1625 	[MASTER_CPP] = &mas_cpp,
1626 	[MASTER_JPEG] = &mas_jpeg,
1627 	[MASTER_MDP_P0] = &mas_mdp_p0,
1628 	[MASTER_MDP_P1] = &mas_mdp_p1,
1629 	[MASTER_VENUS] = &mas_venus,
1630 	[MASTER_VFE] = &mas_vfe,
1631 	[MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1632 	[MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1633 	[SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1634 	[SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1635 	[SLAVE_MISC_CFG] = &slv_misc_cfg,
1636 	[SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1637 	[SLAVE_VENUS_CFG] = &slv_venus_cfg,
1638 	[SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
1639 	[SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
1640 	[SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1641 	[SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1642 	[SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
1643 	[SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1644 	[SLAVE_SMMU_CFG] = &slv_smmu_cfg,
1645 	[SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
1646 	[SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1647 };
1648 
1649 static const struct regmap_config sdm660_mnoc_regmap_config = {
1650 	.reg_bits	= 32,
1651 	.reg_stride	= 4,
1652 	.val_bits	= 32,
1653 	.max_register	= 0x10000,
1654 	.fast_io	= true,
1655 };
1656 
1657 static const struct qcom_icc_desc sdm660_mnoc = {
1658 	.type = QCOM_ICC_NOC,
1659 	.nodes = sdm660_mnoc_nodes,
1660 	.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1661 	.bus_clk_desc = &mmaxi_0_clk,
1662 	.intf_clocks = mm_intf_clocks,
1663 	.num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
1664 	.regmap_cfg = &sdm660_mnoc_regmap_config,
1665 	.ab_coeff = 153,
1666 };
1667 
1668 static struct qcom_icc_node * const sdm660_snoc_nodes[] = {
1669 	[MASTER_QDSS_ETR] = &mas_qdss_etr,
1670 	[MASTER_QDSS_BAM] = &mas_qdss_bam,
1671 	[MASTER_SNOC_CFG] = &mas_snoc_cfg,
1672 	[MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1673 	[MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
1674 	[MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
1675 	[SLAVE_HMSS] = &slv_hmss,
1676 	[SLAVE_LPASS] = &slv_lpass,
1677 	[SLAVE_WLAN] = &slv_wlan,
1678 	[SLAVE_CDSP] = &slv_cdsp,
1679 	[SLAVE_IPA] = &slv_ipa,
1680 	[SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1681 	[SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1682 	[SLAVE_IMEM] = &slv_imem,
1683 	[SLAVE_PIMEM] = &slv_pimem,
1684 	[SLAVE_QDSS_STM] = &slv_qdss_stm,
1685 	[SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1686 };
1687 
1688 static const struct regmap_config sdm660_snoc_regmap_config = {
1689 	.reg_bits	= 32,
1690 	.reg_stride	= 4,
1691 	.val_bits	= 32,
1692 	.max_register	= 0x20000,
1693 	.fast_io	= true,
1694 };
1695 
1696 static const struct qcom_icc_desc sdm660_snoc = {
1697 	.type = QCOM_ICC_NOC,
1698 	.nodes = sdm660_snoc_nodes,
1699 	.num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
1700 	.bus_clk_desc = &bus_1_clk,
1701 	.regmap_cfg = &sdm660_snoc_regmap_config,
1702 };
1703 
1704 static const struct of_device_id sdm660_noc_of_match[] = {
1705 	{ .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
1706 	{ .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
1707 	{ .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
1708 	{ .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
1709 	{ .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
1710 	{ .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
1711 	{ },
1712 };
1713 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
1714 
1715 static struct platform_driver sdm660_noc_driver = {
1716 	.probe = qnoc_probe,
1717 	.remove_new = qnoc_remove,
1718 	.driver = {
1719 		.name = "qnoc-sdm660",
1720 		.of_match_table = sdm660_noc_of_match,
1721 	},
1722 };
1723 module_platform_driver(sdm660_noc_driver);
1724 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
1725 MODULE_LICENSE("GPL v2");
1726