1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver 4 * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7 #include <dt-bindings/interconnect/qcom,sdm660.h> 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 19 #include "icc-rpm.h" 20 #include "smd-rpm.h" 21 22 enum { 23 SDM660_MASTER_IPA = 1, 24 SDM660_MASTER_CNOC_A2NOC, 25 SDM660_MASTER_SDCC_1, 26 SDM660_MASTER_SDCC_2, 27 SDM660_MASTER_BLSP_1, 28 SDM660_MASTER_BLSP_2, 29 SDM660_MASTER_UFS, 30 SDM660_MASTER_USB_HS, 31 SDM660_MASTER_USB3, 32 SDM660_MASTER_CRYPTO_C0, 33 SDM660_MASTER_GNOC_BIMC, 34 SDM660_MASTER_OXILI, 35 SDM660_MASTER_MNOC_BIMC, 36 SDM660_MASTER_SNOC_BIMC, 37 SDM660_MASTER_PIMEM, 38 SDM660_MASTER_SNOC_CNOC, 39 SDM660_MASTER_QDSS_DAP, 40 SDM660_MASTER_APPS_PROC, 41 SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 42 SDM660_MASTER_CNOC_MNOC_CFG, 43 SDM660_MASTER_CPP, 44 SDM660_MASTER_JPEG, 45 SDM660_MASTER_MDP_P0, 46 SDM660_MASTER_MDP_P1, 47 SDM660_MASTER_VENUS, 48 SDM660_MASTER_VFE, 49 SDM660_MASTER_QDSS_ETR, 50 SDM660_MASTER_QDSS_BAM, 51 SDM660_MASTER_SNOC_CFG, 52 SDM660_MASTER_BIMC_SNOC, 53 SDM660_MASTER_A2NOC_SNOC, 54 SDM660_MASTER_GNOC_SNOC, 55 56 SDM660_SLAVE_A2NOC_SNOC, 57 SDM660_SLAVE_EBI, 58 SDM660_SLAVE_HMSS_L3, 59 SDM660_SLAVE_BIMC_SNOC, 60 SDM660_SLAVE_CNOC_A2NOC, 61 SDM660_SLAVE_MPM, 62 SDM660_SLAVE_PMIC_ARB, 63 SDM660_SLAVE_TLMM_NORTH, 64 SDM660_SLAVE_TCSR, 65 SDM660_SLAVE_PIMEM_CFG, 66 SDM660_SLAVE_IMEM_CFG, 67 SDM660_SLAVE_MESSAGE_RAM, 68 SDM660_SLAVE_GLM, 69 SDM660_SLAVE_BIMC_CFG, 70 SDM660_SLAVE_PRNG, 71 SDM660_SLAVE_SPDM, 72 SDM660_SLAVE_QDSS_CFG, 73 SDM660_SLAVE_CNOC_MNOC_CFG, 74 SDM660_SLAVE_SNOC_CFG, 75 SDM660_SLAVE_QM_CFG, 76 SDM660_SLAVE_CLK_CTL, 77 SDM660_SLAVE_MSS_CFG, 78 SDM660_SLAVE_TLMM_SOUTH, 79 SDM660_SLAVE_UFS_CFG, 80 SDM660_SLAVE_A2NOC_CFG, 81 SDM660_SLAVE_A2NOC_SMMU_CFG, 82 SDM660_SLAVE_GPUSS_CFG, 83 SDM660_SLAVE_AHB2PHY, 84 SDM660_SLAVE_BLSP_1, 85 SDM660_SLAVE_SDCC_1, 86 SDM660_SLAVE_SDCC_2, 87 SDM660_SLAVE_TLMM_CENTER, 88 SDM660_SLAVE_BLSP_2, 89 SDM660_SLAVE_PDM, 90 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 91 SDM660_SLAVE_USB_HS, 92 SDM660_SLAVE_USB3_0, 93 SDM660_SLAVE_SRVC_CNOC, 94 SDM660_SLAVE_GNOC_BIMC, 95 SDM660_SLAVE_GNOC_SNOC, 96 SDM660_SLAVE_CAMERA_CFG, 97 SDM660_SLAVE_CAMERA_THROTTLE_CFG, 98 SDM660_SLAVE_MISC_CFG, 99 SDM660_SLAVE_VENUS_THROTTLE_CFG, 100 SDM660_SLAVE_VENUS_CFG, 101 SDM660_SLAVE_MMSS_CLK_XPU_CFG, 102 SDM660_SLAVE_MMSS_CLK_CFG, 103 SDM660_SLAVE_MNOC_MPU_CFG, 104 SDM660_SLAVE_DISPLAY_CFG, 105 SDM660_SLAVE_CSI_PHY_CFG, 106 SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 107 SDM660_SLAVE_SMMU_CFG, 108 SDM660_SLAVE_MNOC_BIMC, 109 SDM660_SLAVE_SRVC_MNOC, 110 SDM660_SLAVE_HMSS, 111 SDM660_SLAVE_LPASS, 112 SDM660_SLAVE_WLAN, 113 SDM660_SLAVE_CDSP, 114 SDM660_SLAVE_IPA, 115 SDM660_SLAVE_SNOC_BIMC, 116 SDM660_SLAVE_SNOC_CNOC, 117 SDM660_SLAVE_IMEM, 118 SDM660_SLAVE_PIMEM, 119 SDM660_SLAVE_QDSS_STM, 120 SDM660_SLAVE_SRVC_SNOC, 121 122 SDM660_A2NOC, 123 SDM660_BIMC, 124 SDM660_CNOC, 125 SDM660_GNOC, 126 SDM660_MNOC, 127 SDM660_SNOC, 128 }; 129 130 static const char * const bus_mm_clocks[] = { 131 "bus", 132 "bus_a", 133 "iface", 134 }; 135 136 static const char * const bus_a2noc_clocks[] = { 137 "bus", 138 "bus_a", 139 "ipa", 140 "ufs_axi", 141 "aggre2_ufs_axi", 142 "aggre2_usb3_axi", 143 "cfg_noc_usb2_axi", 144 }; 145 146 static const u16 mas_ipa_links[] = { 147 SDM660_SLAVE_A2NOC_SNOC 148 }; 149 150 static struct qcom_icc_node mas_ipa = { 151 .name = "mas_ipa", 152 .id = SDM660_MASTER_IPA, 153 .buswidth = 8, 154 .mas_rpm_id = 59, 155 .slv_rpm_id = -1, 156 .qos.ap_owned = true, 157 .qos.qos_mode = NOC_QOS_MODE_FIXED, 158 .qos.areq_prio = 1, 159 .qos.prio_level = 1, 160 .qos.qos_port = 3, 161 .num_links = ARRAY_SIZE(mas_ipa_links), 162 .links = mas_ipa_links, 163 }; 164 165 static const u16 mas_cnoc_a2noc_links[] = { 166 SDM660_SLAVE_A2NOC_SNOC 167 }; 168 169 static struct qcom_icc_node mas_cnoc_a2noc = { 170 .name = "mas_cnoc_a2noc", 171 .id = SDM660_MASTER_CNOC_A2NOC, 172 .buswidth = 8, 173 .mas_rpm_id = 146, 174 .slv_rpm_id = -1, 175 .qos.ap_owned = true, 176 .qos.qos_mode = NOC_QOS_MODE_INVALID, 177 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links), 178 .links = mas_cnoc_a2noc_links, 179 }; 180 181 static const u16 mas_sdcc_1_links[] = { 182 SDM660_SLAVE_A2NOC_SNOC 183 }; 184 185 static struct qcom_icc_node mas_sdcc_1 = { 186 .name = "mas_sdcc_1", 187 .id = SDM660_MASTER_SDCC_1, 188 .buswidth = 8, 189 .mas_rpm_id = 33, 190 .slv_rpm_id = -1, 191 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 192 .links = mas_sdcc_1_links, 193 }; 194 195 static const u16 mas_sdcc_2_links[] = { 196 SDM660_SLAVE_A2NOC_SNOC 197 }; 198 199 static struct qcom_icc_node mas_sdcc_2 = { 200 .name = "mas_sdcc_2", 201 .id = SDM660_MASTER_SDCC_2, 202 .buswidth = 8, 203 .mas_rpm_id = 35, 204 .slv_rpm_id = -1, 205 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 206 .links = mas_sdcc_2_links, 207 }; 208 209 static const u16 mas_blsp_1_links[] = { 210 SDM660_SLAVE_A2NOC_SNOC 211 }; 212 213 static struct qcom_icc_node mas_blsp_1 = { 214 .name = "mas_blsp_1", 215 .id = SDM660_MASTER_BLSP_1, 216 .buswidth = 4, 217 .mas_rpm_id = 41, 218 .slv_rpm_id = -1, 219 .num_links = ARRAY_SIZE(mas_blsp_1_links), 220 .links = mas_blsp_1_links, 221 }; 222 223 static const u16 mas_blsp_2_links[] = { 224 SDM660_SLAVE_A2NOC_SNOC 225 }; 226 227 static struct qcom_icc_node mas_blsp_2 = { 228 .name = "mas_blsp_2", 229 .id = SDM660_MASTER_BLSP_2, 230 .buswidth = 4, 231 .mas_rpm_id = 39, 232 .slv_rpm_id = -1, 233 .num_links = ARRAY_SIZE(mas_blsp_2_links), 234 .links = mas_blsp_2_links, 235 }; 236 237 static const u16 mas_ufs_links[] = { 238 SDM660_SLAVE_A2NOC_SNOC 239 }; 240 241 static struct qcom_icc_node mas_ufs = { 242 .name = "mas_ufs", 243 .id = SDM660_MASTER_UFS, 244 .buswidth = 8, 245 .mas_rpm_id = 68, 246 .slv_rpm_id = -1, 247 .qos.ap_owned = true, 248 .qos.qos_mode = NOC_QOS_MODE_FIXED, 249 .qos.areq_prio = 1, 250 .qos.prio_level = 1, 251 .qos.qos_port = 4, 252 .num_links = ARRAY_SIZE(mas_ufs_links), 253 .links = mas_ufs_links, 254 }; 255 256 static const u16 mas_usb_hs_links[] = { 257 SDM660_SLAVE_A2NOC_SNOC 258 }; 259 260 static struct qcom_icc_node mas_usb_hs = { 261 .name = "mas_usb_hs", 262 .id = SDM660_MASTER_USB_HS, 263 .buswidth = 8, 264 .mas_rpm_id = 42, 265 .slv_rpm_id = -1, 266 .qos.ap_owned = true, 267 .qos.qos_mode = NOC_QOS_MODE_FIXED, 268 .qos.areq_prio = 1, 269 .qos.prio_level = 1, 270 .qos.qos_port = 1, 271 .num_links = ARRAY_SIZE(mas_usb_hs_links), 272 .links = mas_usb_hs_links, 273 }; 274 275 static const u16 mas_usb3_links[] = { 276 SDM660_SLAVE_A2NOC_SNOC 277 }; 278 279 static struct qcom_icc_node mas_usb3 = { 280 .name = "mas_usb3", 281 .id = SDM660_MASTER_USB3, 282 .buswidth = 8, 283 .mas_rpm_id = 32, 284 .slv_rpm_id = -1, 285 .qos.ap_owned = true, 286 .qos.qos_mode = NOC_QOS_MODE_FIXED, 287 .qos.areq_prio = 1, 288 .qos.prio_level = 1, 289 .qos.qos_port = 2, 290 .num_links = ARRAY_SIZE(mas_usb3_links), 291 .links = mas_usb3_links, 292 }; 293 294 static const u16 mas_crypto_links[] = { 295 SDM660_SLAVE_A2NOC_SNOC 296 }; 297 298 static struct qcom_icc_node mas_crypto = { 299 .name = "mas_crypto", 300 .id = SDM660_MASTER_CRYPTO_C0, 301 .buswidth = 8, 302 .mas_rpm_id = 23, 303 .slv_rpm_id = -1, 304 .qos.ap_owned = true, 305 .qos.qos_mode = NOC_QOS_MODE_FIXED, 306 .qos.areq_prio = 1, 307 .qos.prio_level = 1, 308 .qos.qos_port = 11, 309 .num_links = ARRAY_SIZE(mas_crypto_links), 310 .links = mas_crypto_links, 311 }; 312 313 static const u16 mas_gnoc_bimc_links[] = { 314 SDM660_SLAVE_EBI 315 }; 316 317 static struct qcom_icc_node mas_gnoc_bimc = { 318 .name = "mas_gnoc_bimc", 319 .id = SDM660_MASTER_GNOC_BIMC, 320 .buswidth = 4, 321 .mas_rpm_id = 144, 322 .slv_rpm_id = -1, 323 .qos.ap_owned = true, 324 .qos.qos_mode = NOC_QOS_MODE_FIXED, 325 .qos.areq_prio = 0, 326 .qos.prio_level = 0, 327 .qos.qos_port = 0, 328 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links), 329 .links = mas_gnoc_bimc_links, 330 }; 331 332 static const u16 mas_oxili_links[] = { 333 SDM660_SLAVE_HMSS_L3, 334 SDM660_SLAVE_EBI, 335 SDM660_SLAVE_BIMC_SNOC 336 }; 337 338 static struct qcom_icc_node mas_oxili = { 339 .name = "mas_oxili", 340 .id = SDM660_MASTER_OXILI, 341 .buswidth = 4, 342 .mas_rpm_id = 6, 343 .slv_rpm_id = -1, 344 .qos.ap_owned = true, 345 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 346 .qos.areq_prio = 0, 347 .qos.prio_level = 0, 348 .qos.qos_port = 1, 349 .num_links = ARRAY_SIZE(mas_oxili_links), 350 .links = mas_oxili_links, 351 }; 352 353 static const u16 mas_mnoc_bimc_links[] = { 354 SDM660_SLAVE_HMSS_L3, 355 SDM660_SLAVE_EBI, 356 SDM660_SLAVE_BIMC_SNOC 357 }; 358 359 static struct qcom_icc_node mas_mnoc_bimc = { 360 .name = "mas_mnoc_bimc", 361 .id = SDM660_MASTER_MNOC_BIMC, 362 .buswidth = 4, 363 .mas_rpm_id = 2, 364 .slv_rpm_id = -1, 365 .qos.ap_owned = true, 366 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 367 .qos.areq_prio = 0, 368 .qos.prio_level = 0, 369 .qos.qos_port = 2, 370 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links), 371 .links = mas_mnoc_bimc_links, 372 }; 373 374 static const u16 mas_snoc_bimc_links[] = { 375 SDM660_SLAVE_HMSS_L3, 376 SDM660_SLAVE_EBI 377 }; 378 379 static struct qcom_icc_node mas_snoc_bimc = { 380 .name = "mas_snoc_bimc", 381 .id = SDM660_MASTER_SNOC_BIMC, 382 .buswidth = 4, 383 .mas_rpm_id = 3, 384 .slv_rpm_id = -1, 385 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 386 .links = mas_snoc_bimc_links, 387 }; 388 389 static const u16 mas_pimem_links[] = { 390 SDM660_SLAVE_HMSS_L3, 391 SDM660_SLAVE_EBI 392 }; 393 394 static struct qcom_icc_node mas_pimem = { 395 .name = "mas_pimem", 396 .id = SDM660_MASTER_PIMEM, 397 .buswidth = 4, 398 .mas_rpm_id = 113, 399 .slv_rpm_id = -1, 400 .qos.ap_owned = true, 401 .qos.qos_mode = NOC_QOS_MODE_FIXED, 402 .qos.areq_prio = 1, 403 .qos.prio_level = 1, 404 .qos.qos_port = 4, 405 .num_links = ARRAY_SIZE(mas_pimem_links), 406 .links = mas_pimem_links, 407 }; 408 409 static const u16 mas_snoc_cnoc_links[] = { 410 SDM660_SLAVE_CLK_CTL, 411 SDM660_SLAVE_QDSS_CFG, 412 SDM660_SLAVE_QM_CFG, 413 SDM660_SLAVE_SRVC_CNOC, 414 SDM660_SLAVE_UFS_CFG, 415 SDM660_SLAVE_TCSR, 416 SDM660_SLAVE_A2NOC_SMMU_CFG, 417 SDM660_SLAVE_SNOC_CFG, 418 SDM660_SLAVE_TLMM_SOUTH, 419 SDM660_SLAVE_MPM, 420 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 421 SDM660_SLAVE_SDCC_2, 422 SDM660_SLAVE_SDCC_1, 423 SDM660_SLAVE_SPDM, 424 SDM660_SLAVE_PMIC_ARB, 425 SDM660_SLAVE_PRNG, 426 SDM660_SLAVE_MSS_CFG, 427 SDM660_SLAVE_GPUSS_CFG, 428 SDM660_SLAVE_IMEM_CFG, 429 SDM660_SLAVE_USB3_0, 430 SDM660_SLAVE_A2NOC_CFG, 431 SDM660_SLAVE_TLMM_NORTH, 432 SDM660_SLAVE_USB_HS, 433 SDM660_SLAVE_PDM, 434 SDM660_SLAVE_TLMM_CENTER, 435 SDM660_SLAVE_AHB2PHY, 436 SDM660_SLAVE_BLSP_2, 437 SDM660_SLAVE_BLSP_1, 438 SDM660_SLAVE_PIMEM_CFG, 439 SDM660_SLAVE_GLM, 440 SDM660_SLAVE_MESSAGE_RAM, 441 SDM660_SLAVE_BIMC_CFG, 442 SDM660_SLAVE_CNOC_MNOC_CFG 443 }; 444 445 static struct qcom_icc_node mas_snoc_cnoc = { 446 .name = "mas_snoc_cnoc", 447 .id = SDM660_MASTER_SNOC_CNOC, 448 .buswidth = 8, 449 .mas_rpm_id = 52, 450 .slv_rpm_id = -1, 451 .qos.ap_owned = true, 452 .qos.qos_mode = NOC_QOS_MODE_INVALID, 453 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 454 .links = mas_snoc_cnoc_links, 455 }; 456 457 static const u16 mas_qdss_dap_links[] = { 458 SDM660_SLAVE_CLK_CTL, 459 SDM660_SLAVE_QDSS_CFG, 460 SDM660_SLAVE_QM_CFG, 461 SDM660_SLAVE_SRVC_CNOC, 462 SDM660_SLAVE_UFS_CFG, 463 SDM660_SLAVE_TCSR, 464 SDM660_SLAVE_A2NOC_SMMU_CFG, 465 SDM660_SLAVE_SNOC_CFG, 466 SDM660_SLAVE_TLMM_SOUTH, 467 SDM660_SLAVE_MPM, 468 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 469 SDM660_SLAVE_SDCC_2, 470 SDM660_SLAVE_SDCC_1, 471 SDM660_SLAVE_SPDM, 472 SDM660_SLAVE_PMIC_ARB, 473 SDM660_SLAVE_PRNG, 474 SDM660_SLAVE_MSS_CFG, 475 SDM660_SLAVE_GPUSS_CFG, 476 SDM660_SLAVE_IMEM_CFG, 477 SDM660_SLAVE_USB3_0, 478 SDM660_SLAVE_A2NOC_CFG, 479 SDM660_SLAVE_TLMM_NORTH, 480 SDM660_SLAVE_USB_HS, 481 SDM660_SLAVE_PDM, 482 SDM660_SLAVE_TLMM_CENTER, 483 SDM660_SLAVE_AHB2PHY, 484 SDM660_SLAVE_BLSP_2, 485 SDM660_SLAVE_BLSP_1, 486 SDM660_SLAVE_PIMEM_CFG, 487 SDM660_SLAVE_GLM, 488 SDM660_SLAVE_MESSAGE_RAM, 489 SDM660_SLAVE_CNOC_A2NOC, 490 SDM660_SLAVE_BIMC_CFG, 491 SDM660_SLAVE_CNOC_MNOC_CFG 492 }; 493 494 static struct qcom_icc_node mas_qdss_dap = { 495 .name = "mas_qdss_dap", 496 .id = SDM660_MASTER_QDSS_DAP, 497 .buswidth = 8, 498 .mas_rpm_id = 49, 499 .slv_rpm_id = -1, 500 .qos.ap_owned = true, 501 .qos.qos_mode = NOC_QOS_MODE_INVALID, 502 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 503 .links = mas_qdss_dap_links, 504 }; 505 506 static const u16 mas_apss_proc_links[] = { 507 SDM660_SLAVE_GNOC_SNOC, 508 SDM660_SLAVE_GNOC_BIMC 509 }; 510 511 static struct qcom_icc_node mas_apss_proc = { 512 .name = "mas_apss_proc", 513 .id = SDM660_MASTER_APPS_PROC, 514 .buswidth = 16, 515 .mas_rpm_id = 0, 516 .slv_rpm_id = -1, 517 .qos.ap_owned = true, 518 .qos.qos_mode = NOC_QOS_MODE_INVALID, 519 .num_links = ARRAY_SIZE(mas_apss_proc_links), 520 .links = mas_apss_proc_links, 521 }; 522 523 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { 524 SDM660_SLAVE_VENUS_THROTTLE_CFG, 525 SDM660_SLAVE_VENUS_CFG, 526 SDM660_SLAVE_CAMERA_THROTTLE_CFG, 527 SDM660_SLAVE_SMMU_CFG, 528 SDM660_SLAVE_CAMERA_CFG, 529 SDM660_SLAVE_CSI_PHY_CFG, 530 SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 531 SDM660_SLAVE_DISPLAY_CFG, 532 SDM660_SLAVE_MMSS_CLK_CFG, 533 SDM660_SLAVE_MNOC_MPU_CFG, 534 SDM660_SLAVE_MISC_CFG, 535 SDM660_SLAVE_MMSS_CLK_XPU_CFG 536 }; 537 538 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { 539 .name = "mas_cnoc_mnoc_mmss_cfg", 540 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 541 .buswidth = 8, 542 .mas_rpm_id = 4, 543 .slv_rpm_id = -1, 544 .qos.ap_owned = true, 545 .qos.qos_mode = NOC_QOS_MODE_INVALID, 546 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), 547 .links = mas_cnoc_mnoc_mmss_cfg_links, 548 }; 549 550 static const u16 mas_cnoc_mnoc_cfg_links[] = { 551 SDM660_SLAVE_SRVC_MNOC 552 }; 553 554 static struct qcom_icc_node mas_cnoc_mnoc_cfg = { 555 .name = "mas_cnoc_mnoc_cfg", 556 .id = SDM660_MASTER_CNOC_MNOC_CFG, 557 .buswidth = 4, 558 .mas_rpm_id = 5, 559 .slv_rpm_id = -1, 560 .qos.ap_owned = true, 561 .qos.qos_mode = NOC_QOS_MODE_INVALID, 562 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), 563 .links = mas_cnoc_mnoc_cfg_links, 564 }; 565 566 static const u16 mas_cpp_links[] = { 567 SDM660_SLAVE_MNOC_BIMC 568 }; 569 570 static struct qcom_icc_node mas_cpp = { 571 .name = "mas_cpp", 572 .id = SDM660_MASTER_CPP, 573 .buswidth = 16, 574 .mas_rpm_id = 115, 575 .slv_rpm_id = -1, 576 .qos.ap_owned = true, 577 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 578 .qos.areq_prio = 0, 579 .qos.prio_level = 0, 580 .qos.qos_port = 4, 581 .num_links = ARRAY_SIZE(mas_cpp_links), 582 .links = mas_cpp_links, 583 }; 584 585 static const u16 mas_jpeg_links[] = { 586 SDM660_SLAVE_MNOC_BIMC 587 }; 588 589 static struct qcom_icc_node mas_jpeg = { 590 .name = "mas_jpeg", 591 .id = SDM660_MASTER_JPEG, 592 .buswidth = 16, 593 .mas_rpm_id = 7, 594 .slv_rpm_id = -1, 595 .qos.ap_owned = true, 596 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 597 .qos.areq_prio = 0, 598 .qos.prio_level = 0, 599 .qos.qos_port = 6, 600 .num_links = ARRAY_SIZE(mas_jpeg_links), 601 .links = mas_jpeg_links, 602 }; 603 604 static const u16 mas_mdp_p0_links[] = { 605 SDM660_SLAVE_MNOC_BIMC 606 }; 607 608 static struct qcom_icc_node mas_mdp_p0 = { 609 .name = "mas_mdp_p0", 610 .id = SDM660_MASTER_MDP_P0, 611 .buswidth = 16, 612 .mas_rpm_id = 8, 613 .slv_rpm_id = -1, 614 .qos.ap_owned = true, 615 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 616 .qos.areq_prio = 0, 617 .qos.prio_level = 0, 618 .qos.qos_port = 0, 619 .num_links = ARRAY_SIZE(mas_mdp_p0_links), 620 .links = mas_mdp_p0_links, 621 }; 622 623 static const u16 mas_mdp_p1_links[] = { 624 SDM660_SLAVE_MNOC_BIMC 625 }; 626 627 static struct qcom_icc_node mas_mdp_p1 = { 628 .name = "mas_mdp_p1", 629 .id = SDM660_MASTER_MDP_P1, 630 .buswidth = 16, 631 .mas_rpm_id = 61, 632 .slv_rpm_id = -1, 633 .qos.ap_owned = true, 634 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 635 .qos.areq_prio = 0, 636 .qos.prio_level = 0, 637 .qos.qos_port = 1, 638 .num_links = ARRAY_SIZE(mas_mdp_p1_links), 639 .links = mas_mdp_p1_links, 640 }; 641 642 static const u16 mas_venus_links[] = { 643 SDM660_SLAVE_MNOC_BIMC 644 }; 645 646 static struct qcom_icc_node mas_venus = { 647 .name = "mas_venus", 648 .id = SDM660_MASTER_VENUS, 649 .buswidth = 16, 650 .mas_rpm_id = 9, 651 .slv_rpm_id = -1, 652 .qos.ap_owned = true, 653 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 654 .qos.areq_prio = 0, 655 .qos.prio_level = 0, 656 .qos.qos_port = 1, 657 .num_links = ARRAY_SIZE(mas_venus_links), 658 .links = mas_venus_links, 659 }; 660 661 static const u16 mas_vfe_links[] = { 662 SDM660_SLAVE_MNOC_BIMC 663 }; 664 665 static struct qcom_icc_node mas_vfe = { 666 .name = "mas_vfe", 667 .id = SDM660_MASTER_VFE, 668 .buswidth = 16, 669 .mas_rpm_id = 11, 670 .slv_rpm_id = -1, 671 .qos.ap_owned = true, 672 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 673 .qos.areq_prio = 0, 674 .qos.prio_level = 0, 675 .qos.qos_port = 5, 676 .num_links = ARRAY_SIZE(mas_vfe_links), 677 .links = mas_vfe_links, 678 }; 679 680 static const u16 mas_qdss_etr_links[] = { 681 SDM660_SLAVE_PIMEM, 682 SDM660_SLAVE_IMEM, 683 SDM660_SLAVE_SNOC_CNOC, 684 SDM660_SLAVE_SNOC_BIMC 685 }; 686 687 static struct qcom_icc_node mas_qdss_etr = { 688 .name = "mas_qdss_etr", 689 .id = SDM660_MASTER_QDSS_ETR, 690 .buswidth = 8, 691 .mas_rpm_id = 31, 692 .slv_rpm_id = -1, 693 .qos.ap_owned = true, 694 .qos.qos_mode = NOC_QOS_MODE_FIXED, 695 .qos.areq_prio = 1, 696 .qos.prio_level = 1, 697 .qos.qos_port = 1, 698 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 699 .links = mas_qdss_etr_links, 700 }; 701 702 static const u16 mas_qdss_bam_links[] = { 703 SDM660_SLAVE_PIMEM, 704 SDM660_SLAVE_IMEM, 705 SDM660_SLAVE_SNOC_CNOC, 706 SDM660_SLAVE_SNOC_BIMC 707 }; 708 709 static struct qcom_icc_node mas_qdss_bam = { 710 .name = "mas_qdss_bam", 711 .id = SDM660_MASTER_QDSS_BAM, 712 .buswidth = 4, 713 .mas_rpm_id = 19, 714 .slv_rpm_id = -1, 715 .qos.ap_owned = true, 716 .qos.qos_mode = NOC_QOS_MODE_FIXED, 717 .qos.areq_prio = 1, 718 .qos.prio_level = 1, 719 .qos.qos_port = 0, 720 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 721 .links = mas_qdss_bam_links, 722 }; 723 724 static const u16 mas_snoc_cfg_links[] = { 725 SDM660_SLAVE_SRVC_SNOC 726 }; 727 728 static struct qcom_icc_node mas_snoc_cfg = { 729 .name = "mas_snoc_cfg", 730 .id = SDM660_MASTER_SNOC_CFG, 731 .buswidth = 4, 732 .mas_rpm_id = 20, 733 .slv_rpm_id = -1, 734 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 735 .links = mas_snoc_cfg_links, 736 }; 737 738 static const u16 mas_bimc_snoc_links[] = { 739 SDM660_SLAVE_PIMEM, 740 SDM660_SLAVE_IPA, 741 SDM660_SLAVE_QDSS_STM, 742 SDM660_SLAVE_LPASS, 743 SDM660_SLAVE_HMSS, 744 SDM660_SLAVE_CDSP, 745 SDM660_SLAVE_SNOC_CNOC, 746 SDM660_SLAVE_WLAN, 747 SDM660_SLAVE_IMEM 748 }; 749 750 static struct qcom_icc_node mas_bimc_snoc = { 751 .name = "mas_bimc_snoc", 752 .id = SDM660_MASTER_BIMC_SNOC, 753 .buswidth = 8, 754 .mas_rpm_id = 21, 755 .slv_rpm_id = -1, 756 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 757 .links = mas_bimc_snoc_links, 758 }; 759 760 static const u16 mas_gnoc_snoc_links[] = { 761 SDM660_SLAVE_PIMEM, 762 SDM660_SLAVE_IPA, 763 SDM660_SLAVE_QDSS_STM, 764 SDM660_SLAVE_LPASS, 765 SDM660_SLAVE_HMSS, 766 SDM660_SLAVE_CDSP, 767 SDM660_SLAVE_SNOC_CNOC, 768 SDM660_SLAVE_WLAN, 769 SDM660_SLAVE_IMEM 770 }; 771 772 static struct qcom_icc_node mas_gnoc_snoc = { 773 .name = "mas_gnoc_snoc", 774 .id = SDM660_MASTER_GNOC_SNOC, 775 .buswidth = 8, 776 .mas_rpm_id = 150, 777 .slv_rpm_id = -1, 778 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links), 779 .links = mas_gnoc_snoc_links, 780 }; 781 782 static const u16 mas_a2noc_snoc_links[] = { 783 SDM660_SLAVE_PIMEM, 784 SDM660_SLAVE_IPA, 785 SDM660_SLAVE_QDSS_STM, 786 SDM660_SLAVE_LPASS, 787 SDM660_SLAVE_HMSS, 788 SDM660_SLAVE_SNOC_BIMC, 789 SDM660_SLAVE_CDSP, 790 SDM660_SLAVE_SNOC_CNOC, 791 SDM660_SLAVE_WLAN, 792 SDM660_SLAVE_IMEM 793 }; 794 795 static struct qcom_icc_node mas_a2noc_snoc = { 796 .name = "mas_a2noc_snoc", 797 .id = SDM660_MASTER_A2NOC_SNOC, 798 .buswidth = 16, 799 .mas_rpm_id = 112, 800 .slv_rpm_id = -1, 801 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), 802 .links = mas_a2noc_snoc_links, 803 }; 804 805 static const u16 slv_a2noc_snoc_links[] = { 806 SDM660_MASTER_A2NOC_SNOC 807 }; 808 809 static struct qcom_icc_node slv_a2noc_snoc = { 810 .name = "slv_a2noc_snoc", 811 .id = SDM660_SLAVE_A2NOC_SNOC, 812 .buswidth = 16, 813 .mas_rpm_id = -1, 814 .slv_rpm_id = 143, 815 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), 816 .links = slv_a2noc_snoc_links, 817 }; 818 819 static struct qcom_icc_node slv_ebi = { 820 .name = "slv_ebi", 821 .id = SDM660_SLAVE_EBI, 822 .buswidth = 4, 823 .mas_rpm_id = -1, 824 .slv_rpm_id = 0, 825 }; 826 827 static struct qcom_icc_node slv_hmss_l3 = { 828 .name = "slv_hmss_l3", 829 .id = SDM660_SLAVE_HMSS_L3, 830 .buswidth = 4, 831 .mas_rpm_id = -1, 832 .slv_rpm_id = 160, 833 }; 834 835 static const u16 slv_bimc_snoc_links[] = { 836 SDM660_MASTER_BIMC_SNOC 837 }; 838 839 static struct qcom_icc_node slv_bimc_snoc = { 840 .name = "slv_bimc_snoc", 841 .id = SDM660_SLAVE_BIMC_SNOC, 842 .buswidth = 4, 843 .mas_rpm_id = -1, 844 .slv_rpm_id = 2, 845 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 846 .links = slv_bimc_snoc_links, 847 }; 848 849 static const u16 slv_cnoc_a2noc_links[] = { 850 SDM660_MASTER_CNOC_A2NOC 851 }; 852 853 static struct qcom_icc_node slv_cnoc_a2noc = { 854 .name = "slv_cnoc_a2noc", 855 .id = SDM660_SLAVE_CNOC_A2NOC, 856 .buswidth = 8, 857 .mas_rpm_id = -1, 858 .slv_rpm_id = 208, 859 .qos.ap_owned = true, 860 .qos.qos_mode = NOC_QOS_MODE_INVALID, 861 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links), 862 .links = slv_cnoc_a2noc_links, 863 }; 864 865 static struct qcom_icc_node slv_mpm = { 866 .name = "slv_mpm", 867 .id = SDM660_SLAVE_MPM, 868 .buswidth = 4, 869 .mas_rpm_id = -1, 870 .slv_rpm_id = 62, 871 .qos.ap_owned = true, 872 .qos.qos_mode = NOC_QOS_MODE_INVALID, 873 }; 874 875 static struct qcom_icc_node slv_pmic_arb = { 876 .name = "slv_pmic_arb", 877 .id = SDM660_SLAVE_PMIC_ARB, 878 .buswidth = 4, 879 .mas_rpm_id = -1, 880 .slv_rpm_id = 59, 881 .qos.ap_owned = true, 882 .qos.qos_mode = NOC_QOS_MODE_INVALID, 883 }; 884 885 static struct qcom_icc_node slv_tlmm_north = { 886 .name = "slv_tlmm_north", 887 .id = SDM660_SLAVE_TLMM_NORTH, 888 .buswidth = 8, 889 .mas_rpm_id = -1, 890 .slv_rpm_id = 214, 891 .qos.ap_owned = true, 892 .qos.qos_mode = NOC_QOS_MODE_INVALID, 893 }; 894 895 static struct qcom_icc_node slv_tcsr = { 896 .name = "slv_tcsr", 897 .id = SDM660_SLAVE_TCSR, 898 .buswidth = 4, 899 .mas_rpm_id = -1, 900 .slv_rpm_id = 50, 901 .qos.ap_owned = true, 902 .qos.qos_mode = NOC_QOS_MODE_INVALID, 903 }; 904 905 static struct qcom_icc_node slv_pimem_cfg = { 906 .name = "slv_pimem_cfg", 907 .id = SDM660_SLAVE_PIMEM_CFG, 908 .buswidth = 4, 909 .mas_rpm_id = -1, 910 .slv_rpm_id = 167, 911 .qos.ap_owned = true, 912 .qos.qos_mode = NOC_QOS_MODE_INVALID, 913 }; 914 915 static struct qcom_icc_node slv_imem_cfg = { 916 .name = "slv_imem_cfg", 917 .id = SDM660_SLAVE_IMEM_CFG, 918 .buswidth = 4, 919 .mas_rpm_id = -1, 920 .slv_rpm_id = 54, 921 .qos.ap_owned = true, 922 .qos.qos_mode = NOC_QOS_MODE_INVALID, 923 }; 924 925 static struct qcom_icc_node slv_message_ram = { 926 .name = "slv_message_ram", 927 .id = SDM660_SLAVE_MESSAGE_RAM, 928 .buswidth = 4, 929 .mas_rpm_id = -1, 930 .slv_rpm_id = 55, 931 .qos.ap_owned = true, 932 .qos.qos_mode = NOC_QOS_MODE_INVALID, 933 }; 934 935 static struct qcom_icc_node slv_glm = { 936 .name = "slv_glm", 937 .id = SDM660_SLAVE_GLM, 938 .buswidth = 4, 939 .mas_rpm_id = -1, 940 .slv_rpm_id = 209, 941 .qos.ap_owned = true, 942 .qos.qos_mode = NOC_QOS_MODE_INVALID, 943 }; 944 945 static struct qcom_icc_node slv_bimc_cfg = { 946 .name = "slv_bimc_cfg", 947 .id = SDM660_SLAVE_BIMC_CFG, 948 .buswidth = 4, 949 .mas_rpm_id = -1, 950 .slv_rpm_id = 56, 951 .qos.ap_owned = true, 952 .qos.qos_mode = NOC_QOS_MODE_INVALID, 953 }; 954 955 static struct qcom_icc_node slv_prng = { 956 .name = "slv_prng", 957 .id = SDM660_SLAVE_PRNG, 958 .buswidth = 4, 959 .mas_rpm_id = -1, 960 .slv_rpm_id = 44, 961 .qos.ap_owned = true, 962 .qos.qos_mode = NOC_QOS_MODE_INVALID, 963 }; 964 965 static struct qcom_icc_node slv_spdm = { 966 .name = "slv_spdm", 967 .id = SDM660_SLAVE_SPDM, 968 .buswidth = 4, 969 .mas_rpm_id = -1, 970 .slv_rpm_id = 60, 971 .qos.ap_owned = true, 972 .qos.qos_mode = NOC_QOS_MODE_INVALID, 973 }; 974 975 static struct qcom_icc_node slv_qdss_cfg = { 976 .name = "slv_qdss_cfg", 977 .id = SDM660_SLAVE_QDSS_CFG, 978 .buswidth = 4, 979 .mas_rpm_id = -1, 980 .slv_rpm_id = 63, 981 .qos.ap_owned = true, 982 .qos.qos_mode = NOC_QOS_MODE_INVALID, 983 }; 984 985 static const u16 slv_cnoc_mnoc_cfg_links[] = { 986 SDM660_MASTER_CNOC_MNOC_CFG 987 }; 988 989 static struct qcom_icc_node slv_cnoc_mnoc_cfg = { 990 .name = "slv_cnoc_mnoc_cfg", 991 .id = SDM660_SLAVE_CNOC_MNOC_CFG, 992 .buswidth = 4, 993 .mas_rpm_id = -1, 994 .slv_rpm_id = 66, 995 .qos.ap_owned = true, 996 .qos.qos_mode = NOC_QOS_MODE_INVALID, 997 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), 998 .links = slv_cnoc_mnoc_cfg_links, 999 }; 1000 1001 static struct qcom_icc_node slv_snoc_cfg = { 1002 .name = "slv_snoc_cfg", 1003 .id = SDM660_SLAVE_SNOC_CFG, 1004 .buswidth = 4, 1005 .mas_rpm_id = -1, 1006 .slv_rpm_id = 70, 1007 .qos.ap_owned = true, 1008 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1009 }; 1010 1011 static struct qcom_icc_node slv_qm_cfg = { 1012 .name = "slv_qm_cfg", 1013 .id = SDM660_SLAVE_QM_CFG, 1014 .buswidth = 4, 1015 .mas_rpm_id = -1, 1016 .slv_rpm_id = 212, 1017 .qos.ap_owned = true, 1018 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1019 }; 1020 1021 static struct qcom_icc_node slv_clk_ctl = { 1022 .name = "slv_clk_ctl", 1023 .id = SDM660_SLAVE_CLK_CTL, 1024 .buswidth = 4, 1025 .mas_rpm_id = -1, 1026 .slv_rpm_id = 47, 1027 .qos.ap_owned = true, 1028 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1029 }; 1030 1031 static struct qcom_icc_node slv_mss_cfg = { 1032 .name = "slv_mss_cfg", 1033 .id = SDM660_SLAVE_MSS_CFG, 1034 .buswidth = 4, 1035 .mas_rpm_id = -1, 1036 .slv_rpm_id = 48, 1037 .qos.ap_owned = true, 1038 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1039 }; 1040 1041 static struct qcom_icc_node slv_tlmm_south = { 1042 .name = "slv_tlmm_south", 1043 .id = SDM660_SLAVE_TLMM_SOUTH, 1044 .buswidth = 4, 1045 .mas_rpm_id = -1, 1046 .slv_rpm_id = 217, 1047 .qos.ap_owned = true, 1048 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1049 }; 1050 1051 static struct qcom_icc_node slv_ufs_cfg = { 1052 .name = "slv_ufs_cfg", 1053 .id = SDM660_SLAVE_UFS_CFG, 1054 .buswidth = 4, 1055 .mas_rpm_id = -1, 1056 .slv_rpm_id = 92, 1057 .qos.ap_owned = true, 1058 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1059 }; 1060 1061 static struct qcom_icc_node slv_a2noc_cfg = { 1062 .name = "slv_a2noc_cfg", 1063 .id = SDM660_SLAVE_A2NOC_CFG, 1064 .buswidth = 4, 1065 .mas_rpm_id = -1, 1066 .slv_rpm_id = 150, 1067 .qos.ap_owned = true, 1068 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1069 }; 1070 1071 static struct qcom_icc_node slv_a2noc_smmu_cfg = { 1072 .name = "slv_a2noc_smmu_cfg", 1073 .id = SDM660_SLAVE_A2NOC_SMMU_CFG, 1074 .buswidth = 8, 1075 .mas_rpm_id = -1, 1076 .slv_rpm_id = 152, 1077 .qos.ap_owned = true, 1078 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1079 }; 1080 1081 static struct qcom_icc_node slv_gpuss_cfg = { 1082 .name = "slv_gpuss_cfg", 1083 .id = SDM660_SLAVE_GPUSS_CFG, 1084 .buswidth = 8, 1085 .mas_rpm_id = -1, 1086 .slv_rpm_id = 11, 1087 .qos.ap_owned = true, 1088 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1089 }; 1090 1091 static struct qcom_icc_node slv_ahb2phy = { 1092 .name = "slv_ahb2phy", 1093 .id = SDM660_SLAVE_AHB2PHY, 1094 .buswidth = 4, 1095 .mas_rpm_id = -1, 1096 .slv_rpm_id = 163, 1097 .qos.ap_owned = true, 1098 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1099 }; 1100 1101 static struct qcom_icc_node slv_blsp_1 = { 1102 .name = "slv_blsp_1", 1103 .id = SDM660_SLAVE_BLSP_1, 1104 .buswidth = 4, 1105 .mas_rpm_id = -1, 1106 .slv_rpm_id = 39, 1107 .qos.ap_owned = true, 1108 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1109 }; 1110 1111 static struct qcom_icc_node slv_sdcc_1 = { 1112 .name = "slv_sdcc_1", 1113 .id = SDM660_SLAVE_SDCC_1, 1114 .buswidth = 4, 1115 .mas_rpm_id = -1, 1116 .slv_rpm_id = 31, 1117 .qos.ap_owned = true, 1118 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1119 }; 1120 1121 static struct qcom_icc_node slv_sdcc_2 = { 1122 .name = "slv_sdcc_2", 1123 .id = SDM660_SLAVE_SDCC_2, 1124 .buswidth = 4, 1125 .mas_rpm_id = -1, 1126 .slv_rpm_id = 33, 1127 .qos.ap_owned = true, 1128 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1129 }; 1130 1131 static struct qcom_icc_node slv_tlmm_center = { 1132 .name = "slv_tlmm_center", 1133 .id = SDM660_SLAVE_TLMM_CENTER, 1134 .buswidth = 4, 1135 .mas_rpm_id = -1, 1136 .slv_rpm_id = 218, 1137 .qos.ap_owned = true, 1138 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1139 }; 1140 1141 static struct qcom_icc_node slv_blsp_2 = { 1142 .name = "slv_blsp_2", 1143 .id = SDM660_SLAVE_BLSP_2, 1144 .buswidth = 4, 1145 .mas_rpm_id = -1, 1146 .slv_rpm_id = 37, 1147 .qos.ap_owned = true, 1148 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1149 }; 1150 1151 static struct qcom_icc_node slv_pdm = { 1152 .name = "slv_pdm", 1153 .id = SDM660_SLAVE_PDM, 1154 .buswidth = 4, 1155 .mas_rpm_id = -1, 1156 .slv_rpm_id = 41, 1157 .qos.ap_owned = true, 1158 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1159 }; 1160 1161 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { 1162 SDM660_MASTER_CNOC_MNOC_MMSS_CFG 1163 }; 1164 1165 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { 1166 .name = "slv_cnoc_mnoc_mmss_cfg", 1167 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 1168 .buswidth = 8, 1169 .mas_rpm_id = -1, 1170 .slv_rpm_id = 58, 1171 .qos.ap_owned = true, 1172 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1173 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), 1174 .links = slv_cnoc_mnoc_mmss_cfg_links, 1175 }; 1176 1177 static struct qcom_icc_node slv_usb_hs = { 1178 .name = "slv_usb_hs", 1179 .id = SDM660_SLAVE_USB_HS, 1180 .buswidth = 4, 1181 .mas_rpm_id = -1, 1182 .slv_rpm_id = 40, 1183 .qos.ap_owned = true, 1184 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1185 }; 1186 1187 static struct qcom_icc_node slv_usb3_0 = { 1188 .name = "slv_usb3_0", 1189 .id = SDM660_SLAVE_USB3_0, 1190 .buswidth = 4, 1191 .mas_rpm_id = -1, 1192 .slv_rpm_id = 22, 1193 .qos.ap_owned = true, 1194 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1195 }; 1196 1197 static struct qcom_icc_node slv_srvc_cnoc = { 1198 .name = "slv_srvc_cnoc", 1199 .id = SDM660_SLAVE_SRVC_CNOC, 1200 .buswidth = 4, 1201 .mas_rpm_id = -1, 1202 .slv_rpm_id = 76, 1203 .qos.ap_owned = true, 1204 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1205 }; 1206 1207 static const u16 slv_gnoc_bimc_links[] = { 1208 SDM660_MASTER_GNOC_BIMC 1209 }; 1210 1211 static struct qcom_icc_node slv_gnoc_bimc = { 1212 .name = "slv_gnoc_bimc", 1213 .id = SDM660_SLAVE_GNOC_BIMC, 1214 .buswidth = 16, 1215 .mas_rpm_id = -1, 1216 .slv_rpm_id = 210, 1217 .qos.ap_owned = true, 1218 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1219 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links), 1220 .links = slv_gnoc_bimc_links, 1221 }; 1222 1223 static const u16 slv_gnoc_snoc_links[] = { 1224 SDM660_MASTER_GNOC_SNOC 1225 }; 1226 1227 static struct qcom_icc_node slv_gnoc_snoc = { 1228 .name = "slv_gnoc_snoc", 1229 .id = SDM660_SLAVE_GNOC_SNOC, 1230 .buswidth = 8, 1231 .mas_rpm_id = -1, 1232 .slv_rpm_id = 211, 1233 .qos.ap_owned = true, 1234 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1235 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links), 1236 .links = slv_gnoc_snoc_links, 1237 }; 1238 1239 static struct qcom_icc_node slv_camera_cfg = { 1240 .name = "slv_camera_cfg", 1241 .id = SDM660_SLAVE_CAMERA_CFG, 1242 .buswidth = 4, 1243 .mas_rpm_id = -1, 1244 .slv_rpm_id = 3, 1245 .qos.ap_owned = true, 1246 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1247 }; 1248 1249 static struct qcom_icc_node slv_camera_throttle_cfg = { 1250 .name = "slv_camera_throttle_cfg", 1251 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG, 1252 .buswidth = 4, 1253 .mas_rpm_id = -1, 1254 .slv_rpm_id = 154, 1255 .qos.ap_owned = true, 1256 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1257 }; 1258 1259 static struct qcom_icc_node slv_misc_cfg = { 1260 .name = "slv_misc_cfg", 1261 .id = SDM660_SLAVE_MISC_CFG, 1262 .buswidth = 4, 1263 .mas_rpm_id = -1, 1264 .slv_rpm_id = 8, 1265 .qos.ap_owned = true, 1266 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1267 }; 1268 1269 static struct qcom_icc_node slv_venus_throttle_cfg = { 1270 .name = "slv_venus_throttle_cfg", 1271 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG, 1272 .buswidth = 4, 1273 .mas_rpm_id = -1, 1274 .slv_rpm_id = 178, 1275 .qos.ap_owned = true, 1276 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1277 }; 1278 1279 static struct qcom_icc_node slv_venus_cfg = { 1280 .name = "slv_venus_cfg", 1281 .id = SDM660_SLAVE_VENUS_CFG, 1282 .buswidth = 4, 1283 .mas_rpm_id = -1, 1284 .slv_rpm_id = 10, 1285 .qos.ap_owned = true, 1286 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1287 }; 1288 1289 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = { 1290 .name = "slv_mmss_clk_xpu_cfg", 1291 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG, 1292 .buswidth = 4, 1293 .mas_rpm_id = -1, 1294 .slv_rpm_id = 13, 1295 .qos.ap_owned = true, 1296 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1297 }; 1298 1299 static struct qcom_icc_node slv_mmss_clk_cfg = { 1300 .name = "slv_mmss_clk_cfg", 1301 .id = SDM660_SLAVE_MMSS_CLK_CFG, 1302 .buswidth = 4, 1303 .mas_rpm_id = -1, 1304 .slv_rpm_id = 12, 1305 .qos.ap_owned = true, 1306 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1307 }; 1308 1309 static struct qcom_icc_node slv_mnoc_mpu_cfg = { 1310 .name = "slv_mnoc_mpu_cfg", 1311 .id = SDM660_SLAVE_MNOC_MPU_CFG, 1312 .buswidth = 4, 1313 .mas_rpm_id = -1, 1314 .slv_rpm_id = 14, 1315 .qos.ap_owned = true, 1316 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1317 }; 1318 1319 static struct qcom_icc_node slv_display_cfg = { 1320 .name = "slv_display_cfg", 1321 .id = SDM660_SLAVE_DISPLAY_CFG, 1322 .buswidth = 4, 1323 .mas_rpm_id = -1, 1324 .slv_rpm_id = 4, 1325 .qos.ap_owned = true, 1326 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1327 }; 1328 1329 static struct qcom_icc_node slv_csi_phy_cfg = { 1330 .name = "slv_csi_phy_cfg", 1331 .id = SDM660_SLAVE_CSI_PHY_CFG, 1332 .buswidth = 4, 1333 .mas_rpm_id = -1, 1334 .slv_rpm_id = 224, 1335 .qos.ap_owned = true, 1336 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1337 }; 1338 1339 static struct qcom_icc_node slv_display_throttle_cfg = { 1340 .name = "slv_display_throttle_cfg", 1341 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 1342 .buswidth = 4, 1343 .mas_rpm_id = -1, 1344 .slv_rpm_id = 156, 1345 .qos.ap_owned = true, 1346 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1347 }; 1348 1349 static struct qcom_icc_node slv_smmu_cfg = { 1350 .name = "slv_smmu_cfg", 1351 .id = SDM660_SLAVE_SMMU_CFG, 1352 .buswidth = 8, 1353 .mas_rpm_id = -1, 1354 .slv_rpm_id = 205, 1355 .qos.ap_owned = true, 1356 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1357 }; 1358 1359 static const u16 slv_mnoc_bimc_links[] = { 1360 SDM660_MASTER_MNOC_BIMC 1361 }; 1362 1363 static struct qcom_icc_node slv_mnoc_bimc = { 1364 .name = "slv_mnoc_bimc", 1365 .id = SDM660_SLAVE_MNOC_BIMC, 1366 .buswidth = 16, 1367 .mas_rpm_id = -1, 1368 .slv_rpm_id = 16, 1369 .qos.ap_owned = true, 1370 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1371 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), 1372 .links = slv_mnoc_bimc_links, 1373 }; 1374 1375 static struct qcom_icc_node slv_srvc_mnoc = { 1376 .name = "slv_srvc_mnoc", 1377 .id = SDM660_SLAVE_SRVC_MNOC, 1378 .buswidth = 8, 1379 .mas_rpm_id = -1, 1380 .slv_rpm_id = 17, 1381 .qos.ap_owned = true, 1382 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1383 }; 1384 1385 static struct qcom_icc_node slv_hmss = { 1386 .name = "slv_hmss", 1387 .id = SDM660_SLAVE_HMSS, 1388 .buswidth = 8, 1389 .mas_rpm_id = -1, 1390 .slv_rpm_id = 20, 1391 .qos.ap_owned = true, 1392 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1393 }; 1394 1395 static struct qcom_icc_node slv_lpass = { 1396 .name = "slv_lpass", 1397 .id = SDM660_SLAVE_LPASS, 1398 .buswidth = 4, 1399 .mas_rpm_id = -1, 1400 .slv_rpm_id = 21, 1401 .qos.ap_owned = true, 1402 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1403 }; 1404 1405 static struct qcom_icc_node slv_wlan = { 1406 .name = "slv_wlan", 1407 .id = SDM660_SLAVE_WLAN, 1408 .buswidth = 4, 1409 .mas_rpm_id = -1, 1410 .slv_rpm_id = 206, 1411 }; 1412 1413 static struct qcom_icc_node slv_cdsp = { 1414 .name = "slv_cdsp", 1415 .id = SDM660_SLAVE_CDSP, 1416 .buswidth = 4, 1417 .mas_rpm_id = -1, 1418 .slv_rpm_id = 221, 1419 .qos.ap_owned = true, 1420 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1421 }; 1422 1423 static struct qcom_icc_node slv_ipa = { 1424 .name = "slv_ipa", 1425 .id = SDM660_SLAVE_IPA, 1426 .buswidth = 4, 1427 .mas_rpm_id = -1, 1428 .slv_rpm_id = 183, 1429 .qos.ap_owned = true, 1430 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1431 }; 1432 1433 static const u16 slv_snoc_bimc_links[] = { 1434 SDM660_MASTER_SNOC_BIMC 1435 }; 1436 1437 static struct qcom_icc_node slv_snoc_bimc = { 1438 .name = "slv_snoc_bimc", 1439 .id = SDM660_SLAVE_SNOC_BIMC, 1440 .buswidth = 16, 1441 .mas_rpm_id = -1, 1442 .slv_rpm_id = 24, 1443 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1444 .links = slv_snoc_bimc_links, 1445 }; 1446 1447 static const u16 slv_snoc_cnoc_links[] = { 1448 SDM660_MASTER_SNOC_CNOC 1449 }; 1450 1451 static struct qcom_icc_node slv_snoc_cnoc = { 1452 .name = "slv_snoc_cnoc", 1453 .id = SDM660_SLAVE_SNOC_CNOC, 1454 .buswidth = 8, 1455 .mas_rpm_id = -1, 1456 .slv_rpm_id = 25, 1457 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1458 .links = slv_snoc_cnoc_links, 1459 }; 1460 1461 static struct qcom_icc_node slv_imem = { 1462 .name = "slv_imem", 1463 .id = SDM660_SLAVE_IMEM, 1464 .buswidth = 8, 1465 .mas_rpm_id = -1, 1466 .slv_rpm_id = 26, 1467 }; 1468 1469 static struct qcom_icc_node slv_pimem = { 1470 .name = "slv_pimem", 1471 .id = SDM660_SLAVE_PIMEM, 1472 .buswidth = 8, 1473 .mas_rpm_id = -1, 1474 .slv_rpm_id = 166, 1475 }; 1476 1477 static struct qcom_icc_node slv_qdss_stm = { 1478 .name = "slv_qdss_stm", 1479 .id = SDM660_SLAVE_QDSS_STM, 1480 .buswidth = 4, 1481 .mas_rpm_id = -1, 1482 .slv_rpm_id = 30, 1483 }; 1484 1485 static struct qcom_icc_node slv_srvc_snoc = { 1486 .name = "slv_srvc_snoc", 1487 .id = SDM660_SLAVE_SRVC_SNOC, 1488 .buswidth = 16, 1489 .mas_rpm_id = -1, 1490 .slv_rpm_id = 29, 1491 }; 1492 1493 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = { 1494 [MASTER_IPA] = &mas_ipa, 1495 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc, 1496 [MASTER_SDCC_1] = &mas_sdcc_1, 1497 [MASTER_SDCC_2] = &mas_sdcc_2, 1498 [MASTER_BLSP_1] = &mas_blsp_1, 1499 [MASTER_BLSP_2] = &mas_blsp_2, 1500 [MASTER_UFS] = &mas_ufs, 1501 [MASTER_USB_HS] = &mas_usb_hs, 1502 [MASTER_USB3] = &mas_usb3, 1503 [MASTER_CRYPTO_C0] = &mas_crypto, 1504 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, 1505 }; 1506 1507 static const struct regmap_config sdm660_a2noc_regmap_config = { 1508 .reg_bits = 32, 1509 .reg_stride = 4, 1510 .val_bits = 32, 1511 .max_register = 0x20000, 1512 .fast_io = true, 1513 }; 1514 1515 static const struct qcom_icc_desc sdm660_a2noc = { 1516 .type = QCOM_ICC_NOC, 1517 .nodes = sdm660_a2noc_nodes, 1518 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), 1519 .clocks = bus_a2noc_clocks, 1520 .num_clocks = ARRAY_SIZE(bus_a2noc_clocks), 1521 .regmap_cfg = &sdm660_a2noc_regmap_config, 1522 }; 1523 1524 static struct qcom_icc_node * const sdm660_bimc_nodes[] = { 1525 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc, 1526 [MASTER_OXILI] = &mas_oxili, 1527 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, 1528 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1529 [MASTER_PIMEM] = &mas_pimem, 1530 [SLAVE_EBI] = &slv_ebi, 1531 [SLAVE_HMSS_L3] = &slv_hmss_l3, 1532 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1533 }; 1534 1535 static const struct regmap_config sdm660_bimc_regmap_config = { 1536 .reg_bits = 32, 1537 .reg_stride = 4, 1538 .val_bits = 32, 1539 .max_register = 0x80000, 1540 .fast_io = true, 1541 }; 1542 1543 static const struct qcom_icc_desc sdm660_bimc = { 1544 .type = QCOM_ICC_BIMC, 1545 .nodes = sdm660_bimc_nodes, 1546 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), 1547 .regmap_cfg = &sdm660_bimc_regmap_config, 1548 }; 1549 1550 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { 1551 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1552 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1553 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc, 1554 [SLAVE_MPM] = &slv_mpm, 1555 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1556 [SLAVE_TLMM_NORTH] = &slv_tlmm_north, 1557 [SLAVE_TCSR] = &slv_tcsr, 1558 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1559 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1560 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1561 [SLAVE_GLM] = &slv_glm, 1562 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1563 [SLAVE_PRNG] = &slv_prng, 1564 [SLAVE_SPDM] = &slv_spdm, 1565 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1566 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, 1567 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1568 [SLAVE_QM_CFG] = &slv_qm_cfg, 1569 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1570 [SLAVE_MSS_CFG] = &slv_mss_cfg, 1571 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south, 1572 [SLAVE_UFS_CFG] = &slv_ufs_cfg, 1573 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, 1574 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, 1575 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg, 1576 [SLAVE_AHB2PHY] = &slv_ahb2phy, 1577 [SLAVE_BLSP_1] = &slv_blsp_1, 1578 [SLAVE_SDCC_1] = &slv_sdcc_1, 1579 [SLAVE_SDCC_2] = &slv_sdcc_2, 1580 [SLAVE_TLMM_CENTER] = &slv_tlmm_center, 1581 [SLAVE_BLSP_2] = &slv_blsp_2, 1582 [SLAVE_PDM] = &slv_pdm, 1583 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, 1584 [SLAVE_USB_HS] = &slv_usb_hs, 1585 [SLAVE_USB3_0] = &slv_usb3_0, 1586 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc, 1587 }; 1588 1589 static const struct regmap_config sdm660_cnoc_regmap_config = { 1590 .reg_bits = 32, 1591 .reg_stride = 4, 1592 .val_bits = 32, 1593 .max_register = 0x10000, 1594 .fast_io = true, 1595 }; 1596 1597 static const struct qcom_icc_desc sdm660_cnoc = { 1598 .type = QCOM_ICC_NOC, 1599 .nodes = sdm660_cnoc_nodes, 1600 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), 1601 .regmap_cfg = &sdm660_cnoc_regmap_config, 1602 }; 1603 1604 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = { 1605 [MASTER_APSS_PROC] = &mas_apss_proc, 1606 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc, 1607 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc, 1608 }; 1609 1610 static const struct regmap_config sdm660_gnoc_regmap_config = { 1611 .reg_bits = 32, 1612 .reg_stride = 4, 1613 .val_bits = 32, 1614 .max_register = 0xe000, 1615 .fast_io = true, 1616 }; 1617 1618 static const struct qcom_icc_desc sdm660_gnoc = { 1619 .type = QCOM_ICC_NOC, 1620 .nodes = sdm660_gnoc_nodes, 1621 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes), 1622 .regmap_cfg = &sdm660_gnoc_regmap_config, 1623 }; 1624 1625 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = { 1626 [MASTER_CPP] = &mas_cpp, 1627 [MASTER_JPEG] = &mas_jpeg, 1628 [MASTER_MDP_P0] = &mas_mdp_p0, 1629 [MASTER_MDP_P1] = &mas_mdp_p1, 1630 [MASTER_VENUS] = &mas_venus, 1631 [MASTER_VFE] = &mas_vfe, 1632 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, 1633 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, 1634 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1635 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, 1636 [SLAVE_MISC_CFG] = &slv_misc_cfg, 1637 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1638 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1639 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, 1640 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, 1641 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, 1642 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1643 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg, 1644 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1645 [SLAVE_SMMU_CFG] = &slv_smmu_cfg, 1646 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc, 1647 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, 1648 }; 1649 1650 static const struct regmap_config sdm660_mnoc_regmap_config = { 1651 .reg_bits = 32, 1652 .reg_stride = 4, 1653 .val_bits = 32, 1654 .max_register = 0x10000, 1655 .fast_io = true, 1656 }; 1657 1658 static const struct qcom_icc_desc sdm660_mnoc = { 1659 .type = QCOM_ICC_NOC, 1660 .nodes = sdm660_mnoc_nodes, 1661 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), 1662 .clocks = bus_mm_clocks, 1663 .num_clocks = ARRAY_SIZE(bus_mm_clocks), 1664 .regmap_cfg = &sdm660_mnoc_regmap_config, 1665 }; 1666 1667 static struct qcom_icc_node * const sdm660_snoc_nodes[] = { 1668 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1669 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1670 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1671 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1672 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, 1673 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc, 1674 [SLAVE_HMSS] = &slv_hmss, 1675 [SLAVE_LPASS] = &slv_lpass, 1676 [SLAVE_WLAN] = &slv_wlan, 1677 [SLAVE_CDSP] = &slv_cdsp, 1678 [SLAVE_IPA] = &slv_ipa, 1679 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1680 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1681 [SLAVE_IMEM] = &slv_imem, 1682 [SLAVE_PIMEM] = &slv_pimem, 1683 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1684 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, 1685 }; 1686 1687 static const struct regmap_config sdm660_snoc_regmap_config = { 1688 .reg_bits = 32, 1689 .reg_stride = 4, 1690 .val_bits = 32, 1691 .max_register = 0x20000, 1692 .fast_io = true, 1693 }; 1694 1695 static const struct qcom_icc_desc sdm660_snoc = { 1696 .type = QCOM_ICC_NOC, 1697 .nodes = sdm660_snoc_nodes, 1698 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), 1699 .regmap_cfg = &sdm660_snoc_regmap_config, 1700 }; 1701 1702 static const struct of_device_id sdm660_noc_of_match[] = { 1703 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc }, 1704 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc }, 1705 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc }, 1706 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc }, 1707 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc }, 1708 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc }, 1709 { }, 1710 }; 1711 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match); 1712 1713 static struct platform_driver sdm660_noc_driver = { 1714 .probe = qnoc_probe, 1715 .remove = qnoc_remove, 1716 .driver = { 1717 .name = "qnoc-sdm660", 1718 .of_match_table = sdm660_noc_of_match, 1719 }, 1720 }; 1721 module_platform_driver(sdm660_noc_driver); 1722 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver"); 1723 MODULE_LICENSE("GPL v2"); 1724