1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,nord-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qup0_core_slave = { 18 .name = "qup0_core_slave", 19 .channels = 1, 20 .buswidth = 4, 21 }; 22 23 static struct qcom_icc_node qup1_core_slave = { 24 .name = "qup1_core_slave", 25 .channels = 1, 26 .buswidth = 4, 27 }; 28 29 static struct qcom_icc_node qup2_core_slave = { 30 .name = "qup2_core_slave", 31 .channels = 1, 32 .buswidth = 4, 33 }; 34 35 static struct qcom_icc_node qup3_core_slave = { 36 .name = "qup3_core_slave", 37 .channels = 1, 38 .buswidth = 4, 39 }; 40 41 static struct qcom_icc_node ps_eth_0 = { 42 .name = "ps_eth_0", 43 .channels = 1, 44 .buswidth = 4, 45 }; 46 47 static struct qcom_icc_node ps_eth_1 = { 48 .name = "ps_eth_1", 49 .channels = 1, 50 .buswidth = 4, 51 }; 52 53 static struct qcom_icc_node ps_shs_server = { 54 .name = "ps_shs_server", 55 .channels = 1, 56 .buswidth = 4, 57 }; 58 59 static struct qcom_icc_node qhs_ahb2phy0 = { 60 .name = "qhs_ahb2phy0", 61 .channels = 1, 62 .buswidth = 4, 63 }; 64 65 static struct qcom_icc_node qhs_ahb2phy1 = { 66 .name = "qhs_ahb2phy1", 67 .channels = 1, 68 .buswidth = 4, 69 }; 70 71 static struct qcom_icc_node qhs_ahb2phy2 = { 72 .name = "qhs_ahb2phy2", 73 .channels = 1, 74 .buswidth = 4, 75 }; 76 77 static struct qcom_icc_node qhs_ahb2phy3 = { 78 .name = "qhs_ahb2phy3", 79 .channels = 1, 80 .buswidth = 4, 81 }; 82 83 static struct qcom_icc_node qhs_ahb2phy_eth_0 = { 84 .name = "qhs_ahb2phy_eth_0", 85 .channels = 1, 86 .buswidth = 4, 87 }; 88 89 static struct qcom_icc_node qhs_ahb2phy_eth_1 = { 90 .name = "qhs_ahb2phy_eth_1", 91 .channels = 1, 92 .buswidth = 4, 93 }; 94 95 static struct qcom_icc_node qhs_camera_cfg = { 96 .name = "qhs_camera_cfg", 97 .channels = 1, 98 .buswidth = 4, 99 }; 100 101 static struct qcom_icc_node qhs_clk_ctl = { 102 .name = "qhs_clk_ctl", 103 .channels = 1, 104 .buswidth = 4, 105 }; 106 107 static struct qcom_icc_node qhs_crypto0_cfg = { 108 .name = "qhs_crypto0_cfg", 109 .channels = 1, 110 .buswidth = 4, 111 }; 112 113 static struct qcom_icc_node qhs_crypto1_cfg = { 114 .name = "qhs_crypto1_cfg", 115 .channels = 1, 116 .buswidth = 4, 117 }; 118 119 static struct qcom_icc_node qhs_crypto2_cfg = { 120 .name = "qhs_crypto2_cfg", 121 .channels = 1, 122 .buswidth = 4, 123 }; 124 125 static struct qcom_icc_node qhs_display_1_cfg = { 126 .name = "qhs_display_1_cfg", 127 .channels = 1, 128 .buswidth = 4, 129 }; 130 131 static struct qcom_icc_node qhs_display_cfg = { 132 .name = "qhs_display_cfg", 133 .channels = 1, 134 .buswidth = 4, 135 }; 136 137 static struct qcom_icc_node qhs_dprx0 = { 138 .name = "qhs_dprx0", 139 .channels = 1, 140 .buswidth = 4, 141 }; 142 143 static struct qcom_icc_node qhs_dprx1 = { 144 .name = "qhs_dprx1", 145 .channels = 1, 146 .buswidth = 4, 147 }; 148 149 static struct qcom_icc_node qhs_eva_cfg = { 150 .name = "qhs_eva_cfg", 151 .channels = 1, 152 .buswidth = 4, 153 }; 154 155 static struct qcom_icc_node qhs_gpuss_0_cfg = { 156 .name = "qhs_gpuss_0_cfg", 157 .channels = 1, 158 .buswidth = 8, 159 }; 160 161 static struct qcom_icc_node qhs_gpuss_1_cfg = { 162 .name = "qhs_gpuss_1_cfg", 163 .channels = 1, 164 .buswidth = 8, 165 }; 166 167 static struct qcom_icc_node qhs_i2c = { 168 .name = "qhs_i2c", 169 .channels = 1, 170 .buswidth = 4, 171 }; 172 173 static struct qcom_icc_node qhs_imem_cfg = { 174 .name = "qhs_imem_cfg", 175 .channels = 1, 176 .buswidth = 4, 177 }; 178 179 static struct qcom_icc_node qhs_mcw_pcie = { 180 .name = "qhs_mcw_pcie", 181 .channels = 1, 182 .buswidth = 4, 183 }; 184 185 static struct qcom_icc_node qhs_mm_rscc = { 186 .name = "qhs_mm_rscc", 187 .channels = 1, 188 .buswidth = 4, 189 }; 190 191 static struct qcom_icc_node qhs_ne_clk_ctl = { 192 .name = "qhs_ne_clk_ctl", 193 .channels = 1, 194 .buswidth = 4, 195 }; 196 197 static struct qcom_icc_node qhs_nspss0_cfg = { 198 .name = "qhs_nspss0_cfg", 199 .channels = 1, 200 .buswidth = 4, 201 }; 202 203 static struct qcom_icc_node qhs_nspss1_cfg = { 204 .name = "qhs_nspss1_cfg", 205 .channels = 1, 206 .buswidth = 4, 207 }; 208 209 static struct qcom_icc_node qhs_nspss2_cfg = { 210 .name = "qhs_nspss2_cfg", 211 .channels = 1, 212 .buswidth = 4, 213 }; 214 215 static struct qcom_icc_node qhs_nspss3_cfg = { 216 .name = "qhs_nspss3_cfg", 217 .channels = 1, 218 .buswidth = 4, 219 }; 220 221 static struct qcom_icc_node qhs_nw_clk_ctl = { 222 .name = "qhs_nw_clk_ctl", 223 .channels = 1, 224 .buswidth = 4, 225 }; 226 227 static struct qcom_icc_node qhs_prng = { 228 .name = "qhs_prng", 229 .channels = 1, 230 .buswidth = 4, 231 }; 232 233 static struct qcom_icc_node qhs_qdss_cfg = { 234 .name = "qhs_qdss_cfg", 235 .channels = 1, 236 .buswidth = 4, 237 }; 238 239 static struct qcom_icc_node qhs_qspi = { 240 .name = "qhs_qspi", 241 .channels = 1, 242 .buswidth = 4, 243 }; 244 245 static struct qcom_icc_node qhs_qup0 = { 246 .name = "qhs_qup0", 247 .channels = 1, 248 .buswidth = 4, 249 }; 250 251 static struct qcom_icc_node qhs_qup3 = { 252 .name = "qhs_qup3", 253 .channels = 1, 254 .buswidth = 4, 255 }; 256 257 static struct qcom_icc_node qhs_qup1 = { 258 .name = "qhs_qup1", 259 .channels = 1, 260 .buswidth = 4, 261 }; 262 263 static struct qcom_icc_node qhs_qup2 = { 264 .name = "qhs_qup2", 265 .channels = 1, 266 .buswidth = 4, 267 }; 268 269 static struct qcom_icc_node qhs_safedma_cfg = { 270 .name = "qhs_safedma_cfg", 271 .channels = 1, 272 .buswidth = 4, 273 }; 274 275 static struct qcom_icc_node qhs_sdc4 = { 276 .name = "qhs_sdc4", 277 .channels = 1, 278 .buswidth = 4, 279 }; 280 281 static struct qcom_icc_node qhs_se_clk_ctl = { 282 .name = "qhs_se_clk_ctl", 283 .channels = 1, 284 .buswidth = 4, 285 }; 286 287 static struct qcom_icc_node qhs_tcsr = { 288 .name = "qhs_tcsr", 289 .channels = 1, 290 .buswidth = 4, 291 }; 292 293 static struct qcom_icc_node qhs_tlmm = { 294 .name = "qhs_tlmm", 295 .channels = 1, 296 .buswidth = 4, 297 }; 298 299 static struct qcom_icc_node qhs_tsc_cfg = { 300 .name = "qhs_tsc_cfg", 301 .channels = 1, 302 .buswidth = 4, 303 }; 304 305 static struct qcom_icc_node qhs_ufs_mem_cfg = { 306 .name = "qhs_ufs_mem_cfg", 307 .channels = 1, 308 .buswidth = 4, 309 }; 310 311 static struct qcom_icc_node qhs_usb2 = { 312 .name = "qhs_usb2", 313 .channels = 1, 314 .buswidth = 4, 315 }; 316 317 static struct qcom_icc_node qhs_usb3_0 = { 318 .name = "qhs_usb3_0", 319 .channels = 1, 320 .buswidth = 4, 321 }; 322 323 static struct qcom_icc_node qhs_usb3_1 = { 324 .name = "qhs_usb3_1", 325 .channels = 1, 326 .buswidth = 4, 327 }; 328 329 static struct qcom_icc_node qhs_venus_cfg = { 330 .name = "qhs_venus_cfg", 331 .channels = 1, 332 .buswidth = 4, 333 }; 334 335 static struct qcom_icc_node qss_computenoc_cfg = { 336 .name = "qss_computenoc_cfg", 337 .channels = 1, 338 .buswidth = 4, 339 }; 340 341 static struct qcom_icc_node qss_qtc_cfg = { 342 .name = "qss_qtc_cfg", 343 .channels = 1, 344 .buswidth = 4, 345 }; 346 347 static struct qcom_icc_node xs_qdss_stm = { 348 .name = "xs_qdss_stm", 349 .channels = 1, 350 .buswidth = 4, 351 }; 352 353 static struct qcom_icc_node xs_sys_tcu0_cfg = { 354 .name = "xs_sys_tcu0_cfg", 355 .channels = 1, 356 .buswidth = 8, 357 }; 358 359 static struct qcom_icc_node xs_sys_tcu1_cfg = { 360 .name = "xs_sys_tcu1_cfg", 361 .channels = 1, 362 .buswidth = 8, 363 }; 364 365 static struct qcom_icc_node xs_sys_tcu2_cfg = { 366 .name = "xs_sys_tcu2_cfg", 367 .channels = 1, 368 .buswidth = 8, 369 }; 370 371 static struct qcom_icc_node qhs_aoss = { 372 .name = "qhs_aoss", 373 .channels = 1, 374 .buswidth = 4, 375 }; 376 377 static struct qcom_icc_node qhs_hbcu = { 378 .name = "qhs_hbcu", 379 .channels = 1, 380 .buswidth = 4, 381 }; 382 383 static struct qcom_icc_node qhs_ipa = { 384 .name = "qhs_ipa", 385 .channels = 1, 386 .buswidth = 4, 387 }; 388 389 static struct qcom_icc_node qhs_ipc_router = { 390 .name = "qhs_ipc_router", 391 .channels = 1, 392 .buswidth = 4, 393 }; 394 395 static struct qcom_icc_node qhs_soccp = { 396 .name = "qhs_soccp", 397 .channels = 1, 398 .buswidth = 4, 399 }; 400 401 static struct qcom_icc_node qhs_tme_cfg = { 402 .name = "qhs_tme_cfg", 403 .channels = 1, 404 .buswidth = 4, 405 }; 406 407 static struct qcom_icc_node qss_ddrss_cfg = { 408 .name = "qss_ddrss_cfg", 409 .channels = 1, 410 .buswidth = 4, 411 }; 412 413 static struct qcom_icc_node qxs_imem = { 414 .name = "qxs_imem", 415 .channels = 1, 416 .buswidth = 8, 417 }; 418 419 static struct qcom_icc_node ebi = { 420 .name = "ebi", 421 .channels = 16, 422 .buswidth = 4, 423 }; 424 425 static struct qcom_icc_node qhs_pcie_ahb2phy_cfg = { 426 .name = "qhs_pcie_ahb2phy_cfg", 427 .channels = 1, 428 .buswidth = 4, 429 }; 430 431 static struct qcom_icc_node qhs_pcie_cfg_0 = { 432 .name = "qhs_pcie_cfg_0", 433 .channels = 1, 434 .buswidth = 4, 435 }; 436 437 static struct qcom_icc_node qhs_pcie_cfg_1 = { 438 .name = "qhs_pcie_cfg_1", 439 .channels = 1, 440 .buswidth = 4, 441 }; 442 443 static struct qcom_icc_node qhs_pcie_cfg_2 = { 444 .name = "qhs_pcie_cfg_2", 445 .channels = 1, 446 .buswidth = 4, 447 }; 448 449 static struct qcom_icc_node qhs_pcie_cfg_3 = { 450 .name = "qhs_pcie_cfg_3", 451 .channels = 1, 452 .buswidth = 4, 453 }; 454 455 static struct qcom_icc_node qhs_pcie_dma_0_cfg = { 456 .name = "qhs_pcie_dma_0_cfg", 457 .channels = 1, 458 .buswidth = 4, 459 }; 460 461 static struct qcom_icc_node qhs_pcie_dma_1_cfg = { 462 .name = "qhs_pcie_dma_1_cfg", 463 .channels = 1, 464 .buswidth = 4, 465 }; 466 467 static struct qcom_icc_node qhs_pcie_dma_2_cfg = { 468 .name = "qhs_pcie_dma_2_cfg", 469 .channels = 1, 470 .buswidth = 4, 471 }; 472 473 static struct qcom_icc_node qxs_pcie_dma_0 = { 474 .name = "qxs_pcie_dma_0", 475 .channels = 1, 476 .buswidth = 8, 477 }; 478 479 static struct qcom_icc_node qxs_pcie_dma_1 = { 480 .name = "qxs_pcie_dma_1", 481 .channels = 1, 482 .buswidth = 8, 483 }; 484 485 static struct qcom_icc_node qxs_pcie_dma_2 = { 486 .name = "qxs_pcie_dma_2", 487 .channels = 1, 488 .buswidth = 8, 489 }; 490 491 static struct qcom_icc_node xs_pcie_0 = { 492 .name = "xs_pcie_0", 493 .channels = 1, 494 .buswidth = 32, 495 }; 496 497 static struct qcom_icc_node xs_pcie_1 = { 498 .name = "xs_pcie_1", 499 .channels = 1, 500 .buswidth = 32, 501 }; 502 503 static struct qcom_icc_node xs_pcie_2 = { 504 .name = "xs_pcie_2", 505 .channels = 1, 506 .buswidth = 16, 507 }; 508 509 static struct qcom_icc_node xs_pcie_3 = { 510 .name = "xs_pcie_3", 511 .channels = 1, 512 .buswidth = 8, 513 }; 514 515 static struct qcom_icc_node qup0_core_master = { 516 .name = "qup0_core_master", 517 .channels = 1, 518 .buswidth = 4, 519 .num_links = 1, 520 .link_nodes = { &qup0_core_slave }, 521 }; 522 523 static struct qcom_icc_node qup1_core_master = { 524 .name = "qup1_core_master", 525 .channels = 1, 526 .buswidth = 4, 527 .num_links = 1, 528 .link_nodes = { &qup1_core_slave }, 529 }; 530 531 static struct qcom_icc_node qup2_core_master = { 532 .name = "qup2_core_master", 533 .channels = 1, 534 .buswidth = 4, 535 .num_links = 1, 536 .link_nodes = { &qup2_core_slave }, 537 }; 538 539 static struct qcom_icc_node qup3_core_master = { 540 .name = "qup3_core_master", 541 .channels = 1, 542 .buswidth = 4, 543 .num_links = 1, 544 .link_nodes = { &qup3_core_slave }, 545 }; 546 547 static struct qcom_icc_node llcc_mc = { 548 .name = "llcc_mc", 549 .channels = 16, 550 .buswidth = 4, 551 .num_links = 1, 552 .link_nodes = { &ebi }, 553 }; 554 555 static struct qcom_icc_node qsm_pcie_noc_cfg = { 556 .name = "qsm_pcie_noc_cfg", 557 .channels = 1, 558 .buswidth = 4, 559 .num_links = 8, 560 .link_nodes = { &qhs_pcie_ahb2phy_cfg, &qhs_pcie_cfg_0, 561 &qhs_pcie_cfg_1, &qhs_pcie_cfg_2, 562 &qhs_pcie_cfg_3, &qhs_pcie_dma_0_cfg, 563 &qhs_pcie_dma_1_cfg, &qhs_pcie_dma_2_cfg }, 564 }; 565 566 static struct qcom_icc_node qnm_cnoc_pcie_dma = { 567 .name = "qnm_cnoc_pcie_dma", 568 .channels = 1, 569 .buswidth = 16, 570 .num_links = 3, 571 .link_nodes = { &qxs_pcie_dma_0, &qxs_pcie_dma_1, 572 &qxs_pcie_dma_2 }, 573 }; 574 575 static struct qcom_icc_node qnm_hscnoc_pcie = { 576 .name = "qnm_hscnoc_pcie", 577 .channels = 1, 578 .buswidth = 32, 579 .num_links = 4, 580 .link_nodes = { &xs_pcie_0, &xs_pcie_1, 581 &xs_pcie_2, &xs_pcie_3 }, 582 }; 583 584 static struct qcom_icc_node qnm_pcie_ibnoc_dma = { 585 .name = "qnm_pcie_ibnoc_dma", 586 .channels = 1, 587 .buswidth = 16, 588 .num_links = 1, 589 .link_nodes = { &xs_pcie_0 }, 590 }; 591 592 static struct qcom_icc_node qss_pcie_noc_cfg = { 593 .name = "qss_pcie_noc_cfg", 594 .channels = 1, 595 .buswidth = 4, 596 .num_links = 1, 597 .link_nodes = { &qsm_pcie_noc_cfg }, 598 }; 599 600 static struct qcom_icc_node qns_pcie_dma = { 601 .name = "qns_pcie_dma", 602 .channels = 1, 603 .buswidth = 16, 604 .num_links = 1, 605 .link_nodes = { &qnm_cnoc_pcie_dma }, 606 }; 607 608 static struct qcom_icc_node qns_llcc = { 609 .name = "qns_llcc", 610 .channels = 16, 611 .buswidth = 16, 612 .num_links = 1, 613 .link_nodes = { &llcc_mc }, 614 }; 615 616 static struct qcom_icc_node qns_pcie = { 617 .name = "qns_pcie", 618 .channels = 1, 619 .buswidth = 32, 620 .num_links = 1, 621 .link_nodes = { &qnm_hscnoc_pcie }, 622 }; 623 624 static struct qcom_icc_node qns_pcie_obnoc_dma = { 625 .name = "qns_pcie_obnoc_dma", 626 .channels = 1, 627 .buswidth = 16, 628 .num_links = 1, 629 .link_nodes = { &qnm_pcie_ibnoc_dma }, 630 }; 631 632 static struct qcom_icc_node qsm_cfg = { 633 .name = "qsm_cfg", 634 .channels = 1, 635 .buswidth = 4, 636 .num_links = 56, 637 .link_nodes = { &ps_eth_0, &ps_eth_1, 638 &ps_shs_server, &qhs_ahb2phy0, 639 &qhs_ahb2phy1, &qhs_ahb2phy2, 640 &qhs_ahb2phy3, &qhs_ahb2phy_eth_0, 641 &qhs_ahb2phy_eth_1, &qhs_camera_cfg, 642 &qhs_clk_ctl, &qhs_crypto0_cfg, 643 &qhs_crypto1_cfg, &qhs_crypto2_cfg, 644 &qhs_display_1_cfg, &qhs_display_cfg, 645 &qhs_dprx0, &qhs_dprx1, 646 &qhs_eva_cfg, &qhs_gpuss_0_cfg, 647 &qhs_gpuss_1_cfg, &qhs_i2c, 648 &qhs_imem_cfg, &qhs_mcw_pcie, 649 &qhs_mm_rscc, &qhs_ne_clk_ctl, 650 &qhs_nspss0_cfg, &qhs_nspss1_cfg, 651 &qhs_nspss2_cfg, &qhs_nspss3_cfg, 652 &qhs_nw_clk_ctl, &qhs_prng, 653 &qhs_qdss_cfg, &qhs_qspi, 654 &qhs_qup0, &qhs_qup3, 655 &qhs_qup1, &qhs_qup2, 656 &qhs_safedma_cfg, &qhs_sdc4, 657 &qhs_se_clk_ctl, &qhs_tcsr, 658 &qhs_tlmm, &qhs_tsc_cfg, 659 &qhs_ufs_mem_cfg, &qhs_usb2, 660 &qhs_usb3_0, &qhs_usb3_1, 661 &qhs_venus_cfg, &qss_computenoc_cfg, 662 &qss_pcie_noc_cfg, &qss_qtc_cfg, 663 &xs_qdss_stm, &xs_sys_tcu0_cfg, 664 &xs_sys_tcu1_cfg, &xs_sys_tcu2_cfg }, 665 }; 666 667 static struct qcom_icc_node xm_gic = { 668 .name = "xm_gic", 669 .channels = 1, 670 .buswidth = 8, 671 .qosbox = &(const struct qcom_icc_qosbox) { 672 .num_ports = 1, 673 .port_offsets = { 0xa44000 }, 674 .prio = 4, 675 .urg_fwd = 0, 676 .prio_fwd_disable = 1, 677 }, 678 .num_links = 1, 679 .link_nodes = { &qns_llcc }, 680 }; 681 682 static struct qcom_icc_node qss_cfg = { 683 .name = "qss_cfg", 684 .channels = 1, 685 .buswidth = 4, 686 .num_links = 1, 687 .link_nodes = { &qsm_cfg }, 688 }; 689 690 static struct qcom_icc_node qhm_mm_rscc = { 691 .name = "qhm_mm_rscc", 692 .channels = 1, 693 .buswidth = 4, 694 .num_links = 1, 695 .link_nodes = { &qss_cfg }, 696 }; 697 698 static struct qcom_icc_node qnm_hscnoc = { 699 .name = "qnm_hscnoc", 700 .channels = 1, 701 .buswidth = 16, 702 .num_links = 10, 703 .link_nodes = { &qhs_aoss, &qhs_hbcu, 704 &qhs_ipa, &qhs_ipc_router, 705 &qhs_soccp, &qhs_tme_cfg, 706 &qns_pcie_dma, &qss_cfg, 707 &qss_ddrss_cfg, &qxs_imem }, 708 }; 709 710 static struct qcom_icc_node qns_hscnoc_cnoc = { 711 .name = "qns_hscnoc_cnoc", 712 .channels = 1, 713 .buswidth = 16, 714 .num_links = 1, 715 .link_nodes = { &qnm_hscnoc }, 716 }; 717 718 static struct qcom_icc_node alm_gpu_tcu = { 719 .name = "alm_gpu_tcu", 720 .channels = 2, 721 .buswidth = 8, 722 .qosbox = &(const struct qcom_icc_qosbox) { 723 .num_ports = 2, 724 .port_offsets = { 0x930000, 0xa45000 }, 725 .prio = 1, 726 .urg_fwd = 0, 727 .prio_fwd_disable = 1, 728 }, 729 .num_links = 2, 730 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, 731 }; 732 733 static struct qcom_icc_node alm_qtc = { 734 .name = "alm_qtc", 735 .channels = 1, 736 .buswidth = 8, 737 .qosbox = &(const struct qcom_icc_qosbox) { 738 .num_ports = 1, 739 .port_offsets = { 0x2c0000 }, 740 .prio = 3, 741 .urg_fwd = 0, 742 .prio_fwd_disable = 1, 743 }, 744 .num_links = 2, 745 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, 746 }; 747 748 static struct qcom_icc_node alm_sys_tcu0 = { 749 .name = "alm_sys_tcu0", 750 .channels = 1, 751 .buswidth = 8, 752 .qosbox = &(const struct qcom_icc_qosbox) { 753 .num_ports = 1, 754 .port_offsets = { 0xa42000 }, 755 .prio = 6, 756 .urg_fwd = 0, 757 .prio_fwd_disable = 1, 758 }, 759 .num_links = 2, 760 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, 761 }; 762 763 static struct qcom_icc_node alm_sys_tcu1 = { 764 .name = "alm_sys_tcu1", 765 .channels = 1, 766 .buswidth = 8, 767 .qosbox = &(const struct qcom_icc_qosbox) { 768 .num_ports = 1, 769 .port_offsets = { 0x81f000 }, 770 .prio = 6, 771 .urg_fwd = 0, 772 .prio_fwd_disable = 1, 773 }, 774 .num_links = 2, 775 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, 776 }; 777 778 static struct qcom_icc_node alm_sys_tcu2 = { 779 .name = "alm_sys_tcu2", 780 .channels = 1, 781 .buswidth = 8, 782 .qosbox = &(const struct qcom_icc_qosbox) { 783 .num_ports = 1, 784 .port_offsets = { 0x30000 }, 785 .prio = 6, 786 .urg_fwd = 0, 787 .prio_fwd_disable = 1, 788 }, 789 .num_links = 2, 790 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, 791 }; 792 793 static struct qcom_icc_node chm_apps = { 794 .name = "chm_apps", 795 .channels = 6, 796 .buswidth = 32, 797 .num_links = 3, 798 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 799 &qns_pcie }, 800 }; 801 802 static struct qcom_icc_node qnm_aggre_north = { 803 .name = "qnm_aggre_north", 804 .channels = 1, 805 .buswidth = 16, 806 .qosbox = &(const struct qcom_icc_qosbox) { 807 .num_ports = 1, 808 .port_offsets = { 0x935000 }, 809 .prio = 0, 810 .urg_fwd = 1, 811 .prio_fwd_disable = 0, 812 }, 813 .num_links = 3, 814 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 815 &qns_pcie }, 816 }; 817 818 static struct qcom_icc_node qnm_aggre_south = { 819 .name = "qnm_aggre_south", 820 .channels = 1, 821 .buswidth = 16, 822 .qosbox = &(const struct qcom_icc_qosbox) { 823 .num_ports = 1, 824 .port_offsets = { 0x31000 }, 825 .prio = 0, 826 .urg_fwd = 1, 827 .prio_fwd_disable = 0, 828 }, 829 .num_links = 3, 830 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 831 &qns_pcie }, 832 }; 833 834 static struct qcom_icc_node qnm_gpu0 = { 835 .name = "qnm_gpu0", 836 .channels = 4, 837 .buswidth = 32, 838 .qosbox = &(const struct qcom_icc_qosbox) { 839 .num_ports = 4, 840 .port_offsets = { 0x931000, 0x932000, 0x933000, 0x934000 }, 841 .prio = 0, 842 .urg_fwd = 0, 843 .prio_fwd_disable = 1, 844 }, 845 .num_links = 3, 846 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 847 &qns_pcie }, 848 }; 849 850 static struct qcom_icc_node qnm_gpu1 = { 851 .name = "qnm_gpu1", 852 .channels = 2, 853 .buswidth = 32, 854 .qosbox = &(const struct qcom_icc_qosbox) { 855 .num_ports = 2, 856 .port_offsets = { 0xa40000, 0xa41000 }, 857 .prio = 0, 858 .urg_fwd = 0, 859 .prio_fwd_disable = 1, 860 }, 861 .num_links = 3, 862 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 863 &qns_pcie }, 864 }; 865 866 static struct qcom_icc_node qnm_hpass_adas_hscnoc = { 867 .name = "qnm_hpass_adas_hscnoc", 868 .channels = 2, 869 .buswidth = 32, 870 .qosbox = &(const struct qcom_icc_qosbox) { 871 .num_ports = 2, 872 .port_offsets = { 0x240000, 0x245000 }, 873 .prio = 0, 874 .urg_fwd = 1, 875 .prio_fwd_disable = 0, 876 }, 877 .num_links = 3, 878 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 879 &qns_pcie }, 880 }; 881 882 static struct qcom_icc_node qnm_hpass_audio_hscnoc = { 883 .name = "qnm_hpass_audio_hscnoc", 884 .channels = 1, 885 .buswidth = 32, 886 .qosbox = &(const struct qcom_icc_qosbox) { 887 .num_ports = 1, 888 .port_offsets = { 0x241000 }, 889 .prio = 3, 890 .urg_fwd = 1, 891 .prio_fwd_disable = 0, 892 }, 893 .num_links = 3, 894 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 895 &qns_pcie }, 896 }; 897 898 static struct qcom_icc_node qnm_mnoc_hf = { 899 .name = "qnm_mnoc_hf", 900 .channels = 2, 901 .buswidth = 32, 902 .qosbox = &(const struct qcom_icc_qosbox) { 903 .num_ports = 2, 904 .port_offsets = { 0x81d000, 0x820000 }, 905 .prio = 0, 906 .urg_fwd = 1, 907 .prio_fwd_disable = 0, 908 }, 909 .num_links = 3, 910 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 911 &qns_pcie }, 912 }; 913 914 static struct qcom_icc_node qnm_mnoc_sf = { 915 .name = "qnm_mnoc_sf", 916 .channels = 2, 917 .buswidth = 32, 918 .qosbox = &(const struct qcom_icc_qosbox) { 919 .num_ports = 2, 920 .port_offsets = { 0x81e000, 0x821000 }, 921 .prio = 0, 922 .urg_fwd = 1, 923 .prio_fwd_disable = 0, 924 }, 925 .num_links = 3, 926 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 927 &qns_pcie }, 928 }; 929 930 static struct qcom_icc_node qnm_nsp0_hscnoc = { 931 .name = "qnm_nsp0_hscnoc", 932 .channels = 2, 933 .buswidth = 32, 934 .qosbox = &(const struct qcom_icc_qosbox) { 935 .num_ports = 2, 936 .port_offsets = { 0x32000, 0x33000 }, 937 .prio = 0, 938 .urg_fwd = 0, 939 .prio_fwd_disable = 1, 940 }, 941 .num_links = 3, 942 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 943 &qns_pcie }, 944 }; 945 946 static struct qcom_icc_node qnm_nsp1_hscnoc = { 947 .name = "qnm_nsp1_hscnoc", 948 .channels = 2, 949 .buswidth = 32, 950 .qosbox = &(const struct qcom_icc_qosbox) { 951 .num_ports = 2, 952 .port_offsets = { 0x34000, 0x35000 }, 953 .prio = 0, 954 .urg_fwd = 0, 955 .prio_fwd_disable = 1, 956 }, 957 .num_links = 3, 958 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 959 &qns_pcie }, 960 }; 961 962 static struct qcom_icc_node qnm_nsp2_hscnoc = { 963 .name = "qnm_nsp2_hscnoc", 964 .channels = 2, 965 .buswidth = 32, 966 .qosbox = &(const struct qcom_icc_qosbox) { 967 .num_ports = 2, 968 .port_offsets = { 0x36000, 0x37000 }, 969 .prio = 0, 970 .urg_fwd = 0, 971 .prio_fwd_disable = 1, 972 }, 973 .num_links = 3, 974 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 975 &qns_pcie }, 976 }; 977 978 static struct qcom_icc_node qnm_nsp3_hscnoc = { 979 .name = "qnm_nsp3_hscnoc", 980 .channels = 2, 981 .buswidth = 32, 982 .qosbox = &(const struct qcom_icc_qosbox) { 983 .num_ports = 2, 984 .port_offsets = { 0x38000, 0x39000 }, 985 .prio = 0, 986 .urg_fwd = 0, 987 .prio_fwd_disable = 1, 988 }, 989 .num_links = 3, 990 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 991 &qns_pcie }, 992 }; 993 994 static struct qcom_icc_node qnm_pcie = { 995 .name = "qnm_pcie", 996 .channels = 1, 997 .buswidth = 64, 998 .qosbox = &(const struct qcom_icc_qosbox) { 999 .num_ports = 1, 1000 .port_offsets = { 0x2c1000 }, 1001 .prio = 2, 1002 .urg_fwd = 1, 1003 .prio_fwd_disable = 1, 1004 }, 1005 .num_links = 2, 1006 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, 1007 }; 1008 1009 static struct qcom_icc_node qnm_sailss_md0_hscnoc = { 1010 .name = "qnm_sailss_md0_hscnoc", 1011 .channels = 1, 1012 .buswidth = 16, 1013 .qosbox = &(const struct qcom_icc_qosbox) { 1014 .num_ports = 1, 1015 .port_offsets = { 0x243000 }, 1016 .prio = 2, 1017 .urg_fwd = 0, 1018 .prio_fwd_disable = 1, 1019 }, 1020 .num_links = 3, 1021 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 1022 &qns_pcie }, 1023 }; 1024 1025 static struct qcom_icc_node qnm_snoc_sf = { 1026 .name = "qnm_snoc_sf", 1027 .channels = 1, 1028 .buswidth = 64, 1029 .qosbox = &(const struct qcom_icc_qosbox) { 1030 .num_ports = 1, 1031 .port_offsets = { 0xa43000 }, 1032 .prio = 0, 1033 .urg_fwd = 1, 1034 .prio_fwd_disable = 0, 1035 }, 1036 .num_links = 3, 1037 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, 1038 &qns_pcie }, 1039 }; 1040 1041 static struct qcom_icc_node qns_a1noc_hscnoc = { 1042 .name = "qns_a1noc_hscnoc", 1043 .channels = 1, 1044 .buswidth = 16, 1045 .num_links = 1, 1046 .link_nodes = { &qnm_aggre_north }, 1047 }; 1048 1049 static struct qcom_icc_node qns_a2noc_hscnoc = { 1050 .name = "qns_a2noc_hscnoc", 1051 .channels = 1, 1052 .buswidth = 16, 1053 .num_links = 1, 1054 .link_nodes = { &qnm_aggre_south }, 1055 }; 1056 1057 static struct qcom_icc_node qns_hpass_agnoc_audio = { 1058 .name = "qns_hpass_agnoc_audio", 1059 .channels = 1, 1060 .buswidth = 32, 1061 .num_links = 1, 1062 .link_nodes = { &qnm_hpass_audio_hscnoc }, 1063 }; 1064 1065 static struct qcom_icc_node qns_mem_noc_hf = { 1066 .name = "qns_mem_noc_hf", 1067 .channels = 2, 1068 .buswidth = 32, 1069 .num_links = 1, 1070 .link_nodes = { &qnm_mnoc_hf }, 1071 }; 1072 1073 static struct qcom_icc_node qns_mem_noc_sf = { 1074 .name = "qns_mem_noc_sf", 1075 .channels = 2, 1076 .buswidth = 32, 1077 .num_links = 1, 1078 .link_nodes = { &qnm_mnoc_sf }, 1079 }; 1080 1081 static struct qcom_icc_node qns_nsp0_hsc_noc = { 1082 .name = "qns_nsp0_hsc_noc", 1083 .channels = 2, 1084 .buswidth = 32, 1085 .num_links = 1, 1086 .link_nodes = { &qnm_nsp0_hscnoc }, 1087 }; 1088 1089 static struct qcom_icc_node qns_nsp1_hsc_noc = { 1090 .name = "qns_nsp1_hsc_noc", 1091 .channels = 2, 1092 .buswidth = 32, 1093 .num_links = 1, 1094 .link_nodes = { &qnm_nsp1_hscnoc }, 1095 }; 1096 1097 static struct qcom_icc_node qns_nsp2_hsc_noc = { 1098 .name = "qns_nsp2_hsc_noc", 1099 .channels = 2, 1100 .buswidth = 32, 1101 .num_links = 1, 1102 .link_nodes = { &qnm_nsp2_hscnoc }, 1103 }; 1104 1105 static struct qcom_icc_node qns_nsp3_hsc_noc = { 1106 .name = "qns_nsp3_hsc_noc", 1107 .channels = 2, 1108 .buswidth = 32, 1109 .num_links = 1, 1110 .link_nodes = { &qnm_nsp3_hscnoc }, 1111 }; 1112 1113 static struct qcom_icc_node qns_pcie_hscnoc = { 1114 .name = "qns_pcie_hscnoc", 1115 .channels = 1, 1116 .buswidth = 64, 1117 .num_links = 1, 1118 .link_nodes = { &qnm_pcie }, 1119 }; 1120 1121 static struct qcom_icc_node qns_hscnoc_sf = { 1122 .name = "qns_hscnoc_sf", 1123 .channels = 1, 1124 .buswidth = 64, 1125 .num_links = 1, 1126 .link_nodes = { &qnm_snoc_sf }, 1127 }; 1128 1129 static struct qcom_icc_node qhm_qup2 = { 1130 .name = "qhm_qup2", 1131 .channels = 1, 1132 .buswidth = 4, 1133 .qosbox = &(const struct qcom_icc_qosbox) { 1134 .num_ports = 1, 1135 .port_offsets = { 0x1b000 }, 1136 .prio = 2, 1137 .urg_fwd = 0, 1138 .prio_fwd_disable = 1, 1139 }, 1140 .num_links = 1, 1141 .link_nodes = { &qns_a1noc_hscnoc }, 1142 }; 1143 1144 static struct qcom_icc_node qxm_crypto_0 = { 1145 .name = "qxm_crypto_0", 1146 .channels = 1, 1147 .buswidth = 8, 1148 .qosbox = &(const struct qcom_icc_qosbox) { 1149 .num_ports = 1, 1150 .port_offsets = { 0x1c000 }, 1151 .prio = 2, 1152 .urg_fwd = 0, 1153 .prio_fwd_disable = 1, 1154 }, 1155 .num_links = 1, 1156 .link_nodes = { &qns_a1noc_hscnoc }, 1157 }; 1158 1159 static struct qcom_icc_node qxm_crypto_1 = { 1160 .name = "qxm_crypto_1", 1161 .channels = 1, 1162 .buswidth = 8, 1163 .qosbox = &(const struct qcom_icc_qosbox) { 1164 .num_ports = 1, 1165 .port_offsets = { 0x1d000 }, 1166 .prio = 2, 1167 .urg_fwd = 0, 1168 .prio_fwd_disable = 1, 1169 }, 1170 .num_links = 1, 1171 .link_nodes = { &qns_a1noc_hscnoc }, 1172 }; 1173 1174 static struct qcom_icc_node qxm_crypto_2 = { 1175 .name = "qxm_crypto_2", 1176 .channels = 1, 1177 .buswidth = 8, 1178 .qosbox = &(const struct qcom_icc_qosbox) { 1179 .num_ports = 1, 1180 .port_offsets = { 0x1e000 }, 1181 .prio = 2, 1182 .urg_fwd = 0, 1183 .prio_fwd_disable = 1, 1184 }, 1185 .num_links = 1, 1186 .link_nodes = { &qns_a1noc_hscnoc }, 1187 }; 1188 1189 static struct qcom_icc_node xm_sdc4 = { 1190 .name = "xm_sdc4", 1191 .channels = 1, 1192 .buswidth = 8, 1193 .qosbox = &(const struct qcom_icc_qosbox) { 1194 .num_ports = 1, 1195 .port_offsets = { 0x16000 }, 1196 .prio = 2, 1197 .urg_fwd = 0, 1198 .prio_fwd_disable = 1, 1199 }, 1200 .num_links = 1, 1201 .link_nodes = { &qns_a1noc_hscnoc }, 1202 }; 1203 1204 static struct qcom_icc_node xm_ufs_mem = { 1205 .name = "xm_ufs_mem", 1206 .channels = 1, 1207 .buswidth = 16, 1208 .qosbox = &(const struct qcom_icc_qosbox) { 1209 .num_ports = 1, 1210 .port_offsets = { 0x17000 }, 1211 .prio = 2, 1212 .urg_fwd = 0, 1213 .prio_fwd_disable = 1, 1214 }, 1215 .num_links = 1, 1216 .link_nodes = { &qns_a1noc_hscnoc }, 1217 }; 1218 1219 static struct qcom_icc_node xm_usb2 = { 1220 .name = "xm_usb2", 1221 .channels = 1, 1222 .buswidth = 8, 1223 .qosbox = &(const struct qcom_icc_qosbox) { 1224 .num_ports = 1, 1225 .port_offsets = { 0x19000 }, 1226 .prio = 2, 1227 .urg_fwd = 0, 1228 .prio_fwd_disable = 1, 1229 }, 1230 .num_links = 1, 1231 .link_nodes = { &qns_a1noc_hscnoc }, 1232 }; 1233 1234 static struct qcom_icc_node xm_usb3_0 = { 1235 .name = "xm_usb3_0", 1236 .channels = 1, 1237 .buswidth = 8, 1238 .qosbox = &(const struct qcom_icc_qosbox) { 1239 .num_ports = 1, 1240 .port_offsets = { 0x18000 }, 1241 .prio = 2, 1242 .urg_fwd = 0, 1243 .prio_fwd_disable = 1, 1244 }, 1245 .num_links = 1, 1246 .link_nodes = { &qns_a1noc_hscnoc }, 1247 }; 1248 1249 static struct qcom_icc_node xm_usb3_1 = { 1250 .name = "xm_usb3_1", 1251 .channels = 1, 1252 .buswidth = 8, 1253 .qosbox = &(const struct qcom_icc_qosbox) { 1254 .num_ports = 1, 1255 .port_offsets = { 0x1a000 }, 1256 .prio = 2, 1257 .urg_fwd = 0, 1258 .prio_fwd_disable = 1, 1259 }, 1260 .num_links = 1, 1261 .link_nodes = { &qns_a1noc_hscnoc }, 1262 }; 1263 1264 static struct qcom_icc_node qhm_qup0 = { 1265 .name = "qhm_qup0", 1266 .channels = 1, 1267 .buswidth = 4, 1268 .qosbox = &(const struct qcom_icc_qosbox) { 1269 .num_ports = 1, 1270 .port_offsets = { 0x13000 }, 1271 .prio = 2, 1272 .urg_fwd = 0, 1273 .prio_fwd_disable = 1, 1274 }, 1275 .num_links = 1, 1276 .link_nodes = { &qns_a2noc_hscnoc }, 1277 }; 1278 1279 static struct qcom_icc_node qhm_qup1 = { 1280 .name = "qhm_qup1", 1281 .channels = 1, 1282 .buswidth = 4, 1283 .qosbox = &(const struct qcom_icc_qosbox) { 1284 .num_ports = 1, 1285 .port_offsets = { 0x14000 }, 1286 .prio = 2, 1287 .urg_fwd = 0, 1288 .prio_fwd_disable = 1, 1289 }, 1290 .num_links = 1, 1291 .link_nodes = { &qns_a2noc_hscnoc }, 1292 }; 1293 1294 static struct qcom_icc_node xm_emac_0 = { 1295 .name = "xm_emac_0", 1296 .channels = 1, 1297 .buswidth = 16, 1298 .qosbox = &(const struct qcom_icc_qosbox) { 1299 .num_ports = 1, 1300 .port_offsets = { 0x16000 }, 1301 .prio = 2, 1302 .urg_fwd = 0, 1303 .prio_fwd_disable = 1, 1304 }, 1305 .num_links = 1, 1306 .link_nodes = { &qns_a2noc_hscnoc }, 1307 }; 1308 1309 static struct qcom_icc_node xm_emac_1 = { 1310 .name = "xm_emac_1", 1311 .channels = 1, 1312 .buswidth = 16, 1313 .qosbox = &(const struct qcom_icc_qosbox) { 1314 .num_ports = 1, 1315 .port_offsets = { 0x17000 }, 1316 .prio = 2, 1317 .urg_fwd = 0, 1318 .prio_fwd_disable = 1, 1319 }, 1320 .num_links = 1, 1321 .link_nodes = { &qns_a2noc_hscnoc }, 1322 }; 1323 1324 static struct qcom_icc_node qnm_hpass_dsp0 = { 1325 .name = "qnm_hpass_dsp0", 1326 .channels = 2, 1327 .buswidth = 32, 1328 .num_links = 1, 1329 .link_nodes = { &qns_hpass_agnoc_audio }, 1330 }; 1331 1332 static struct qcom_icc_node qnm_hpass_dsp1 = { 1333 .name = "qnm_hpass_dsp1", 1334 .channels = 2, 1335 .buswidth = 32, 1336 .num_links = 1, 1337 .link_nodes = { &qns_hpass_agnoc_audio }, 1338 }; 1339 1340 static struct qcom_icc_node qnm_hpass_dsp2 = { 1341 .name = "qnm_hpass_dsp2", 1342 .channels = 2, 1343 .buswidth = 32, 1344 .num_links = 1, 1345 .link_nodes = { &qns_hpass_agnoc_audio }, 1346 }; 1347 1348 static struct qcom_icc_node qnm_camnoc_hf = { 1349 .name = "qnm_camnoc_hf", 1350 .channels = 2, 1351 .buswidth = 32, 1352 .qosbox = &(const struct qcom_icc_qosbox) { 1353 .num_ports = 2, 1354 .port_offsets = { 0x57000, 0x58000 }, 1355 .prio = 0, 1356 .urg_fwd = 1, 1357 .prio_fwd_disable = 0, 1358 }, 1359 .num_links = 1, 1360 .link_nodes = { &qns_mem_noc_hf }, 1361 }; 1362 1363 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { 1364 .name = "qnm_camnoc_nrt_icp_sf", 1365 .channels = 1, 1366 .buswidth = 8, 1367 .qosbox = &(const struct qcom_icc_qosbox) { 1368 .num_ports = 1, 1369 .port_offsets = { 0x1a000 }, 1370 .prio = 4, 1371 .urg_fwd = 1, 1372 .prio_fwd_disable = 1, 1373 }, 1374 .num_links = 1, 1375 .link_nodes = { &qns_mem_noc_sf }, 1376 }; 1377 1378 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { 1379 .name = "qnm_camnoc_rt_cdm_sf", 1380 .channels = 1, 1381 .buswidth = 8, 1382 .qosbox = &(const struct qcom_icc_qosbox) { 1383 .num_ports = 1, 1384 .port_offsets = { 0x5b000 }, 1385 .prio = 2, 1386 .urg_fwd = 1, 1387 .prio_fwd_disable = 1, 1388 }, 1389 .num_links = 1, 1390 .link_nodes = { &qns_mem_noc_sf }, 1391 }; 1392 1393 static struct qcom_icc_node qnm_camnoc_sf = { 1394 .name = "qnm_camnoc_sf", 1395 .channels = 2, 1396 .buswidth = 32, 1397 .qosbox = &(const struct qcom_icc_qosbox) { 1398 .num_ports = 2, 1399 .port_offsets = { 0x1b000, 0x1c000 }, 1400 .prio = 0, 1401 .urg_fwd = 1, 1402 .prio_fwd_disable = 0, 1403 }, 1404 .num_links = 1, 1405 .link_nodes = { &qns_mem_noc_sf }, 1406 }; 1407 1408 static struct qcom_icc_node qnm_dprx0 = { 1409 .name = "qnm_dprx0", 1410 .channels = 1, 1411 .buswidth = 32, 1412 .qosbox = &(const struct qcom_icc_qosbox) { 1413 .num_ports = 1, 1414 .port_offsets = { 0x5c000 }, 1415 .prio = 0, 1416 .urg_fwd = 1, 1417 .prio_fwd_disable = 0, 1418 }, 1419 .num_links = 1, 1420 .link_nodes = { &qns_mem_noc_hf }, 1421 }; 1422 1423 static struct qcom_icc_node qnm_dprx1 = { 1424 .name = "qnm_dprx1", 1425 .channels = 1, 1426 .buswidth = 32, 1427 .qosbox = &(const struct qcom_icc_qosbox) { 1428 .num_ports = 1, 1429 .port_offsets = { 0x5d000 }, 1430 .prio = 0, 1431 .urg_fwd = 1, 1432 .prio_fwd_disable = 0, 1433 }, 1434 .num_links = 1, 1435 .link_nodes = { &qns_mem_noc_hf }, 1436 }; 1437 1438 static struct qcom_icc_node qnm_mdp0 = { 1439 .name = "qnm_mdp0", 1440 .channels = 2, 1441 .buswidth = 32, 1442 .qosbox = &(const struct qcom_icc_qosbox) { 1443 .num_ports = 2, 1444 .port_offsets = { 0x59000, 0x5a000 }, 1445 .prio = 0, 1446 .urg_fwd = 1, 1447 .prio_fwd_disable = 0, 1448 }, 1449 .num_links = 1, 1450 .link_nodes = { &qns_mem_noc_hf }, 1451 }; 1452 1453 static struct qcom_icc_node qnm_mdp1 = { 1454 .name = "qnm_mdp1", 1455 .channels = 2, 1456 .buswidth = 32, 1457 .qosbox = &(const struct qcom_icc_qosbox) { 1458 .num_ports = 2, 1459 .port_offsets = { 0x5e000, 0x5f000 }, 1460 .prio = 0, 1461 .urg_fwd = 1, 1462 .prio_fwd_disable = 0, 1463 }, 1464 .num_links = 1, 1465 .link_nodes = { &qns_mem_noc_hf }, 1466 }; 1467 1468 static struct qcom_icc_node qnm_video_cv_cpu = { 1469 .name = "qnm_video_cv_cpu", 1470 .channels = 1, 1471 .buswidth = 8, 1472 .qosbox = &(const struct qcom_icc_qosbox) { 1473 .num_ports = 1, 1474 .port_offsets = { 0x21000 }, 1475 .prio = 4, 1476 .urg_fwd = 1, 1477 .prio_fwd_disable = 1, 1478 }, 1479 .num_links = 1, 1480 .link_nodes = { &qns_mem_noc_sf }, 1481 }; 1482 1483 static struct qcom_icc_node qnm_video_eva = { 1484 .name = "qnm_video_eva", 1485 .channels = 2, 1486 .buswidth = 32, 1487 .qosbox = &(const struct qcom_icc_qosbox) { 1488 .num_ports = 2, 1489 .port_offsets = { 0x22000, 0x23000 }, 1490 .prio = 0, 1491 .urg_fwd = 1, 1492 .prio_fwd_disable = 0, 1493 }, 1494 .num_links = 1, 1495 .link_nodes = { &qns_mem_noc_sf }, 1496 }; 1497 1498 static struct qcom_icc_node qnm_video_mvp0 = { 1499 .name = "qnm_video_mvp0", 1500 .channels = 2, 1501 .buswidth = 32, 1502 .qosbox = &(const struct qcom_icc_qosbox) { 1503 .num_ports = 2, 1504 .port_offsets = { 0x1d000, 0x1e000 }, 1505 .prio = 0, 1506 .urg_fwd = 1, 1507 .prio_fwd_disable = 0, 1508 }, 1509 .num_links = 1, 1510 .link_nodes = { &qns_mem_noc_sf }, 1511 }; 1512 1513 static struct qcom_icc_node qnm_video_mvp1 = { 1514 .name = "qnm_video_mvp1", 1515 .channels = 2, 1516 .buswidth = 32, 1517 .qosbox = &(const struct qcom_icc_qosbox) { 1518 .num_ports = 2, 1519 .port_offsets = { 0x1f000, 0x20000 }, 1520 .prio = 0, 1521 .urg_fwd = 1, 1522 .prio_fwd_disable = 0, 1523 }, 1524 .num_links = 1, 1525 .link_nodes = { &qns_mem_noc_sf }, 1526 }; 1527 1528 static struct qcom_icc_node qnm_video_v_cpu = { 1529 .name = "qnm_video_v_cpu", 1530 .channels = 1, 1531 .buswidth = 8, 1532 .qosbox = &(const struct qcom_icc_qosbox) { 1533 .num_ports = 1, 1534 .port_offsets = { 0x24000 }, 1535 .prio = 4, 1536 .urg_fwd = 1, 1537 .prio_fwd_disable = 1, 1538 }, 1539 .num_links = 1, 1540 .link_nodes = { &qns_mem_noc_sf }, 1541 }; 1542 1543 static struct qcom_icc_node qnm_nsp_data00 = { 1544 .name = "qnm_nsp_data00", 1545 .channels = 2, 1546 .buswidth = 32, 1547 .num_links = 1, 1548 .link_nodes = { &qns_nsp0_hsc_noc }, 1549 }; 1550 1551 static struct qcom_icc_node qnm_nsp_data01 = { 1552 .name = "qnm_nsp_data01", 1553 .channels = 2, 1554 .buswidth = 32, 1555 .num_links = 1, 1556 .link_nodes = { &qns_nsp1_hsc_noc }, 1557 }; 1558 1559 static struct qcom_icc_node qnm_nsp_data02 = { 1560 .name = "qnm_nsp_data02", 1561 .channels = 2, 1562 .buswidth = 32, 1563 .num_links = 1, 1564 .link_nodes = { &qns_nsp2_hsc_noc }, 1565 }; 1566 1567 static struct qcom_icc_node qnm_nsp_data03 = { 1568 .name = "qnm_nsp_data03", 1569 .channels = 2, 1570 .buswidth = 32, 1571 .num_links = 1, 1572 .link_nodes = { &qns_nsp3_hsc_noc }, 1573 }; 1574 1575 static struct qcom_icc_node qxm_pcie_dma_0 = { 1576 .name = "qxm_pcie_dma_0", 1577 .channels = 1, 1578 .buswidth = 8, 1579 .qosbox = &(const struct qcom_icc_qosbox) { 1580 .num_ports = 1, 1581 .port_offsets = { 0x49000 }, 1582 .prio = 0, 1583 .urg_fwd = 0, 1584 .prio_fwd_disable = 0, 1585 }, 1586 .num_links = 2, 1587 .link_nodes = { &qns_pcie_hscnoc, &qns_pcie_obnoc_dma }, 1588 }; 1589 1590 static struct qcom_icc_node qxm_pcie_dma_1 = { 1591 .name = "qxm_pcie_dma_1", 1592 .channels = 1, 1593 .buswidth = 8, 1594 .qosbox = &(const struct qcom_icc_qosbox) { 1595 .num_ports = 1, 1596 .port_offsets = { 0x4a000 }, 1597 .prio = 0, 1598 .urg_fwd = 0, 1599 .prio_fwd_disable = 0, 1600 }, 1601 .num_links = 2, 1602 .link_nodes = { &qns_pcie_hscnoc, &qns_pcie_obnoc_dma }, 1603 }; 1604 1605 static struct qcom_icc_node qxm_pcie_dma_2 = { 1606 .name = "qxm_pcie_dma_2", 1607 .channels = 1, 1608 .buswidth = 8, 1609 .qosbox = &(const struct qcom_icc_qosbox) { 1610 .num_ports = 1, 1611 .port_offsets = { 0x4b000 }, 1612 .prio = 0, 1613 .urg_fwd = 0, 1614 .prio_fwd_disable = 0, 1615 }, 1616 .num_links = 2, 1617 .link_nodes = { &qns_pcie_hscnoc, &qns_pcie_obnoc_dma }, 1618 }; 1619 1620 static struct qcom_icc_node xm_pcie_0 = { 1621 .name = "xm_pcie_0", 1622 .channels = 1, 1623 .buswidth = 64, 1624 .qosbox = &(const struct qcom_icc_qosbox) { 1625 .num_ports = 1, 1626 .port_offsets = { 0x18000 }, 1627 .prio = 2, 1628 .urg_fwd = 0, 1629 .prio_fwd_disable = 1, 1630 }, 1631 .num_links = 1, 1632 .link_nodes = { &qns_pcie_hscnoc }, 1633 }; 1634 1635 static struct qcom_icc_node xm_pcie_1 = { 1636 .name = "xm_pcie_1", 1637 .channels = 1, 1638 .buswidth = 32, 1639 .qosbox = &(const struct qcom_icc_qosbox) { 1640 .num_ports = 1, 1641 .port_offsets = { 0x19000 }, 1642 .prio = 2, 1643 .urg_fwd = 0, 1644 .prio_fwd_disable = 1, 1645 }, 1646 .num_links = 1, 1647 .link_nodes = { &qns_pcie_hscnoc }, 1648 }; 1649 1650 static struct qcom_icc_node xm_pcie_2 = { 1651 .name = "xm_pcie_2", 1652 .channels = 1, 1653 .buswidth = 16, 1654 .qosbox = &(const struct qcom_icc_qosbox) { 1655 .num_ports = 1, 1656 .port_offsets = { 0x1a000 }, 1657 .prio = 2, 1658 .urg_fwd = 0, 1659 .prio_fwd_disable = 1, 1660 }, 1661 .num_links = 1, 1662 .link_nodes = { &qns_pcie_hscnoc }, 1663 }; 1664 1665 static struct qcom_icc_node xm_pcie_3 = { 1666 .name = "xm_pcie_3", 1667 .channels = 1, 1668 .buswidth = 8, 1669 .qosbox = &(const struct qcom_icc_qosbox) { 1670 .num_ports = 1, 1671 .port_offsets = { 0x1b000 }, 1672 .prio = 2, 1673 .urg_fwd = 0, 1674 .prio_fwd_disable = 1, 1675 }, 1676 .num_links = 1, 1677 .link_nodes = { &qns_pcie_hscnoc }, 1678 }; 1679 1680 static struct qcom_icc_node qnm_aggre1_noc = { 1681 .name = "qnm_aggre1_noc", 1682 .channels = 1, 1683 .buswidth = 16, 1684 .num_links = 1, 1685 .link_nodes = { &qns_hscnoc_sf }, 1686 }; 1687 1688 static struct qcom_icc_node qnm_aggre2_noc = { 1689 .name = "qnm_aggre2_noc", 1690 .channels = 1, 1691 .buswidth = 16, 1692 .num_links = 1, 1693 .link_nodes = { &qns_hscnoc_sf }, 1694 }; 1695 1696 static struct qcom_icc_node qnm_cnoc_data = { 1697 .name = "qnm_cnoc_data", 1698 .channels = 1, 1699 .buswidth = 8, 1700 .qosbox = &(const struct qcom_icc_qosbox) { 1701 .num_ports = 1, 1702 .port_offsets = { 0x1a000 }, 1703 .prio = 2, 1704 .urg_fwd = 0, 1705 .prio_fwd_disable = 1, 1706 }, 1707 .num_links = 1, 1708 .link_nodes = { &qns_hscnoc_sf }, 1709 }; 1710 1711 static struct qcom_icc_node qnm_nsi_noc = { 1712 .name = "qnm_nsi_noc", 1713 .channels = 1, 1714 .buswidth = 8, 1715 .qosbox = &(const struct qcom_icc_qosbox) { 1716 .num_ports = 1, 1717 .port_offsets = { 0x19000 }, 1718 .prio = 2, 1719 .urg_fwd = 0, 1720 .prio_fwd_disable = 1, 1721 }, 1722 .num_links = 1, 1723 .link_nodes = { &qns_hscnoc_sf }, 1724 }; 1725 1726 static struct qcom_icc_node qnm_safe_dma = { 1727 .name = "qnm_safe_dma", 1728 .channels = 1, 1729 .buswidth = 64, 1730 .qosbox = &(const struct qcom_icc_qosbox) { 1731 .num_ports = 1, 1732 .port_offsets = { 0x1b000 }, 1733 .prio = 0, 1734 .urg_fwd = 1, 1735 .prio_fwd_disable = 0, 1736 }, 1737 .num_links = 1, 1738 .link_nodes = { &qns_hscnoc_sf }, 1739 }; 1740 1741 static struct qcom_icc_node qns_a1noc_snoc = { 1742 .name = "qns_a1noc_snoc", 1743 .channels = 1, 1744 .buswidth = 16, 1745 .num_links = 1, 1746 .link_nodes = { &qnm_aggre1_noc }, 1747 }; 1748 1749 static struct qcom_icc_node qns_a2noc_snoc = { 1750 .name = "qns_a2noc_snoc", 1751 .channels = 1, 1752 .buswidth = 16, 1753 .num_links = 1, 1754 .link_nodes = { &qnm_aggre2_noc }, 1755 }; 1756 1757 static struct qcom_icc_node qhm_qspi = { 1758 .name = "qhm_qspi", 1759 .channels = 1, 1760 .buswidth = 4, 1761 .qosbox = &(const struct qcom_icc_qosbox) { 1762 .num_ports = 1, 1763 .port_offsets = { 0x18000 }, 1764 .prio = 2, 1765 .urg_fwd = 0, 1766 .prio_fwd_disable = 1, 1767 }, 1768 .num_links = 1, 1769 .link_nodes = { &qns_a1noc_snoc }, 1770 }; 1771 1772 static struct qcom_icc_node qnm_sailss_md1 = { 1773 .name = "qnm_sailss_md1", 1774 .channels = 1, 1775 .buswidth = 8, 1776 .qosbox = &(const struct qcom_icc_qosbox) { 1777 .num_ports = 1, 1778 .port_offsets = { 0x16000 }, 1779 .prio = 2, 1780 .urg_fwd = 1, 1781 .prio_fwd_disable = 1, 1782 }, 1783 .num_links = 1, 1784 .link_nodes = { &qns_a1noc_snoc }, 1785 }; 1786 1787 static struct qcom_icc_node qxm_qup3 = { 1788 .name = "qxm_qup3", 1789 .channels = 1, 1790 .buswidth = 8, 1791 .qosbox = &(const struct qcom_icc_qosbox) { 1792 .num_ports = 1, 1793 .port_offsets = { 0x17000 }, 1794 .prio = 2, 1795 .urg_fwd = 1, 1796 .prio_fwd_disable = 1, 1797 }, 1798 .num_links = 1, 1799 .link_nodes = { &qns_a1noc_snoc }, 1800 }; 1801 1802 static struct qcom_icc_node qxm_ipa = { 1803 .name = "qxm_ipa", 1804 .channels = 1, 1805 .buswidth = 8, 1806 .qosbox = &(const struct qcom_icc_qosbox) { 1807 .num_ports = 1, 1808 .port_offsets = { 0x13000 }, 1809 .prio = 2, 1810 .urg_fwd = 1, 1811 .prio_fwd_disable = 1, 1812 }, 1813 .num_links = 1, 1814 .link_nodes = { &qns_a2noc_snoc }, 1815 }; 1816 1817 static struct qcom_icc_node qxm_soccp = { 1818 .name = "qxm_soccp", 1819 .channels = 1, 1820 .buswidth = 8, 1821 .qosbox = &(const struct qcom_icc_qosbox) { 1822 .num_ports = 1, 1823 .port_offsets = { 0x16000 }, 1824 .prio = 2, 1825 .urg_fwd = 1, 1826 .prio_fwd_disable = 1, 1827 }, 1828 .num_links = 1, 1829 .link_nodes = { &qns_a2noc_snoc }, 1830 }; 1831 1832 static struct qcom_icc_node xm_qdss_etr_0 = { 1833 .name = "xm_qdss_etr_0", 1834 .channels = 1, 1835 .buswidth = 8, 1836 .qosbox = &(const struct qcom_icc_qosbox) { 1837 .num_ports = 1, 1838 .port_offsets = { 0x14000 }, 1839 .prio = 2, 1840 .urg_fwd = 0, 1841 .prio_fwd_disable = 1, 1842 }, 1843 .num_links = 1, 1844 .link_nodes = { &qns_a2noc_snoc }, 1845 }; 1846 1847 static struct qcom_icc_node xm_qdss_etr_1 = { 1848 .name = "xm_qdss_etr_1", 1849 .channels = 1, 1850 .buswidth = 8, 1851 .qosbox = &(const struct qcom_icc_qosbox) { 1852 .num_ports = 1, 1853 .port_offsets = { 0x15000 }, 1854 .prio = 2, 1855 .urg_fwd = 0, 1856 .prio_fwd_disable = 1, 1857 }, 1858 .num_links = 1, 1859 .link_nodes = { &qns_a2noc_snoc }, 1860 }; 1861 1862 static struct qcom_icc_bcm bcm_c0n0 = { 1863 .name = "C0N0", 1864 .enable_mask = BIT(0), 1865 .num_nodes = 2, 1866 .nodes = { &qnm_nsp_data00, &qns_nsp0_hsc_noc }, 1867 }; 1868 1869 static struct qcom_icc_bcm bcm_c1n0 = { 1870 .name = "C1N0", 1871 .enable_mask = BIT(0), 1872 .num_nodes = 2, 1873 .nodes = { &qnm_nsp_data01, &qns_nsp1_hsc_noc }, 1874 }; 1875 1876 static struct qcom_icc_bcm bcm_c2n0 = { 1877 .name = "C2N0", 1878 .enable_mask = BIT(0), 1879 .num_nodes = 2, 1880 .nodes = { &qnm_nsp_data02, &qns_nsp2_hsc_noc }, 1881 }; 1882 1883 static struct qcom_icc_bcm bcm_c3n0 = { 1884 .name = "C3N0", 1885 .enable_mask = BIT(0), 1886 .num_nodes = 2, 1887 .nodes = { &qnm_nsp_data03, &qns_nsp3_hsc_noc }, 1888 }; 1889 1890 static struct qcom_icc_bcm bcm_ce0 = { 1891 .name = "CE0", 1892 .num_nodes = 1, 1893 .nodes = { &qxm_crypto_0 }, 1894 }; 1895 1896 static struct qcom_icc_bcm bcm_ce1 = { 1897 .name = "CE1", 1898 .num_nodes = 1, 1899 .nodes = { &qxm_crypto_1 }, 1900 }; 1901 1902 static struct qcom_icc_bcm bcm_ce2 = { 1903 .name = "CE2", 1904 .num_nodes = 1, 1905 .nodes = { &qxm_crypto_2 }, 1906 }; 1907 1908 static struct qcom_icc_bcm bcm_cn0 = { 1909 .name = "CN0", 1910 .keepalive = true, 1911 .enable_mask = BIT(0), 1912 .num_nodes = 6, 1913 .nodes = { &qsm_cfg, &qhm_mm_rscc, 1914 &qnm_hscnoc, &qnm_cnoc_pcie_dma, 1915 &qnm_hscnoc_pcie, &qnm_pcie_ibnoc_dma }, 1916 }; 1917 1918 static struct qcom_icc_bcm bcm_cn1 = { 1919 .name = "CN1", 1920 .num_nodes = 2, 1921 .nodes = { &qhs_display_1_cfg, &qhs_display_cfg }, 1922 }; 1923 1924 static struct qcom_icc_bcm bcm_mc0 = { 1925 .name = "MC0", 1926 .keepalive = true, 1927 .num_nodes = 1, 1928 .nodes = { &ebi }, 1929 }; 1930 1931 static struct qcom_icc_bcm bcm_mm0 = { 1932 .name = "MM0", 1933 .num_nodes = 1, 1934 .nodes = { &qns_mem_noc_hf }, 1935 }; 1936 1937 static struct qcom_icc_bcm bcm_mm1 = { 1938 .name = "MM1", 1939 .enable_mask = BIT(0), 1940 .num_nodes = 14, 1941 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, 1942 &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, 1943 &qnm_dprx0, &qnm_dprx1, 1944 &qnm_mdp0, &qnm_mdp1, 1945 &qnm_video_cv_cpu, &qnm_video_eva, 1946 &qnm_video_mvp0, &qnm_video_mvp1, 1947 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1948 }; 1949 1950 static struct qcom_icc_bcm bcm_qup0 = { 1951 .name = "QUP0", 1952 .vote_scale = 1, 1953 .keepalive = true, 1954 .num_nodes = 1, 1955 .nodes = { &qup0_core_slave }, 1956 }; 1957 1958 static struct qcom_icc_bcm bcm_qup1 = { 1959 .name = "QUP1", 1960 .vote_scale = 1, 1961 .keepalive = true, 1962 .num_nodes = 1, 1963 .nodes = { &qup1_core_slave }, 1964 }; 1965 1966 static struct qcom_icc_bcm bcm_qup2 = { 1967 .name = "QUP2", 1968 .vote_scale = 1, 1969 .keepalive = true, 1970 .num_nodes = 1, 1971 .nodes = { &qup2_core_slave }, 1972 }; 1973 1974 static struct qcom_icc_bcm bcm_qup3 = { 1975 .name = "QUP3", 1976 .vote_scale = 1, 1977 .keepalive = true, 1978 .num_nodes = 1, 1979 .nodes = { &qup3_core_slave }, 1980 }; 1981 1982 static struct qcom_icc_bcm bcm_sh0 = { 1983 .name = "SH0", 1984 .keepalive = true, 1985 .num_nodes = 1, 1986 .nodes = { &qns_llcc }, 1987 }; 1988 1989 static struct qcom_icc_bcm bcm_sh1 = { 1990 .name = "SH1", 1991 .enable_mask = BIT(0), 1992 .num_nodes = 24, 1993 .nodes = { &alm_gpu_tcu, &alm_qtc, 1994 &alm_sys_tcu0, &alm_sys_tcu1, 1995 &alm_sys_tcu2, &chm_apps, 1996 &qnm_aggre_north, &qnm_aggre_south, 1997 &qnm_gpu0, &qnm_gpu1, 1998 &qnm_hpass_adas_hscnoc, &qnm_hpass_audio_hscnoc, 1999 &qnm_mnoc_hf, &qnm_mnoc_sf, 2000 &qnm_nsp0_hscnoc, &qnm_nsp1_hscnoc, 2001 &qnm_nsp2_hscnoc, &qnm_nsp3_hscnoc, 2002 &qnm_pcie, &qnm_sailss_md0_hscnoc, 2003 &qnm_snoc_sf, &xm_gic, 2004 &qns_hscnoc_cnoc, &qns_pcie }, 2005 }; 2006 2007 static struct qcom_icc_bcm bcm_sn0 = { 2008 .name = "SN0", 2009 .keepalive = true, 2010 .num_nodes = 1, 2011 .nodes = { &qns_hscnoc_sf }, 2012 }; 2013 2014 static struct qcom_icc_bcm bcm_sn1 = { 2015 .name = "SN1", 2016 .enable_mask = BIT(0), 2017 .num_nodes = 14, 2018 .nodes = { &qns_a1noc_hscnoc, &qns_a2noc_hscnoc, 2019 &qxm_pcie_dma_0, &qxm_pcie_dma_1, 2020 &qxm_pcie_dma_2, &xm_pcie_0, 2021 &xm_pcie_1, &xm_pcie_2, 2022 &xm_pcie_3, &qns_pcie_hscnoc, 2023 &qns_pcie_obnoc_dma, &qnm_cnoc_data, 2024 &qnm_nsi_noc, &qnm_safe_dma }, 2025 }; 2026 2027 static struct qcom_icc_bcm bcm_sn2 = { 2028 .name = "SN2", 2029 .num_nodes = 1, 2030 .nodes = { &qnm_aggre1_noc }, 2031 }; 2032 2033 static struct qcom_icc_bcm bcm_sn3 = { 2034 .name = "SN3", 2035 .num_nodes = 1, 2036 .nodes = { &qnm_aggre2_noc }, 2037 }; 2038 2039 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 2040 [MASTER_QSPI_0] = &qhm_qspi, 2041 [MASTER_SAILSS_MD1] = &qnm_sailss_md1, 2042 [MASTER_QUP_3] = &qxm_qup3, 2043 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 2044 }; 2045 2046 static const struct regmap_config nord_aggre1_noc_regmap_config = { 2047 .reg_bits = 32, 2048 .reg_stride = 4, 2049 .val_bits = 32, 2050 .max_register = 0x1c400, 2051 .fast_io = true, 2052 }; 2053 2054 static const struct qcom_icc_desc nord_aggre1_noc = { 2055 .config = &nord_aggre1_noc_regmap_config, 2056 .nodes = aggre1_noc_nodes, 2057 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2058 }; 2059 2060 static struct qcom_icc_bcm * const aggre1_noc_tile_bcms[] = { 2061 &bcm_ce0, 2062 &bcm_ce1, 2063 &bcm_ce2, 2064 &bcm_sn1, 2065 }; 2066 2067 static struct qcom_icc_node * const aggre1_noc_tile_nodes[] = { 2068 [MASTER_QUP_2] = &qhm_qup2, 2069 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0, 2070 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1, 2071 [MASTER_CRYPTO_CORE2] = &qxm_crypto_2, 2072 [MASTER_SDCC_4] = &xm_sdc4, 2073 [MASTER_UFS_MEM] = &xm_ufs_mem, 2074 [MASTER_USB2] = &xm_usb2, 2075 [MASTER_USB3_0] = &xm_usb3_0, 2076 [MASTER_USB3_1] = &xm_usb3_1, 2077 [SLAVE_A1NOC_HSCNOC] = &qns_a1noc_hscnoc, 2078 }; 2079 2080 static const struct regmap_config nord_aggre1_noc_tile_regmap_config = { 2081 .reg_bits = 32, 2082 .reg_stride = 4, 2083 .val_bits = 32, 2084 .max_register = 0x23400, 2085 .fast_io = true, 2086 }; 2087 2088 static const struct qcom_icc_desc nord_aggre1_noc_tile = { 2089 .config = &nord_aggre1_noc_tile_regmap_config, 2090 .nodes = aggre1_noc_tile_nodes, 2091 .num_nodes = ARRAY_SIZE(aggre1_noc_tile_nodes), 2092 .bcms = aggre1_noc_tile_bcms, 2093 .num_bcms = ARRAY_SIZE(aggre1_noc_tile_bcms), 2094 }; 2095 2096 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 2097 [MASTER_IPA] = &qxm_ipa, 2098 [MASTER_SOCCP_AGGR_NOC] = &qxm_soccp, 2099 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 2100 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 2101 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2102 }; 2103 2104 static const struct regmap_config nord_aggre2_noc_regmap_config = { 2105 .reg_bits = 32, 2106 .reg_stride = 4, 2107 .val_bits = 32, 2108 .max_register = 0x1b400, 2109 .fast_io = true, 2110 }; 2111 2112 static const struct qcom_icc_desc nord_aggre2_noc = { 2113 .config = &nord_aggre2_noc_regmap_config, 2114 .nodes = aggre2_noc_nodes, 2115 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2116 }; 2117 2118 static struct qcom_icc_bcm * const aggre2_noc_tile_bcms[] = { 2119 &bcm_sn1, 2120 }; 2121 2122 static struct qcom_icc_node * const aggre2_noc_tile_nodes[] = { 2123 [MASTER_QUP_0] = &qhm_qup0, 2124 [MASTER_QUP_1] = &qhm_qup1, 2125 [MASTER_EMAC_0] = &xm_emac_0, 2126 [MASTER_EMAC_1] = &xm_emac_1, 2127 [SLAVE_A2NOC_HSCNOC] = &qns_a2noc_hscnoc, 2128 }; 2129 2130 static const struct regmap_config nord_aggre2_noc_tile_regmap_config = { 2131 .reg_bits = 32, 2132 .reg_stride = 4, 2133 .val_bits = 32, 2134 .max_register = 0x1b400, 2135 .fast_io = true, 2136 }; 2137 2138 static const struct qcom_icc_desc nord_aggre2_noc_tile = { 2139 .config = &nord_aggre2_noc_tile_regmap_config, 2140 .nodes = aggre2_noc_tile_nodes, 2141 .num_nodes = ARRAY_SIZE(aggre2_noc_tile_nodes), 2142 .bcms = aggre2_noc_tile_bcms, 2143 .num_bcms = ARRAY_SIZE(aggre2_noc_tile_bcms), 2144 }; 2145 2146 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 2147 &bcm_qup0, 2148 &bcm_qup1, 2149 &bcm_qup2, 2150 &bcm_qup3, 2151 }; 2152 2153 static struct qcom_icc_node * const clk_virt_nodes[] = { 2154 [MASTER_QUP_CORE_0] = &qup0_core_master, 2155 [MASTER_QUP_CORE_1] = &qup1_core_master, 2156 [MASTER_QUP_CORE_2] = &qup2_core_master, 2157 [MASTER_QUP_CORE_3] = &qup3_core_master, 2158 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2159 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2160 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2161 [SLAVE_QUP_CORE_3] = &qup3_core_slave, 2162 }; 2163 2164 static const struct qcom_icc_desc nord_clk_virt = { 2165 .nodes = clk_virt_nodes, 2166 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2167 .bcms = clk_virt_bcms, 2168 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2169 }; 2170 2171 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 2172 &bcm_cn0, 2173 &bcm_cn1, 2174 }; 2175 2176 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 2177 [MASTER_CNOC_CFG] = &qsm_cfg, 2178 [SLAVE_PS_ETH_0] = &ps_eth_0, 2179 [SLAVE_PS_ETH_1] = &ps_eth_1, 2180 [SLAVE_SHS_SERVER] = &ps_shs_server, 2181 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2182 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2183 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2184 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, 2185 [SLAVE_AHB2PHY_ETH_0] = &qhs_ahb2phy_eth_0, 2186 [SLAVE_AHB2PHY_ETH_1] = &qhs_ahb2phy_eth_1, 2187 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2188 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2189 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2190 [SLAVE_CRYPTO_1_CFG] = &qhs_crypto1_cfg, 2191 [SLAVE_CRYPTO_2_CFG] = &qhs_crypto2_cfg, 2192 [SLAVE_DISPLAY_1_CFG] = &qhs_display_1_cfg, 2193 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 2194 [SLAVE_DPRX0] = &qhs_dprx0, 2195 [SLAVE_DPRX1] = &qhs_dprx1, 2196 [SLAVE_EVA_CFG] = &qhs_eva_cfg, 2197 [SLAVE_GFX3D_CFG] = &qhs_gpuss_0_cfg, 2198 [SLAVE_GFX3D_1_CFG] = &qhs_gpuss_1_cfg, 2199 [SLAVE_I2C] = &qhs_i2c, 2200 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2201 [SLAVE_MCW_PCIE] = &qhs_mcw_pcie, 2202 [SLAVE_MM_RSCC] = &qhs_mm_rscc, 2203 [SLAVE_NE_CLK_CTL] = &qhs_ne_clk_ctl, 2204 [SLAVE_NSPSS0_CFG] = &qhs_nspss0_cfg, 2205 [SLAVE_NSPSS1_CFG] = &qhs_nspss1_cfg, 2206 [SLAVE_NSPSS2_CFG] = &qhs_nspss2_cfg, 2207 [SLAVE_NSPSS3_CFG] = &qhs_nspss3_cfg, 2208 [SLAVE_NW_CLK_CTL] = &qhs_nw_clk_ctl, 2209 [SLAVE_PRNG] = &qhs_prng, 2210 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2211 [SLAVE_QSPI_0] = &qhs_qspi, 2212 [SLAVE_QUP_0] = &qhs_qup0, 2213 [SLAVE_QUP_3] = &qhs_qup3, 2214 [SLAVE_QUP_1] = &qhs_qup1, 2215 [SLAVE_QUP_2] = &qhs_qup2, 2216 [SLAVE_SAFEDMA_CFG] = &qhs_safedma_cfg, 2217 [SLAVE_SDCC_4] = &qhs_sdc4, 2218 [SLAVE_SE_CLK_CTL] = &qhs_se_clk_ctl, 2219 [SLAVE_TCSR] = &qhs_tcsr, 2220 [SLAVE_TLMM] = &qhs_tlmm, 2221 [SLAVE_TSC_CFG] = &qhs_tsc_cfg, 2222 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2223 [SLAVE_USB2] = &qhs_usb2, 2224 [SLAVE_USB3_0] = &qhs_usb3_0, 2225 [SLAVE_USB3_1] = &qhs_usb3_1, 2226 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2227 [SLAVE_COMPUTENOC_CFG] = &qss_computenoc_cfg, 2228 [SLAVE_PCIE_NOC_CFG] = &qss_pcie_noc_cfg, 2229 [SLAVE_QTC_CFG] = &qss_qtc_cfg, 2230 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2231 [SLAVE_SYS_TCU0_CFG] = &xs_sys_tcu0_cfg, 2232 [SLAVE_SYS_TCU1_CFG] = &xs_sys_tcu1_cfg, 2233 [SLAVE_SYS_TCU2_CFG] = &xs_sys_tcu2_cfg, 2234 }; 2235 2236 static const struct regmap_config nord_cnoc_cfg_regmap_config = { 2237 .reg_bits = 32, 2238 .reg_stride = 4, 2239 .val_bits = 32, 2240 .max_register = 0xd200, 2241 .fast_io = true, 2242 }; 2243 2244 static const struct qcom_icc_desc nord_cnoc_cfg = { 2245 .config = &nord_cnoc_cfg_regmap_config, 2246 .nodes = cnoc_cfg_nodes, 2247 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 2248 .bcms = cnoc_cfg_bcms, 2249 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 2250 }; 2251 2252 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 2253 &bcm_cn0, 2254 }; 2255 2256 static struct qcom_icc_node * const cnoc_main_nodes[] = { 2257 [MASTER_MM_RSCC] = &qhm_mm_rscc, 2258 [MASTER_HSCNOC_CNOC] = &qnm_hscnoc, 2259 [SLAVE_AOSS] = &qhs_aoss, 2260 [SLAVE_HBCU] = &qhs_hbcu, 2261 [SLAVE_IPA_CFG] = &qhs_ipa, 2262 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2263 [SLAVE_SOCCP] = &qhs_soccp, 2264 [SLAVE_TME_CFG] = &qhs_tme_cfg, 2265 [SLAVE_PCIE_DMA] = &qns_pcie_dma, 2266 [SLAVE_CNOC_CFG] = &qss_cfg, 2267 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 2268 [SLAVE_IMEM] = &qxs_imem, 2269 }; 2270 2271 static const struct regmap_config nord_cnoc_main_regmap_config = { 2272 .reg_bits = 32, 2273 .reg_stride = 4, 2274 .val_bits = 32, 2275 .max_register = 0x1d200, 2276 .fast_io = true, 2277 }; 2278 2279 static const struct qcom_icc_desc nord_cnoc_main = { 2280 .config = &nord_cnoc_main_regmap_config, 2281 .nodes = cnoc_main_nodes, 2282 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 2283 .bcms = cnoc_main_bcms, 2284 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 2285 }; 2286 2287 static struct qcom_icc_node * const hpass_ag_noc_nodes[] = { 2288 [MASTER_HPASS_PROC_0] = &qnm_hpass_dsp0, 2289 [MASTER_HPASS_PROC_1] = &qnm_hpass_dsp1, 2290 [MASTER_HPASS_PROC_2] = &qnm_hpass_dsp2, 2291 [SLAVE_HPASS_AGNOC_AUDIO] = &qns_hpass_agnoc_audio, 2292 }; 2293 2294 static const struct regmap_config nord_hpass_ag_noc_regmap_config = { 2295 .reg_bits = 32, 2296 .reg_stride = 4, 2297 .val_bits = 32, 2298 .max_register = 0x37080, 2299 .fast_io = true, 2300 }; 2301 2302 static const struct qcom_icc_desc nord_hpass_ag_noc = { 2303 .config = &nord_hpass_ag_noc_regmap_config, 2304 .nodes = hpass_ag_noc_nodes, 2305 .num_nodes = ARRAY_SIZE(hpass_ag_noc_nodes), 2306 }; 2307 2308 static struct qcom_icc_bcm * const hscnoc_bcms[] = { 2309 &bcm_sh0, 2310 &bcm_sh1, 2311 }; 2312 2313 static struct qcom_icc_node * const hscnoc_nodes[] = { 2314 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2315 [MASTER_QTC_TCU] = &alm_qtc, 2316 [MASTER_SYS_TCU_0] = &alm_sys_tcu0, 2317 [MASTER_SYS_TCU_1] = &alm_sys_tcu1, 2318 [MASTER_SYS_TCU_2] = &alm_sys_tcu2, 2319 [MASTER_APPSS_PROC] = &chm_apps, 2320 [MASTER_A1NOC_TILE_HSCNOC] = &qnm_aggre_north, 2321 [MASTER_A2NOC_TILE_HSCNOC] = &qnm_aggre_south, 2322 [MASTER_GFX3D] = &qnm_gpu0, 2323 [MASTER_GFX3D_1] = &qnm_gpu1, 2324 [MASTER_HPASS_ADAS_HSCNOC] = &qnm_hpass_adas_hscnoc, 2325 [MASTER_HPASS_AUDIO_HSCNOC] = &qnm_hpass_audio_hscnoc, 2326 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2327 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2328 [MASTER_NSP0_HSCNOC] = &qnm_nsp0_hscnoc, 2329 [MASTER_NSP1_HSCNOC] = &qnm_nsp1_hscnoc, 2330 [MASTER_NSP2_HSCNOC] = &qnm_nsp2_hscnoc, 2331 [MASTER_NSP3_HSCNOC] = &qnm_nsp3_hscnoc, 2332 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2333 [MASTER_SAILSS_MD0_HSCNOC] = &qnm_sailss_md0_hscnoc, 2334 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2335 [MASTER_GIC] = &xm_gic, 2336 [SLAVE_HSCNOC_CNOC] = &qns_hscnoc_cnoc, 2337 [SLAVE_LLCC] = &qns_llcc, 2338 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 2339 }; 2340 2341 static const struct regmap_config nord_hscnoc_regmap_config = { 2342 .reg_bits = 32, 2343 .reg_stride = 4, 2344 .val_bits = 32, 2345 .max_register = 0xa45080, 2346 .fast_io = true, 2347 }; 2348 2349 static const struct qcom_icc_desc nord_hscnoc = { 2350 .config = &nord_hscnoc_regmap_config, 2351 .nodes = hscnoc_nodes, 2352 .num_nodes = ARRAY_SIZE(hscnoc_nodes), 2353 .bcms = hscnoc_bcms, 2354 .num_bcms = ARRAY_SIZE(hscnoc_bcms), 2355 }; 2356 2357 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2358 &bcm_mc0, 2359 }; 2360 2361 static struct qcom_icc_node * const mc_virt_nodes[] = { 2362 [MASTER_LLCC] = &llcc_mc, 2363 [SLAVE_EBI1] = &ebi, 2364 }; 2365 2366 static const struct qcom_icc_desc nord_mc_virt = { 2367 .nodes = mc_virt_nodes, 2368 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2369 .bcms = mc_virt_bcms, 2370 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2371 }; 2372 2373 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2374 &bcm_mm0, 2375 &bcm_mm1, 2376 }; 2377 2378 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2379 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2380 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, 2381 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, 2382 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 2383 [MASTER_DPRX0] = &qnm_dprx0, 2384 [MASTER_DPRX1] = &qnm_dprx1, 2385 [MASTER_MDP0] = &qnm_mdp0, 2386 [MASTER_MDP1] = &qnm_mdp1, 2387 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 2388 [MASTER_VIDEO_EVA] = &qnm_video_eva, 2389 [MASTER_VIDEO_MVP0] = &qnm_video_mvp0, 2390 [MASTER_VIDEO_MVP1] = &qnm_video_mvp1, 2391 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 2392 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2393 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2394 }; 2395 2396 static const struct regmap_config nord_mmss_noc_regmap_config = { 2397 .reg_bits = 32, 2398 .reg_stride = 4, 2399 .val_bits = 32, 2400 .max_register = 0x72800, 2401 .fast_io = true, 2402 }; 2403 2404 static const struct qcom_icc_desc nord_mmss_noc = { 2405 .config = &nord_mmss_noc_regmap_config, 2406 .nodes = mmss_noc_nodes, 2407 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2408 .bcms = mmss_noc_bcms, 2409 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2410 }; 2411 2412 static struct qcom_icc_bcm * const nsp_data_noc_0_bcms[] = { 2413 &bcm_c0n0, 2414 }; 2415 2416 static struct qcom_icc_node * const nsp_data_noc_0_nodes[] = { 2417 [MASTER_NSP0_PROC] = &qnm_nsp_data00, 2418 [SLAVE_NSP0_HSC_NOC] = &qns_nsp0_hsc_noc, 2419 }; 2420 2421 static const struct regmap_config nord_nsp_data_noc_0_regmap_config = { 2422 .reg_bits = 32, 2423 .reg_stride = 4, 2424 .val_bits = 32, 2425 .max_register = 0x2a200, 2426 .fast_io = true, 2427 }; 2428 2429 static const struct qcom_icc_desc nord_nsp_data_noc_0 = { 2430 .config = &nord_nsp_data_noc_0_regmap_config, 2431 .nodes = nsp_data_noc_0_nodes, 2432 .num_nodes = ARRAY_SIZE(nsp_data_noc_0_nodes), 2433 .bcms = nsp_data_noc_0_bcms, 2434 .num_bcms = ARRAY_SIZE(nsp_data_noc_0_bcms), 2435 }; 2436 2437 static struct qcom_icc_bcm * const nsp_data_noc_1_bcms[] = { 2438 &bcm_c1n0, 2439 }; 2440 2441 static struct qcom_icc_node * const nsp_data_noc_1_nodes[] = { 2442 [MASTER_NSP1_PROC] = &qnm_nsp_data01, 2443 [SLAVE_NSP1_HSC_NOC] = &qns_nsp1_hsc_noc, 2444 }; 2445 2446 static const struct regmap_config nord_nsp_data_noc_1_regmap_config = { 2447 .reg_bits = 32, 2448 .reg_stride = 4, 2449 .val_bits = 32, 2450 .max_register = 0x2a200, 2451 .fast_io = true, 2452 }; 2453 2454 static const struct qcom_icc_desc nord_nsp_data_noc_1 = { 2455 .config = &nord_nsp_data_noc_1_regmap_config, 2456 .nodes = nsp_data_noc_1_nodes, 2457 .num_nodes = ARRAY_SIZE(nsp_data_noc_1_nodes), 2458 .bcms = nsp_data_noc_1_bcms, 2459 .num_bcms = ARRAY_SIZE(nsp_data_noc_1_bcms), 2460 }; 2461 2462 static struct qcom_icc_bcm * const nsp_data_noc_2_bcms[] = { 2463 &bcm_c2n0, 2464 }; 2465 2466 static struct qcom_icc_node * const nsp_data_noc_2_nodes[] = { 2467 [MASTER_NSP2_PROC] = &qnm_nsp_data02, 2468 [SLAVE_NSP2_HSC_NOC] = &qns_nsp2_hsc_noc, 2469 }; 2470 2471 static const struct regmap_config nord_nsp_data_noc_2_regmap_config = { 2472 .reg_bits = 32, 2473 .reg_stride = 4, 2474 .val_bits = 32, 2475 .max_register = 0x2a200, 2476 .fast_io = true, 2477 }; 2478 2479 static const struct qcom_icc_desc nord_nsp_data_noc_2 = { 2480 .config = &nord_nsp_data_noc_2_regmap_config, 2481 .nodes = nsp_data_noc_2_nodes, 2482 .num_nodes = ARRAY_SIZE(nsp_data_noc_2_nodes), 2483 .bcms = nsp_data_noc_2_bcms, 2484 .num_bcms = ARRAY_SIZE(nsp_data_noc_2_bcms), 2485 }; 2486 2487 static struct qcom_icc_bcm * const nsp_data_noc_3_bcms[] = { 2488 &bcm_c3n0, 2489 }; 2490 2491 static struct qcom_icc_node * const nsp_data_noc_3_nodes[] = { 2492 [MASTER_NSP3_PROC] = &qnm_nsp_data03, 2493 [SLAVE_NSP3_HSC_NOC] = &qns_nsp3_hsc_noc, 2494 }; 2495 2496 static const struct regmap_config nord_nsp_data_noc_3_regmap_config = { 2497 .reg_bits = 32, 2498 .reg_stride = 4, 2499 .val_bits = 32, 2500 .max_register = 0x2a200, 2501 .fast_io = true, 2502 }; 2503 2504 static const struct qcom_icc_desc nord_nsp_data_noc_3 = { 2505 .config = &nord_nsp_data_noc_3_regmap_config, 2506 .nodes = nsp_data_noc_3_nodes, 2507 .num_nodes = ARRAY_SIZE(nsp_data_noc_3_nodes), 2508 .bcms = nsp_data_noc_3_bcms, 2509 .num_bcms = ARRAY_SIZE(nsp_data_noc_3_bcms), 2510 }; 2511 2512 static struct qcom_icc_node * const pcie_cfg_nodes[] = { 2513 [MASTER_PCIE_NOC_CFG] = &qsm_pcie_noc_cfg, 2514 [SLAVE_PCIE_AHB2PHY_CFG] = &qhs_pcie_ahb2phy_cfg, 2515 [SLAVE_PCIE_CFG_0] = &qhs_pcie_cfg_0, 2516 [SLAVE_PCIE_CFG_1] = &qhs_pcie_cfg_1, 2517 [SLAVE_PCIE_CFG_2] = &qhs_pcie_cfg_2, 2518 [SLAVE_PCIE_CFG_3] = &qhs_pcie_cfg_3, 2519 [SLAVE_PCIE_DMA_0_CFG] = &qhs_pcie_dma_0_cfg, 2520 [SLAVE_PCIE_DMA_1_CFG] = &qhs_pcie_dma_1_cfg, 2521 [SLAVE_PCIE_DMA_2_CFG] = &qhs_pcie_dma_2_cfg, 2522 }; 2523 2524 static const struct regmap_config nord_pcie_cfg_regmap_config = { 2525 .reg_bits = 32, 2526 .reg_stride = 4, 2527 .val_bits = 32, 2528 .max_register = 0x7200, 2529 .fast_io = true, 2530 }; 2531 2532 static const struct qcom_icc_desc nord_pcie_cfg = { 2533 .config = &nord_pcie_cfg_regmap_config, 2534 .nodes = pcie_cfg_nodes, 2535 .num_nodes = ARRAY_SIZE(pcie_cfg_nodes), 2536 }; 2537 2538 static struct qcom_icc_bcm * const pcie_data_inbound_bcms[] = { 2539 &bcm_sn1, 2540 }; 2541 2542 static struct qcom_icc_node * const pcie_data_inbound_nodes[] = { 2543 [MASTER_PCIE_DMA_0] = &qxm_pcie_dma_0, 2544 [MASTER_PCIE_DMA_1] = &qxm_pcie_dma_1, 2545 [MASTER_PCIE_DMA_2] = &qxm_pcie_dma_2, 2546 [MASTER_PCIE_0] = &xm_pcie_0, 2547 [MASTER_PCIE_1] = &xm_pcie_1, 2548 [MASTER_PCIE_2] = &xm_pcie_2, 2549 [MASTER_PCIE_3] = &xm_pcie_3, 2550 [SLAVE_PCIE_HSCNOC] = &qns_pcie_hscnoc, 2551 [SLAVE_PCIE_OBNOC_DMA] = &qns_pcie_obnoc_dma, 2552 }; 2553 2554 static const struct regmap_config nord_pcie_data_inbound_regmap_config = { 2555 .reg_bits = 32, 2556 .reg_stride = 4, 2557 .val_bits = 32, 2558 .max_register = 0x4b080, 2559 .fast_io = true, 2560 }; 2561 2562 static const struct qcom_icc_desc nord_pcie_data_inbound = { 2563 .config = &nord_pcie_data_inbound_regmap_config, 2564 .nodes = pcie_data_inbound_nodes, 2565 .num_nodes = ARRAY_SIZE(pcie_data_inbound_nodes), 2566 .bcms = pcie_data_inbound_bcms, 2567 .num_bcms = ARRAY_SIZE(pcie_data_inbound_bcms), 2568 }; 2569 2570 static struct qcom_icc_bcm * const pcie_data_outbound_bcms[] = { 2571 &bcm_cn0, 2572 }; 2573 2574 static struct qcom_icc_node * const pcie_data_outbound_nodes[] = { 2575 [MASTER_CNOC_PCIE_DMA] = &qnm_cnoc_pcie_dma, 2576 [MASTER_ANOC_PCIE_HSCNOC] = &qnm_hscnoc_pcie, 2577 [MASTER_PCIE_IBNOC_DMA] = &qnm_pcie_ibnoc_dma, 2578 [SLAVE_PCIE_DMA_0] = &qxs_pcie_dma_0, 2579 [SLAVE_PCIE_DMA_1] = &qxs_pcie_dma_1, 2580 [SLAVE_PCIE_DMA_2] = &qxs_pcie_dma_2, 2581 [SLAVE_PCIE_0] = &xs_pcie_0, 2582 [SLAVE_PCIE_1] = &xs_pcie_1, 2583 [SLAVE_PCIE_2] = &xs_pcie_2, 2584 [SLAVE_PCIE_3] = &xs_pcie_3, 2585 }; 2586 2587 static const struct regmap_config nord_pcie_data_outbound_regmap_config = { 2588 .reg_bits = 32, 2589 .reg_stride = 4, 2590 .val_bits = 32, 2591 .max_register = 0x17000, 2592 .fast_io = true, 2593 }; 2594 2595 static const struct qcom_icc_desc nord_pcie_data_outbound = { 2596 .config = &nord_pcie_data_outbound_regmap_config, 2597 .nodes = pcie_data_outbound_nodes, 2598 .num_nodes = ARRAY_SIZE(pcie_data_outbound_nodes), 2599 .bcms = pcie_data_outbound_bcms, 2600 .num_bcms = ARRAY_SIZE(pcie_data_outbound_bcms), 2601 }; 2602 2603 static struct qcom_icc_bcm * const system_noc_bcms[] = { 2604 &bcm_sn0, 2605 &bcm_sn1, 2606 &bcm_sn2, 2607 &bcm_sn3, 2608 }; 2609 2610 static struct qcom_icc_node * const system_noc_nodes[] = { 2611 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2612 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2613 [MASTER_CNOC_SNOC] = &qnm_cnoc_data, 2614 [MASTER_NSINOC_SNOC] = &qnm_nsi_noc, 2615 [MASTER_SAFE_DMA] = &qnm_safe_dma, 2616 [SLAVE_SNOC_HSCNOC_SF] = &qns_hscnoc_sf, 2617 }; 2618 2619 static const struct regmap_config nord_system_noc_regmap_config = { 2620 .reg_bits = 32, 2621 .reg_stride = 4, 2622 .val_bits = 32, 2623 .max_register = 0x1c080, 2624 .fast_io = true, 2625 }; 2626 2627 static const struct qcom_icc_desc nord_system_noc = { 2628 .config = &nord_system_noc_regmap_config, 2629 .nodes = system_noc_nodes, 2630 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2631 .bcms = system_noc_bcms, 2632 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2633 }; 2634 2635 static const struct of_device_id qnoc_of_match[] = { 2636 { .compatible = "qcom,nord-aggre1-noc", .data = &nord_aggre1_noc }, 2637 { .compatible = "qcom,nord-aggre1-noc-tile", .data = &nord_aggre1_noc_tile }, 2638 { .compatible = "qcom,nord-aggre2-noc", .data = &nord_aggre2_noc }, 2639 { .compatible = "qcom,nord-aggre2-noc-tile", .data = &nord_aggre2_noc_tile }, 2640 { .compatible = "qcom,nord-clk-virt", .data = &nord_clk_virt }, 2641 { .compatible = "qcom,nord-cnoc-cfg", .data = &nord_cnoc_cfg }, 2642 { .compatible = "qcom,nord-cnoc-main", .data = &nord_cnoc_main }, 2643 { .compatible = "qcom,nord-hpass-ag-noc", .data = &nord_hpass_ag_noc }, 2644 { .compatible = "qcom,nord-hscnoc", .data = &nord_hscnoc }, 2645 { .compatible = "qcom,nord-mc-virt", .data = &nord_mc_virt }, 2646 { .compatible = "qcom,nord-mmss-noc", .data = &nord_mmss_noc }, 2647 { .compatible = "qcom,nord-nsp-data-noc-0", .data = &nord_nsp_data_noc_0 }, 2648 { .compatible = "qcom,nord-nsp-data-noc-1", .data = &nord_nsp_data_noc_1 }, 2649 { .compatible = "qcom,nord-nsp-data-noc-2", .data = &nord_nsp_data_noc_2 }, 2650 { .compatible = "qcom,nord-nsp-data-noc-3", .data = &nord_nsp_data_noc_3 }, 2651 { .compatible = "qcom,nord-pcie-cfg", .data = &nord_pcie_cfg }, 2652 { .compatible = "qcom,nord-pcie-data-inbound", .data = &nord_pcie_data_inbound }, 2653 { .compatible = "qcom,nord-pcie-data-outbound", .data = &nord_pcie_data_outbound }, 2654 { .compatible = "qcom,nord-system-noc", .data = &nord_system_noc }, 2655 { } 2656 }; 2657 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2658 2659 static struct platform_driver qnoc_driver = { 2660 .probe = qcom_icc_rpmh_probe, 2661 .remove = qcom_icc_rpmh_remove, 2662 .driver = { 2663 .name = "qnoc-nord", 2664 .of_match_table = qnoc_of_match, 2665 .sync_state = icc_sync_state, 2666 }, 2667 }; 2668 2669 static int __init qnoc_driver_init(void) 2670 { 2671 return platform_driver_register(&qnoc_driver); 2672 } 2673 core_initcall(qnoc_driver_init); 2674 2675 static void __exit qnoc_driver_exit(void) 2676 { 2677 platform_driver_unregister(&qnoc_driver); 2678 } 2679 module_exit(qnoc_driver_exit); 2680 2681 MODULE_DESCRIPTION("Qualcomm Nord NoC driver"); 2682 MODULE_LICENSE("GPL"); 2683