1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,hawi-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node ddr_eff_veto_slave = { 18 .name = "ddr_eff_veto_slave", 19 .channels = 1, 20 .buswidth = 4, 21 }; 22 23 static struct qcom_icc_node qup0_core_slave = { 24 .name = "qup0_core_slave", 25 .channels = 1, 26 .buswidth = 4, 27 }; 28 29 static struct qcom_icc_node qup1_core_slave = { 30 .name = "qup1_core_slave", 31 .channels = 1, 32 .buswidth = 4, 33 }; 34 35 static struct qcom_icc_node qup2_core_slave = { 36 .name = "qup2_core_slave", 37 .channels = 1, 38 .buswidth = 4, 39 }; 40 41 static struct qcom_icc_node qup3_core_slave = { 42 .name = "qup3_core_slave", 43 .channels = 1, 44 .buswidth = 4, 45 }; 46 47 static struct qcom_icc_node qup4_core_slave = { 48 .name = "qup4_core_slave", 49 .channels = 1, 50 .buswidth = 4, 51 }; 52 53 static struct qcom_icc_node qhs_aoss = { 54 .name = "qhs_aoss", 55 .channels = 1, 56 .buswidth = 4, 57 }; 58 59 static struct qcom_icc_node qhs_ipa = { 60 .name = "qhs_ipa", 61 .channels = 1, 62 .buswidth = 4, 63 }; 64 65 static struct qcom_icc_node qhs_ipc_router_fence = { 66 .name = "qhs_ipc_router_fence", 67 .channels = 1, 68 .buswidth = 4, 69 }; 70 71 static struct qcom_icc_node qhs_soccp = { 72 .name = "qhs_soccp", 73 .channels = 1, 74 .buswidth = 4, 75 }; 76 77 static struct qcom_icc_node qhs_tme_cfg = { 78 .name = "qhs_tme_cfg", 79 .channels = 1, 80 .buswidth = 4, 81 }; 82 83 static struct qcom_icc_node qss_ddrss_cfg = { 84 .name = "qss_ddrss_cfg", 85 .channels = 1, 86 .buswidth = 4, 87 }; 88 89 static struct qcom_icc_node qxs_imem = { 90 .name = "qxs_imem", 91 .channels = 1, 92 .buswidth = 8, 93 }; 94 95 static struct qcom_icc_node xs_pcie = { 96 .name = "xs_pcie", 97 .channels = 1, 98 .buswidth = 8, 99 }; 100 101 static struct qcom_icc_node xs_pcie_g4x1 = { 102 .name = "xs_pcie_g4x1", 103 .channels = 1, 104 .buswidth = 8, 105 }; 106 107 static struct qcom_icc_node qhs_lpi_cc = { 108 .name = "qhs_lpi_cc", 109 .channels = 1, 110 .buswidth = 4, 111 }; 112 113 static struct qcom_icc_node qns_lb = { 114 .name = "qns_lb", 115 .channels = 4, 116 .buswidth = 32, 117 }; 118 119 static struct qcom_icc_node srvc_llclpi_noc = { 120 .name = "srvc_llclpi_noc", 121 .channels = 1, 122 .buswidth = 4, 123 }; 124 125 static struct qcom_icc_node srvc_llclpi_noc_chipcx = { 126 .name = "srvc_llclpi_noc_chipcx", 127 .channels = 1, 128 .buswidth = 4, 129 }; 130 131 static struct qcom_icc_node ebi = { 132 .name = "ebi", 133 .channels = 4, 134 .buswidth = 4, 135 }; 136 137 static struct qcom_icc_node ddr_rt_slave = { 138 .name = "ddr_rt_slave", 139 .channels = 4, 140 .buswidth = 4, 141 }; 142 143 static struct qcom_icc_node srvc_pcie_aggre_noc = { 144 .name = "srvc_pcie_aggre_noc", 145 .channels = 1, 146 .buswidth = 4, 147 }; 148 149 static struct qcom_icc_node qhs_ahb2phy0 = { 150 .name = "qhs_ahb2phy0", 151 .channels = 1, 152 .buswidth = 4, 153 }; 154 155 static struct qcom_icc_node qhs_boot_rom = { 156 .name = "qhs_boot_rom", 157 .channels = 1, 158 .buswidth = 4, 159 }; 160 161 static struct qcom_icc_node qhs_camera_cfg = { 162 .name = "qhs_camera_cfg", 163 .channels = 1, 164 .buswidth = 4, 165 }; 166 167 static struct qcom_icc_node qhs_clk_ctl = { 168 .name = "qhs_clk_ctl", 169 .channels = 1, 170 .buswidth = 4, 171 }; 172 173 static struct qcom_icc_node qhs_crypto_cfg = { 174 .name = "qhs_crypto_cfg", 175 .channels = 1, 176 .buswidth = 4, 177 }; 178 179 static struct qcom_icc_node qhs_display_cfg = { 180 .name = "qhs_display_cfg", 181 .channels = 1, 182 .buswidth = 4, 183 }; 184 185 static struct qcom_icc_node qhs_eva_cfg = { 186 .name = "qhs_eva_cfg", 187 .channels = 1, 188 .buswidth = 4, 189 }; 190 191 static struct qcom_icc_node qhs_gpuss_cfg = { 192 .name = "qhs_gpuss_cfg", 193 .channels = 1, 194 .buswidth = 8, 195 }; 196 197 static struct qcom_icc_node qhs_i2c = { 198 .name = "qhs_i2c", 199 .channels = 1, 200 .buswidth = 4, 201 }; 202 203 static struct qcom_icc_node qhs_imem_cfg = { 204 .name = "qhs_imem_cfg", 205 .channels = 1, 206 .buswidth = 4, 207 }; 208 209 static struct qcom_icc_node qhs_ipc_router = { 210 .name = "qhs_ipc_router", 211 .channels = 4, 212 .buswidth = 4, 213 }; 214 215 static struct qcom_icc_node qhs_iris_cfg = { 216 .name = "qhs_iris_cfg", 217 .channels = 1, 218 .buswidth = 4, 219 }; 220 221 static struct qcom_icc_node qhs_mss_cfg = { 222 .name = "qhs_mss_cfg", 223 .channels = 1, 224 .buswidth = 4, 225 }; 226 227 static struct qcom_icc_node qhs_pcie_cfg = { 228 .name = "qhs_pcie_cfg", 229 .channels = 1, 230 .buswidth = 4, 231 }; 232 233 static struct qcom_icc_node qhs_pcie_g4x1_cfg = { 234 .name = "qhs_pcie_g4x1_cfg", 235 .channels = 1, 236 .buswidth = 4, 237 }; 238 239 static struct qcom_icc_node qhs_prng = { 240 .name = "qhs_prng", 241 .channels = 1, 242 .buswidth = 4, 243 }; 244 245 static struct qcom_icc_node qhs_qspi = { 246 .name = "qhs_qspi", 247 .channels = 1, 248 .buswidth = 4, 249 }; 250 251 static struct qcom_icc_node qhs_qup1 = { 252 .name = "qhs_qup1", 253 .channels = 1, 254 .buswidth = 4, 255 }; 256 257 static struct qcom_icc_node qhs_qup2 = { 258 .name = "qhs_qup2", 259 .channels = 1, 260 .buswidth = 4, 261 }; 262 263 static struct qcom_icc_node qhs_qup3 = { 264 .name = "qhs_qup3", 265 .channels = 1, 266 .buswidth = 4, 267 }; 268 269 static struct qcom_icc_node qhs_qup4 = { 270 .name = "qhs_qup4", 271 .channels = 1, 272 .buswidth = 4, 273 }; 274 275 static struct qcom_icc_node qhs_sdc2 = { 276 .name = "qhs_sdc2", 277 .channels = 1, 278 .buswidth = 4, 279 }; 280 281 static struct qcom_icc_node qhs_sdc4 = { 282 .name = "qhs_sdc4", 283 .channels = 1, 284 .buswidth = 4, 285 }; 286 287 static struct qcom_icc_node qhs_tlmm = { 288 .name = "qhs_tlmm", 289 .channels = 1, 290 .buswidth = 4, 291 }; 292 293 static struct qcom_icc_node qhs_ufs_mem_cfg = { 294 .name = "qhs_ufs_mem_cfg", 295 .channels = 1, 296 .buswidth = 4, 297 }; 298 299 static struct qcom_icc_node qhs_usb3 = { 300 .name = "qhs_usb3", 301 .channels = 1, 302 .buswidth = 4, 303 }; 304 305 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 306 .name = "qhs_vsense_ctrl_cfg", 307 .channels = 1, 308 .buswidth = 4, 309 }; 310 311 static struct qcom_icc_node qss_qdss_cfg = { 312 .name = "qss_qdss_cfg", 313 .channels = 1, 314 .buswidth = 4, 315 }; 316 317 static struct qcom_icc_node qss_qdss_stm = { 318 .name = "qss_qdss_stm", 319 .channels = 1, 320 .buswidth = 4, 321 }; 322 323 static struct qcom_icc_node qss_tcsr = { 324 .name = "qss_tcsr", 325 .channels = 1, 326 .buswidth = 4, 327 }; 328 329 static struct qcom_icc_node xs_sys_tcu_cfg = { 330 .name = "xs_sys_tcu_cfg", 331 .channels = 1, 332 .buswidth = 8, 333 }; 334 335 static struct qcom_icc_node ddr_eff_veto_master = { 336 .name = "ddr_eff_veto_master", 337 .channels = 1, 338 .buswidth = 4, 339 .num_links = 1, 340 .link_nodes = { &ddr_eff_veto_slave }, 341 }; 342 343 static struct qcom_icc_node qup0_core_master = { 344 .name = "qup0_core_master", 345 .channels = 1, 346 .buswidth = 4, 347 .num_links = 1, 348 .link_nodes = { &qup0_core_slave }, 349 }; 350 351 static struct qcom_icc_node qup1_core_master = { 352 .name = "qup1_core_master", 353 .channels = 1, 354 .buswidth = 4, 355 .num_links = 1, 356 .link_nodes = { &qup1_core_slave }, 357 }; 358 359 static struct qcom_icc_node qup2_core_master = { 360 .name = "qup2_core_master", 361 .channels = 1, 362 .buswidth = 4, 363 .num_links = 1, 364 .link_nodes = { &qup2_core_slave }, 365 }; 366 367 static struct qcom_icc_node qup3_core_master = { 368 .name = "qup3_core_master", 369 .channels = 1, 370 .buswidth = 4, 371 .num_links = 1, 372 .link_nodes = { &qup3_core_slave }, 373 }; 374 375 static struct qcom_icc_node qup4_core_master = { 376 .name = "qup4_core_master", 377 .channels = 1, 378 .buswidth = 4, 379 .num_links = 1, 380 .link_nodes = { &qup4_core_slave }, 381 }; 382 383 static struct qcom_icc_node qnm_gemnoc_pcie = { 384 .name = "qnm_gemnoc_pcie", 385 .channels = 1, 386 .buswidth = 8, 387 .num_links = 2, 388 .link_nodes = { &xs_pcie, &xs_pcie_g4x1 }, 389 }; 390 391 static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = { 392 .name = "qnm_lpiaon_noc_llclpi_noc", 393 .channels = 1, 394 .buswidth = 16, 395 .num_links = 4, 396 .link_nodes = { &qhs_lpi_cc, &qns_lb, 397 &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx }, 398 }; 399 400 static struct qcom_icc_node llcc_mc = { 401 .name = "llcc_mc", 402 .channels = 4, 403 .buswidth = 4, 404 .num_links = 1, 405 .link_nodes = { &ebi }, 406 }; 407 408 static struct qcom_icc_node ddr_rt_mc = { 409 .name = "ddr_rt_mc", 410 .channels = 4, 411 .buswidth = 4, 412 .num_links = 1, 413 .link_nodes = { &ddr_rt_slave }, 414 }; 415 416 static struct qcom_icc_node qsm_pcie_anoc_cfg = { 417 .name = "qsm_pcie_anoc_cfg", 418 .channels = 1, 419 .buswidth = 4, 420 .num_links = 1, 421 .link_nodes = { &srvc_pcie_aggre_noc }, 422 }; 423 424 static struct qcom_icc_node qsm_cfg_east = { 425 .name = "qsm_cfg_east", 426 .channels = 1, 427 .buswidth = 4, 428 .num_links = 4, 429 .link_nodes = { &qhs_crypto_cfg, &qhs_gpuss_cfg, 430 &qhs_qup2, &qhs_vsense_ctrl_cfg }, 431 }; 432 433 static struct qcom_icc_node qsm_cfg_mm = { 434 .name = "qsm_cfg_mm", 435 .channels = 1, 436 .buswidth = 4, 437 .num_links = 5, 438 .link_nodes = { &qhs_boot_rom, &qhs_camera_cfg, 439 &qhs_display_cfg, &qhs_eva_cfg, 440 &qhs_iris_cfg }, 441 }; 442 443 static struct qcom_icc_node qsm_cfg_north = { 444 .name = "qsm_cfg_north", 445 .channels = 1, 446 .buswidth = 4, 447 .num_links = 5, 448 .link_nodes = { &qhs_pcie_cfg, &qhs_pcie_g4x1_cfg, 449 &qhs_qup3, &qhs_qup4, 450 &qhs_sdc2 }, 451 }; 452 453 static struct qcom_icc_node qsm_cfg_south = { 454 .name = "qsm_cfg_south", 455 .channels = 1, 456 .buswidth = 4, 457 .num_links = 6, 458 .link_nodes = { &qhs_ahb2phy0, &qhs_qspi, 459 &qhs_qup1, &qhs_sdc4, 460 &qhs_ufs_mem_cfg, &qhs_usb3 }, 461 }; 462 463 static struct qcom_icc_node qsm_cfg_southwest = { 464 .name = "qsm_cfg_southwest", 465 .channels = 1, 466 .buswidth = 4, 467 .num_links = 2, 468 .link_nodes = { &qhs_ipc_router, &qhs_mss_cfg }, 469 }; 470 471 static struct qcom_icc_node qns_llcc = { 472 .name = "qns_llcc", 473 .channels = 4, 474 .buswidth = 32, 475 .num_links = 1, 476 .link_nodes = { &llcc_mc }, 477 }; 478 479 static struct qcom_icc_node qns_pcie = { 480 .name = "qns_pcie", 481 .channels = 1, 482 .buswidth = 8, 483 .num_links = 1, 484 .link_nodes = { &qnm_gemnoc_pcie }, 485 }; 486 487 static struct qcom_icc_node qns_llc_lpinoc = { 488 .name = "qns_llc_lpinoc", 489 .channels = 1, 490 .buswidth = 16, 491 .num_links = 1, 492 .link_nodes = { &qnm_lpiaon_noc_llclpi_noc }, 493 }; 494 495 static struct qcom_icc_node qss_pcie_anoc_cfg = { 496 .name = "qss_pcie_anoc_cfg", 497 .channels = 1, 498 .buswidth = 4, 499 .num_links = 1, 500 .link_nodes = { &qsm_pcie_anoc_cfg }, 501 }; 502 503 static struct qcom_icc_node qss_stdst_east_cfg = { 504 .name = "qss_stdst_east_cfg", 505 .channels = 1, 506 .buswidth = 4, 507 .num_links = 1, 508 .link_nodes = { &qsm_cfg_east }, 509 }; 510 511 static struct qcom_icc_node qss_stdst_mm_cfg = { 512 .name = "qss_stdst_mm_cfg", 513 .channels = 1, 514 .buswidth = 4, 515 .num_links = 1, 516 .link_nodes = { &qsm_cfg_mm }, 517 }; 518 519 static struct qcom_icc_node qss_stdst_north_cfg = { 520 .name = "qss_stdst_north_cfg", 521 .channels = 1, 522 .buswidth = 4, 523 .num_links = 1, 524 .link_nodes = { &qsm_cfg_north }, 525 }; 526 527 static struct qcom_icc_node qss_stdst_south_cfg = { 528 .name = "qss_stdst_south_cfg", 529 .channels = 1, 530 .buswidth = 4, 531 .num_links = 1, 532 .link_nodes = { &qsm_cfg_south }, 533 }; 534 535 static struct qcom_icc_node qss_stdst_southwest_cfg = { 536 .name = "qss_stdst_southwest_cfg", 537 .channels = 1, 538 .buswidth = 4, 539 .num_links = 1, 540 .link_nodes = { &qsm_cfg_southwest }, 541 }; 542 543 static struct qcom_icc_node alm_gic = { 544 .name = "alm_gic", 545 .channels = 1, 546 .buswidth = 8, 547 .qosbox = &(const struct qcom_icc_qosbox) { 548 .num_ports = 1, 549 .port_offsets = { 0x14d000 }, 550 .prio = 4, 551 .urg_fwd = 0, 552 .prio_fwd_disable = 1, 553 }, 554 .num_links = 1, 555 .link_nodes = { &qns_llcc }, 556 }; 557 558 static struct qcom_icc_node qnm_qpace = { 559 .name = "qnm_qpace", 560 .channels = 1, 561 .buswidth = 32, 562 .qosbox = &(const struct qcom_icc_qosbox) { 563 .num_ports = 1, 564 .port_offsets = { 0x153000 }, 565 .prio = 0, 566 .urg_fwd = 1, 567 .prio_fwd_disable = 1, 568 }, 569 .num_links = 1, 570 .link_nodes = { &qns_llcc }, 571 }; 572 573 static struct qcom_icc_node qsm_cfg_center = { 574 .name = "qsm_cfg_center", 575 .channels = 1, 576 .buswidth = 4, 577 .num_links = 10, 578 .link_nodes = { &qhs_clk_ctl, &qhs_i2c, 579 &qhs_imem_cfg, &qhs_prng, 580 &qhs_tlmm, &qss_pcie_anoc_cfg, 581 &qss_qdss_cfg, &qss_qdss_stm, 582 &qss_tcsr, &xs_sys_tcu_cfg }, 583 }; 584 585 static struct qcom_icc_node qss_stdst_center_cfg = { 586 .name = "qss_stdst_center_cfg", 587 .channels = 1, 588 .buswidth = 4, 589 .num_links = 1, 590 .link_nodes = { &qsm_cfg_center }, 591 }; 592 593 static struct qcom_icc_node qsm_cnoc_main = { 594 .name = "qsm_cnoc_main", 595 .channels = 1, 596 .buswidth = 4, 597 .num_links = 6, 598 .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg, 599 &qss_stdst_mm_cfg, &qss_stdst_north_cfg, 600 &qss_stdst_south_cfg, &qss_stdst_southwest_cfg }, 601 }; 602 603 static struct qcom_icc_node qss_cfg = { 604 .name = "qss_cfg", 605 .channels = 1, 606 .buswidth = 4, 607 .num_links = 1, 608 .link_nodes = { &qsm_cnoc_main }, 609 }; 610 611 static struct qcom_icc_node qnm_gemnoc_cnoc = { 612 .name = "qnm_gemnoc_cnoc", 613 .channels = 1, 614 .buswidth = 16, 615 .num_links = 8, 616 .link_nodes = { &qhs_aoss, &qhs_ipa, 617 &qhs_ipc_router_fence, &qhs_soccp, 618 &qhs_tme_cfg, &qss_cfg, 619 &qss_ddrss_cfg, &qxs_imem }, 620 }; 621 622 static struct qcom_icc_node qns_gem_noc_cnoc = { 623 .name = "qns_gem_noc_cnoc", 624 .channels = 1, 625 .buswidth = 16, 626 .num_links = 1, 627 .link_nodes = { &qnm_gemnoc_cnoc }, 628 }; 629 630 static struct qcom_icc_node alm_gpu_tcu = { 631 .name = "alm_gpu_tcu", 632 .channels = 1, 633 .buswidth = 8, 634 .qosbox = &(const struct qcom_icc_qosbox) { 635 .num_ports = 1, 636 .port_offsets = { 0x145000 }, 637 .prio = 1, 638 .urg_fwd = 0, 639 .prio_fwd_disable = 1, 640 }, 641 .num_links = 2, 642 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 643 }; 644 645 static struct qcom_icc_node alm_sys_tcu = { 646 .name = "alm_sys_tcu", 647 .channels = 1, 648 .buswidth = 8, 649 .qosbox = &(const struct qcom_icc_qosbox) { 650 .num_ports = 1, 651 .port_offsets = { 0x147000 }, 652 .prio = 6, 653 .urg_fwd = 0, 654 .prio_fwd_disable = 1, 655 }, 656 .num_links = 2, 657 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 658 }; 659 660 static struct qcom_icc_node chm_apps = { 661 .name = "chm_apps", 662 .channels = 4, 663 .buswidth = 32, 664 .num_links = 3, 665 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 666 &qns_pcie }, 667 }; 668 669 static struct qcom_icc_node qnm_gpu = { 670 .name = "qnm_gpu", 671 .channels = 4, 672 .buswidth = 32, 673 .qosbox = &(const struct qcom_icc_qosbox) { 674 .num_ports = 4, 675 .port_offsets = { 0x51000, 0x53000, 0xd1000, 0xd3000 }, 676 .prio = 0, 677 .urg_fwd = 1, 678 .prio_fwd_disable = 1, 679 }, 680 .num_links = 3, 681 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 682 &qns_pcie }, 683 }; 684 685 static struct qcom_icc_node qnm_lpass_gemnoc = { 686 .name = "qnm_lpass_gemnoc", 687 .channels = 1, 688 .buswidth = 32, 689 .qosbox = &(const struct qcom_icc_qosbox) { 690 .num_ports = 1, 691 .port_offsets = { 0x149000 }, 692 .prio = 0, 693 .urg_fwd = 1, 694 .prio_fwd_disable = 0, 695 }, 696 .num_links = 3, 697 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 698 &qns_pcie }, 699 }; 700 701 static struct qcom_icc_node qnm_mdsp = { 702 .name = "qnm_mdsp", 703 .channels = 1, 704 .buswidth = 16, 705 .num_links = 3, 706 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 707 &qns_pcie }, 708 }; 709 710 static struct qcom_icc_node qnm_mnoc_hf = { 711 .name = "qnm_mnoc_hf", 712 .channels = 2, 713 .buswidth = 32, 714 .qosbox = &(const struct qcom_icc_qosbox) { 715 .num_ports = 2, 716 .port_offsets = { 0x55000, 0xd5000 }, 717 .prio = 0, 718 .urg_fwd = 1, 719 .prio_fwd_disable = 0, 720 }, 721 .num_links = 3, 722 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 723 &qns_pcie }, 724 }; 725 726 static struct qcom_icc_node qnm_mnoc_sf = { 727 .name = "qnm_mnoc_sf", 728 .channels = 2, 729 .buswidth = 32, 730 .qosbox = &(const struct qcom_icc_qosbox) { 731 .num_ports = 2, 732 .port_offsets = { 0x57000, 0xd7000 }, 733 .prio = 0, 734 .urg_fwd = 1, 735 .prio_fwd_disable = 0, 736 }, 737 .num_links = 3, 738 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 739 &qns_pcie }, 740 }; 741 742 static struct qcom_icc_node qnm_nsp_gemnoc = { 743 .name = "qnm_nsp_gemnoc", 744 .channels = 4, 745 .buswidth = 32, 746 .qosbox = &(const struct qcom_icc_qosbox) { 747 .num_ports = 4, 748 .port_offsets = { 0x59000, 0x5b000, 0xd9000, 0xdb000 }, 749 .prio = 0, 750 .urg_fwd = 1, 751 .prio_fwd_disable = 1, 752 }, 753 .num_links = 3, 754 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 755 &qns_pcie }, 756 }; 757 758 static struct qcom_icc_node qnm_pcie = { 759 .name = "qnm_pcie", 760 .channels = 1, 761 .buswidth = 8, 762 .qosbox = &(const struct qcom_icc_qosbox) { 763 .num_ports = 1, 764 .port_offsets = { 0x14b000 }, 765 .prio = 2, 766 .urg_fwd = 1, 767 .prio_fwd_disable = 0, 768 }, 769 .num_links = 2, 770 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 771 }; 772 773 static struct qcom_icc_node qnm_snoc_sf = { 774 .name = "qnm_snoc_sf", 775 .channels = 1, 776 .buswidth = 32, 777 .qosbox = &(const struct qcom_icc_qosbox) { 778 .num_ports = 1, 779 .port_offsets = { 0x14f000 }, 780 .prio = 0, 781 .urg_fwd = 1, 782 .prio_fwd_disable = 0, 783 }, 784 .num_links = 3, 785 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 786 &qns_pcie }, 787 }; 788 789 static struct qcom_icc_node qnm_wlan_q6 = { 790 .name = "qnm_wlan_q6", 791 .channels = 1, 792 .buswidth = 8, 793 .num_links = 3, 794 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 795 &qns_pcie }, 796 }; 797 798 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 799 .name = "qns_lpass_ag_noc_gemnoc", 800 .channels = 1, 801 .buswidth = 32, 802 .num_links = 1, 803 .link_nodes = { &qnm_lpass_gemnoc }, 804 }; 805 806 static struct qcom_icc_node qns_mem_noc_hf = { 807 .name = "qns_mem_noc_hf", 808 .channels = 2, 809 .buswidth = 32, 810 .num_links = 1, 811 .link_nodes = { &qnm_mnoc_hf }, 812 }; 813 814 static struct qcom_icc_node qns_mem_noc_sf = { 815 .name = "qns_mem_noc_sf", 816 .channels = 2, 817 .buswidth = 32, 818 .num_links = 1, 819 .link_nodes = { &qnm_mnoc_sf }, 820 }; 821 822 static struct qcom_icc_node qns_nsp_gemnoc = { 823 .name = "qns_nsp_gemnoc", 824 .channels = 4, 825 .buswidth = 32, 826 .num_links = 1, 827 .link_nodes = { &qnm_nsp_gemnoc }, 828 }; 829 830 static struct qcom_icc_node qns_pcie_gemnoc = { 831 .name = "qns_pcie_gemnoc", 832 .channels = 1, 833 .buswidth = 8, 834 .num_links = 1, 835 .link_nodes = { &qnm_pcie }, 836 }; 837 838 static struct qcom_icc_node qns_gemnoc_sf = { 839 .name = "qns_gemnoc_sf", 840 .channels = 1, 841 .buswidth = 32, 842 .num_links = 1, 843 .link_nodes = { &qnm_snoc_sf }, 844 }; 845 846 static struct qcom_icc_node qnm_lpiaon_noc = { 847 .name = "qnm_lpiaon_noc", 848 .channels = 1, 849 .buswidth = 32, 850 .num_links = 1, 851 .link_nodes = { &qns_lpass_ag_noc_gemnoc }, 852 }; 853 854 static struct qcom_icc_node qnm_camnoc_hf = { 855 .name = "qnm_camnoc_hf", 856 .channels = 2, 857 .buswidth = 32, 858 .qosbox = &(const struct qcom_icc_qosbox) { 859 .num_ports = 2, 860 .port_offsets = { 0x2a000, 0x2b000 }, 861 .prio = 0, 862 .urg_fwd = 1, 863 .prio_fwd_disable = 0, 864 }, 865 .num_links = 1, 866 .link_nodes = { &qns_mem_noc_hf }, 867 }; 868 869 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { 870 .name = "qnm_camnoc_nrt_icp_sf", 871 .channels = 1, 872 .buswidth = 8, 873 .qosbox = &(const struct qcom_icc_qosbox) { 874 .num_ports = 1, 875 .port_offsets = { 0x2c000 }, 876 .prio = 4, 877 .urg_fwd = 1, 878 .prio_fwd_disable = 1, 879 }, 880 .num_links = 1, 881 .link_nodes = { &qns_mem_noc_sf }, 882 }; 883 884 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { 885 .name = "qnm_camnoc_rt_cdm_sf", 886 .channels = 1, 887 .buswidth = 8, 888 .qosbox = &(const struct qcom_icc_qosbox) { 889 .num_ports = 1, 890 .port_offsets = { 0x38000 }, 891 .prio = 2, 892 .urg_fwd = 1, 893 .prio_fwd_disable = 1, 894 }, 895 .num_links = 1, 896 .link_nodes = { &qns_mem_noc_sf }, 897 }; 898 899 static struct qcom_icc_node qnm_camnoc_sf = { 900 .name = "qnm_camnoc_sf", 901 .channels = 2, 902 .buswidth = 32, 903 .qosbox = &(const struct qcom_icc_qosbox) { 904 .num_ports = 2, 905 .port_offsets = { 0x2d000, 0x2e000 }, 906 .prio = 0, 907 .urg_fwd = 1, 908 .prio_fwd_disable = 0, 909 }, 910 .num_links = 1, 911 .link_nodes = { &qns_mem_noc_sf }, 912 }; 913 914 static struct qcom_icc_node qnm_mdp = { 915 .name = "qnm_mdp", 916 .channels = 2, 917 .buswidth = 32, 918 .qosbox = &(const struct qcom_icc_qosbox) { 919 .num_ports = 2, 920 .port_offsets = { 0x2f000, 0x30000 }, 921 .prio = 0, 922 .urg_fwd = 1, 923 .prio_fwd_disable = 0, 924 }, 925 .num_links = 1, 926 .link_nodes = { &qns_mem_noc_hf }, 927 }; 928 929 static struct qcom_icc_node qnm_mdss_dcp = { 930 .name = "qnm_mdss_dcp", 931 .channels = 1, 932 .buswidth = 8, 933 .qosbox = &(const struct qcom_icc_qosbox) { 934 .num_ports = 1, 935 .port_offsets = { 0x39000 }, 936 .prio = 0, 937 .urg_fwd = 1, 938 .prio_fwd_disable = 0, 939 }, 940 .num_links = 1, 941 .link_nodes = { &qns_mem_noc_sf }, 942 }; 943 944 static struct qcom_icc_node qnm_vapss_hcp = { 945 .name = "qnm_vapss_hcp", 946 .channels = 1, 947 .buswidth = 32, 948 .num_links = 1, 949 .link_nodes = { &qns_mem_noc_sf }, 950 }; 951 952 static struct qcom_icc_node qnm_video_cv_cpu = { 953 .name = "qnm_video_cv_cpu", 954 .channels = 1, 955 .buswidth = 8, 956 .qosbox = &(const struct qcom_icc_qosbox) { 957 .num_ports = 1, 958 .port_offsets = { 0x34000 }, 959 .prio = 4, 960 .urg_fwd = 1, 961 .prio_fwd_disable = 1, 962 }, 963 .num_links = 1, 964 .link_nodes = { &qns_mem_noc_sf }, 965 }; 966 967 static struct qcom_icc_node qnm_video_eva = { 968 .name = "qnm_video_eva", 969 .channels = 2, 970 .buswidth = 32, 971 .qosbox = &(const struct qcom_icc_qosbox) { 972 .num_ports = 2, 973 .port_offsets = { 0x35000, 0x36000 }, 974 .prio = 0, 975 .urg_fwd = 1, 976 .prio_fwd_disable = 0, 977 }, 978 .num_links = 1, 979 .link_nodes = { &qns_mem_noc_sf }, 980 }; 981 982 static struct qcom_icc_node qnm_video_mvp = { 983 .name = "qnm_video_mvp", 984 .channels = 2, 985 .buswidth = 32, 986 .qosbox = &(const struct qcom_icc_qosbox) { 987 .num_ports = 2, 988 .port_offsets = { 0x32000, 0x33000 }, 989 .prio = 0, 990 .urg_fwd = 1, 991 .prio_fwd_disable = 0, 992 }, 993 .num_links = 1, 994 .link_nodes = { &qns_mem_noc_sf }, 995 }; 996 997 static struct qcom_icc_node qnm_video_v_cpu = { 998 .name = "qnm_video_v_cpu", 999 .channels = 1, 1000 .buswidth = 8, 1001 .qosbox = &(const struct qcom_icc_qosbox) { 1002 .num_ports = 1, 1003 .port_offsets = { 0x37000 }, 1004 .prio = 4, 1005 .urg_fwd = 1, 1006 .prio_fwd_disable = 1, 1007 }, 1008 .num_links = 1, 1009 .link_nodes = { &qns_mem_noc_sf }, 1010 }; 1011 1012 static struct qcom_icc_node qnm_nsp = { 1013 .name = "qnm_nsp", 1014 .channels = 4, 1015 .buswidth = 32, 1016 .num_links = 1, 1017 .link_nodes = { &qns_nsp_gemnoc }, 1018 }; 1019 1020 static struct qcom_icc_node xm_pcie = { 1021 .name = "xm_pcie", 1022 .channels = 1, 1023 .buswidth = 8, 1024 .qosbox = &(const struct qcom_icc_qosbox) { 1025 .num_ports = 1, 1026 .port_offsets = { 0xc000 }, 1027 .prio = 3, 1028 .urg_fwd = 0, 1029 .prio_fwd_disable = 1, 1030 }, 1031 .num_links = 1, 1032 .link_nodes = { &qns_pcie_gemnoc }, 1033 }; 1034 1035 static struct qcom_icc_node xm_pcie_g4x1 = { 1036 .name = "xm_pcie_g4x1", 1037 .channels = 1, 1038 .buswidth = 8, 1039 .qosbox = &(const struct qcom_icc_qosbox) { 1040 .num_ports = 1, 1041 .port_offsets = { 0xd000 }, 1042 .prio = 2, 1043 .urg_fwd = 0, 1044 .prio_fwd_disable = 1, 1045 }, 1046 .num_links = 1, 1047 .link_nodes = { &qns_pcie_gemnoc }, 1048 }; 1049 1050 static struct qcom_icc_node qnm_aggre_noc = { 1051 .name = "qnm_aggre_noc", 1052 .channels = 1, 1053 .buswidth = 32, 1054 .qosbox = &(const struct qcom_icc_qosbox) { 1055 .num_ports = 1, 1056 .port_offsets = { 0x20000 }, 1057 .prio = 2, 1058 .urg_fwd = 1, 1059 .prio_fwd_disable = 0, 1060 }, 1061 .num_links = 1, 1062 .link_nodes = { &qns_gemnoc_sf }, 1063 }; 1064 1065 static struct qcom_icc_node qnm_apss_noc = { 1066 .name = "qnm_apss_noc", 1067 .channels = 1, 1068 .buswidth = 8, 1069 .qosbox = &(const struct qcom_icc_qosbox) { 1070 .num_ports = 1, 1071 .port_offsets = { 0x1e000 }, 1072 .prio = 2, 1073 .urg_fwd = 1, 1074 .prio_fwd_disable = 1, 1075 }, 1076 .num_links = 1, 1077 .link_nodes = { &qns_gemnoc_sf }, 1078 }; 1079 1080 static struct qcom_icc_node qnm_cnoc_data = { 1081 .name = "qnm_cnoc_data", 1082 .channels = 1, 1083 .buswidth = 8, 1084 .qosbox = &(const struct qcom_icc_qosbox) { 1085 .num_ports = 1, 1086 .port_offsets = { 0x1f000 }, 1087 .prio = 2, 1088 .urg_fwd = 0, 1089 .prio_fwd_disable = 1, 1090 }, 1091 .num_links = 1, 1092 .link_nodes = { &qns_gemnoc_sf }, 1093 }; 1094 1095 static struct qcom_icc_node qns_a1noc_snoc = { 1096 .name = "qns_a1noc_snoc", 1097 .channels = 1, 1098 .buswidth = 32, 1099 .num_links = 1, 1100 .link_nodes = { &qnm_aggre_noc }, 1101 }; 1102 1103 static struct qcom_icc_node qns_lpass_aggnoc = { 1104 .name = "qns_lpass_aggnoc", 1105 .channels = 1, 1106 .buswidth = 32, 1107 .num_links = 1, 1108 .link_nodes = { &qnm_lpiaon_noc }, 1109 }; 1110 1111 static struct qcom_icc_node qhm_qspi = { 1112 .name = "qhm_qspi", 1113 .channels = 1, 1114 .buswidth = 4, 1115 .qosbox = &(const struct qcom_icc_qosbox) { 1116 .num_ports = 1, 1117 .port_offsets = { 0x49000 }, 1118 .prio = 2, 1119 .urg_fwd = 0, 1120 .prio_fwd_disable = 1, 1121 }, 1122 .num_links = 1, 1123 .link_nodes = { &qns_a1noc_snoc }, 1124 }; 1125 1126 static struct qcom_icc_node qhm_qup2 = { 1127 .name = "qhm_qup2", 1128 .channels = 1, 1129 .buswidth = 4, 1130 .qosbox = &(const struct qcom_icc_qosbox) { 1131 .num_ports = 1, 1132 .port_offsets = { 0x48000 }, 1133 .prio = 2, 1134 .urg_fwd = 0, 1135 .prio_fwd_disable = 1, 1136 }, 1137 .num_links = 1, 1138 .link_nodes = { &qns_a1noc_snoc }, 1139 }; 1140 1141 static struct qcom_icc_node qhm_qup3 = { 1142 .name = "qhm_qup3", 1143 .channels = 1, 1144 .buswidth = 4, 1145 .qosbox = &(const struct qcom_icc_qosbox) { 1146 .num_ports = 1, 1147 .port_offsets = { 0x46000 }, 1148 .prio = 2, 1149 .urg_fwd = 0, 1150 .prio_fwd_disable = 1, 1151 }, 1152 .num_links = 1, 1153 .link_nodes = { &qns_a1noc_snoc }, 1154 }; 1155 1156 static struct qcom_icc_node qhm_qup4 = { 1157 .name = "qhm_qup4", 1158 .channels = 1, 1159 .buswidth = 4, 1160 .qosbox = &(const struct qcom_icc_qosbox) { 1161 .num_ports = 1, 1162 .port_offsets = { 0x47000 }, 1163 .prio = 2, 1164 .urg_fwd = 0, 1165 .prio_fwd_disable = 1, 1166 }, 1167 .num_links = 1, 1168 .link_nodes = { &qns_a1noc_snoc }, 1169 }; 1170 1171 static struct qcom_icc_node qxm_crypto = { 1172 .name = "qxm_crypto", 1173 .channels = 1, 1174 .buswidth = 32, 1175 .qosbox = &(const struct qcom_icc_qosbox) { 1176 .num_ports = 1, 1177 .port_offsets = { 0x40000 }, 1178 .prio = 2, 1179 .urg_fwd = 1, 1180 .prio_fwd_disable = 1, 1181 }, 1182 .num_links = 1, 1183 .link_nodes = { &qns_a1noc_snoc }, 1184 }; 1185 1186 static struct qcom_icc_node qxm_ipa = { 1187 .name = "qxm_ipa", 1188 .channels = 1, 1189 .buswidth = 16, 1190 .qosbox = &(const struct qcom_icc_qosbox) { 1191 .num_ports = 1, 1192 .port_offsets = { 0x41000 }, 1193 .prio = 2, 1194 .urg_fwd = 1, 1195 .prio_fwd_disable = 1, 1196 }, 1197 .num_links = 1, 1198 .link_nodes = { &qns_a1noc_snoc }, 1199 }; 1200 1201 static struct qcom_icc_node qxm_qup1 = { 1202 .name = "qxm_qup1", 1203 .channels = 1, 1204 .buswidth = 8, 1205 .qosbox = &(const struct qcom_icc_qosbox) { 1206 .num_ports = 1, 1207 .port_offsets = { 0x4d000 }, 1208 .prio = 2, 1209 .urg_fwd = 1, 1210 .prio_fwd_disable = 1, 1211 }, 1212 .num_links = 1, 1213 .link_nodes = { &qns_a1noc_snoc }, 1214 }; 1215 1216 static struct qcom_icc_node qxm_soccp = { 1217 .name = "qxm_soccp", 1218 .channels = 1, 1219 .buswidth = 8, 1220 .qosbox = &(const struct qcom_icc_qosbox) { 1221 .num_ports = 1, 1222 .port_offsets = { 0x45000 }, 1223 .prio = 2, 1224 .urg_fwd = 1, 1225 .prio_fwd_disable = 1, 1226 }, 1227 .num_links = 1, 1228 .link_nodes = { &qns_a1noc_snoc }, 1229 }; 1230 1231 static struct qcom_icc_node xm_qdss_etr_0 = { 1232 .name = "xm_qdss_etr_0", 1233 .channels = 1, 1234 .buswidth = 8, 1235 .qosbox = &(const struct qcom_icc_qosbox) { 1236 .num_ports = 1, 1237 .port_offsets = { 0x42000 }, 1238 .prio = 2, 1239 .urg_fwd = 0, 1240 .prio_fwd_disable = 1, 1241 }, 1242 .num_links = 1, 1243 .link_nodes = { &qns_a1noc_snoc }, 1244 }; 1245 1246 static struct qcom_icc_node xm_qdss_etr_1 = { 1247 .name = "xm_qdss_etr_1", 1248 .channels = 1, 1249 .buswidth = 8, 1250 .qosbox = &(const struct qcom_icc_qosbox) { 1251 .num_ports = 1, 1252 .port_offsets = { 0x43000 }, 1253 .prio = 2, 1254 .urg_fwd = 0, 1255 .prio_fwd_disable = 1, 1256 }, 1257 .num_links = 1, 1258 .link_nodes = { &qns_a1noc_snoc }, 1259 }; 1260 1261 static struct qcom_icc_node xm_sdc2 = { 1262 .name = "xm_sdc2", 1263 .channels = 1, 1264 .buswidth = 8, 1265 .qosbox = &(const struct qcom_icc_qosbox) { 1266 .num_ports = 1, 1267 .port_offsets = { 0x44000 }, 1268 .prio = 2, 1269 .urg_fwd = 0, 1270 .prio_fwd_disable = 1, 1271 }, 1272 .num_links = 1, 1273 .link_nodes = { &qns_a1noc_snoc }, 1274 }; 1275 1276 static struct qcom_icc_node xm_sdc4 = { 1277 .name = "xm_sdc4", 1278 .channels = 1, 1279 .buswidth = 8, 1280 .qosbox = &(const struct qcom_icc_qosbox) { 1281 .num_ports = 1, 1282 .port_offsets = { 0x4a000 }, 1283 .prio = 2, 1284 .urg_fwd = 0, 1285 .prio_fwd_disable = 1, 1286 }, 1287 .num_links = 1, 1288 .link_nodes = { &qns_a1noc_snoc }, 1289 }; 1290 1291 static struct qcom_icc_node xm_ufs_mem = { 1292 .name = "xm_ufs_mem", 1293 .channels = 1, 1294 .buswidth = 32, 1295 .qosbox = &(const struct qcom_icc_qosbox) { 1296 .num_ports = 1, 1297 .port_offsets = { 0x4b000 }, 1298 .prio = 2, 1299 .urg_fwd = 0, 1300 .prio_fwd_disable = 1, 1301 }, 1302 .num_links = 1, 1303 .link_nodes = { &qns_a1noc_snoc }, 1304 }; 1305 1306 static struct qcom_icc_node xm_usb3 = { 1307 .name = "xm_usb3", 1308 .channels = 1, 1309 .buswidth = 8, 1310 .qosbox = &(const struct qcom_icc_qosbox) { 1311 .num_ports = 1, 1312 .port_offsets = { 0x4c000 }, 1313 .prio = 2, 1314 .urg_fwd = 0, 1315 .prio_fwd_disable = 1, 1316 }, 1317 .num_links = 1, 1318 .link_nodes = { &qns_a1noc_snoc }, 1319 }; 1320 1321 static struct qcom_icc_node qnm_lpass_lpinoc = { 1322 .name = "qnm_lpass_lpinoc", 1323 .channels = 1, 1324 .buswidth = 32, 1325 .num_links = 2, 1326 .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc }, 1327 }; 1328 1329 static struct qcom_icc_node qns_lpi_aon_noc = { 1330 .name = "qns_lpi_aon_noc", 1331 .channels = 1, 1332 .buswidth = 32, 1333 .num_links = 1, 1334 .link_nodes = { &qnm_lpass_lpinoc }, 1335 }; 1336 1337 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { 1338 .name = "qnm_lpinoc_dsp_qns4m", 1339 .channels = 1, 1340 .buswidth = 32, 1341 .num_links = 1, 1342 .link_nodes = { &qns_lpi_aon_noc }, 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_acv = { 1346 .name = "ACV", 1347 .enable_mask = BIT(3), 1348 .num_nodes = 1, 1349 .nodes = { &ebi }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_ce0 = { 1353 .name = "CE0", 1354 .num_nodes = 1, 1355 .nodes = { &qxm_crypto }, 1356 }; 1357 1358 static struct qcom_icc_bcm bcm_cn0 = { 1359 .name = "CN0", 1360 .enable_mask = BIT(0), 1361 .keepalive = true, 1362 .num_nodes = 24, 1363 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, 1364 &qhs_aoss, &qhs_ipa, 1365 &qhs_ipc_router_fence, &qhs_soccp, 1366 &qhs_tme_cfg, &qss_cfg, 1367 &qss_ddrss_cfg, &qxs_imem, 1368 &xs_pcie, &xs_pcie_g4x1, 1369 &qsm_cfg_center, &qsm_cfg_east, 1370 &qsm_cfg_mm, &qsm_cfg_north, 1371 &qsm_cfg_south, &qsm_cfg_southwest, 1372 &qhs_ahb2phy0, &qhs_boot_rom, 1373 &qhs_camera_cfg, &qhs_clk_ctl, 1374 &qhs_crypto_cfg, &qhs_eva_cfg }, 1375 }; 1376 1377 static struct qcom_icc_bcm bcm_cn1 = { 1378 .name = "CN1", 1379 .num_nodes = 1, 1380 .nodes = { &qhs_display_cfg }, 1381 }; 1382 1383 static struct qcom_icc_bcm bcm_co0 = { 1384 .name = "CO0", 1385 .enable_mask = BIT(0), 1386 .num_nodes = 2, 1387 .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, 1388 }; 1389 1390 static struct qcom_icc_bcm bcm_de0 = { 1391 .name = "DE0", 1392 .enable_mask = BIT(0), 1393 .num_nodes = 1, 1394 .nodes = { &ddr_eff_veto_slave }, 1395 }; 1396 1397 static struct qcom_icc_bcm bcm_lp0 = { 1398 .name = "LP0", 1399 .num_nodes = 5, 1400 .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb, 1401 &qnm_lpass_lpinoc, &qns_llc_lpinoc, 1402 &qns_lpass_aggnoc }, 1403 }; 1404 1405 static struct qcom_icc_bcm bcm_mc0 = { 1406 .name = "MC0", 1407 .keepalive = true, 1408 .num_nodes = 1, 1409 .nodes = { &ebi }, 1410 }; 1411 1412 static struct qcom_icc_bcm bcm_mc5 = { 1413 .name = "MC5", 1414 .num_nodes = 1, 1415 .nodes = { &ddr_rt_slave }, 1416 }; 1417 1418 static struct qcom_icc_bcm bcm_mm0 = { 1419 .name = "MM0", 1420 .num_nodes = 1, 1421 .nodes = { &qns_mem_noc_hf }, 1422 }; 1423 1424 static struct qcom_icc_bcm bcm_mm1 = { 1425 .name = "MM1", 1426 .enable_mask = BIT(0), 1427 .num_nodes = 9, 1428 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, 1429 &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, 1430 &qnm_vapss_hcp, &qnm_video_cv_cpu, 1431 &qnm_video_mvp, &qnm_video_v_cpu, 1432 &qns_mem_noc_sf }, 1433 }; 1434 1435 static struct qcom_icc_bcm bcm_qpc0 = { 1436 .name = "QPC0", 1437 .num_nodes = 1, 1438 .nodes = { &qnm_qpace }, 1439 }; 1440 1441 static struct qcom_icc_bcm bcm_qup0 = { 1442 .name = "QUP0", 1443 .keepalive = true, 1444 .vote_scale = 1, 1445 .num_nodes = 1, 1446 .nodes = { &qup0_core_slave }, 1447 }; 1448 1449 static struct qcom_icc_bcm bcm_qup1 = { 1450 .name = "QUP1", 1451 .keepalive = true, 1452 .vote_scale = 1, 1453 .num_nodes = 1, 1454 .nodes = { &qup1_core_slave }, 1455 }; 1456 1457 static struct qcom_icc_bcm bcm_qup2 = { 1458 .name = "QUP2", 1459 .keepalive = true, 1460 .vote_scale = 1, 1461 .num_nodes = 1, 1462 .nodes = { &qup2_core_slave }, 1463 }; 1464 1465 static struct qcom_icc_bcm bcm_qup3 = { 1466 .name = "QUP3", 1467 .keepalive = true, 1468 .vote_scale = 1, 1469 .num_nodes = 1, 1470 .nodes = { &qup3_core_slave }, 1471 }; 1472 1473 static struct qcom_icc_bcm bcm_qup4 = { 1474 .name = "QUP4", 1475 .keepalive = true, 1476 .vote_scale = 1, 1477 .num_nodes = 1, 1478 .nodes = { &qup4_core_slave }, 1479 }; 1480 1481 static struct qcom_icc_bcm bcm_sh0 = { 1482 .name = "SH0", 1483 .keepalive = true, 1484 .num_nodes = 1, 1485 .nodes = { &qns_llcc }, 1486 }; 1487 1488 static struct qcom_icc_bcm bcm_sh1 = { 1489 .name = "SH1", 1490 .enable_mask = BIT(0), 1491 .num_nodes = 15, 1492 .nodes = { &alm_gic, &alm_gpu_tcu, 1493 &alm_sys_tcu, &chm_apps, 1494 &qnm_gpu, &qnm_lpass_gemnoc, 1495 &qnm_mdsp, &qnm_mnoc_hf, 1496 &qnm_mnoc_sf, &qnm_nsp_gemnoc, 1497 &qnm_pcie, &qnm_snoc_sf, 1498 &qnm_wlan_q6, &qns_gem_noc_cnoc, 1499 &qns_pcie }, 1500 }; 1501 1502 static struct qcom_icc_bcm bcm_sn0 = { 1503 .name = "SN0", 1504 .keepalive = true, 1505 .num_nodes = 1, 1506 .nodes = { &qns_gemnoc_sf }, 1507 }; 1508 1509 static struct qcom_icc_bcm bcm_sn2 = { 1510 .name = "SN2", 1511 .num_nodes = 1, 1512 .nodes = { &qnm_aggre_noc }, 1513 }; 1514 1515 static struct qcom_icc_bcm bcm_sn3 = { 1516 .name = "SN3", 1517 .num_nodes = 1, 1518 .nodes = { &qns_pcie_gemnoc }, 1519 }; 1520 1521 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1522 &bcm_ce0, 1523 }; 1524 1525 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1526 [MASTER_QSPI_0] = &qhm_qspi, 1527 [MASTER_QUP_2] = &qhm_qup2, 1528 [MASTER_QUP_3] = &qhm_qup3, 1529 [MASTER_QUP_4] = &qhm_qup4, 1530 [MASTER_CRYPTO] = &qxm_crypto, 1531 [MASTER_IPA] = &qxm_ipa, 1532 [MASTER_QUP_1] = &qxm_qup1, 1533 [MASTER_SOCCP_PROC] = &qxm_soccp, 1534 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1535 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1536 [MASTER_SDCC_2] = &xm_sdc2, 1537 [MASTER_SDCC_4] = &xm_sdc4, 1538 [MASTER_UFS_MEM] = &xm_ufs_mem, 1539 [MASTER_USB3] = &xm_usb3, 1540 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1541 }; 1542 1543 static const struct regmap_config hawi_aggre1_noc_regmap_config = { 1544 .reg_bits = 32, 1545 .reg_stride = 4, 1546 .val_bits = 32, 1547 .max_register = 0x54400, 1548 .fast_io = true, 1549 }; 1550 1551 static const struct qcom_icc_desc hawi_aggre1_noc = { 1552 .config = &hawi_aggre1_noc_regmap_config, 1553 .nodes = aggre1_noc_nodes, 1554 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1555 .bcms = aggre1_noc_bcms, 1556 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1557 .qos_requires_clocks = true, 1558 }; 1559 1560 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1561 &bcm_de0, 1562 &bcm_qup0, 1563 &bcm_qup1, 1564 &bcm_qup2, 1565 &bcm_qup3, 1566 &bcm_qup4, 1567 }; 1568 1569 static struct qcom_icc_node * const clk_virt_nodes[] = { 1570 [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master, 1571 [MASTER_QUP_CORE_0] = &qup0_core_master, 1572 [MASTER_QUP_CORE_1] = &qup1_core_master, 1573 [MASTER_QUP_CORE_2] = &qup2_core_master, 1574 [MASTER_QUP_CORE_3] = &qup3_core_master, 1575 [MASTER_QUP_CORE_4] = &qup4_core_master, 1576 [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave, 1577 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1578 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1579 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1580 [SLAVE_QUP_CORE_3] = &qup3_core_slave, 1581 [SLAVE_QUP_CORE_4] = &qup4_core_slave, 1582 }; 1583 1584 static const struct qcom_icc_desc hawi_clk_virt = { 1585 .nodes = clk_virt_nodes, 1586 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1587 .bcms = clk_virt_bcms, 1588 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1589 }; 1590 1591 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1592 &bcm_cn0, 1593 }; 1594 1595 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1596 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1597 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1598 [SLAVE_AOSS] = &qhs_aoss, 1599 [SLAVE_IPA_CFG] = &qhs_ipa, 1600 [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence, 1601 [SLAVE_SOCCP] = &qhs_soccp, 1602 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1603 [SLAVE_CNOC_CFG] = &qss_cfg, 1604 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 1605 [SLAVE_IMEM] = &qxs_imem, 1606 [SLAVE_PCIE_0] = &xs_pcie, 1607 [SLAVE_PCIE_1] = &xs_pcie_g4x1, 1608 }; 1609 1610 static const struct regmap_config hawi_cnoc_main_regmap_config = { 1611 .reg_bits = 32, 1612 .reg_stride = 4, 1613 .val_bits = 32, 1614 .max_register = 0x20000, 1615 .fast_io = true, 1616 }; 1617 1618 static const struct qcom_icc_desc hawi_cnoc_main = { 1619 .config = &hawi_cnoc_main_regmap_config, 1620 .nodes = cnoc_main_nodes, 1621 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1622 .bcms = cnoc_main_bcms, 1623 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1624 }; 1625 1626 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1627 &bcm_qpc0, 1628 &bcm_sh0, 1629 &bcm_sh1, 1630 }; 1631 1632 static struct qcom_icc_node * const gem_noc_nodes[] = { 1633 [MASTER_GIC] = &alm_gic, 1634 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1635 [MASTER_SYS_TCU] = &alm_sys_tcu, 1636 [MASTER_APPSS_PROC] = &chm_apps, 1637 [MASTER_GFX3D] = &qnm_gpu, 1638 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, 1639 [MASTER_MSS_PROC] = &qnm_mdsp, 1640 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1641 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1642 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1643 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1644 [MASTER_QPACE] = &qnm_qpace, 1645 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1646 [MASTER_WLAN_Q6] = &qnm_wlan_q6, 1647 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1648 [SLAVE_LLCC] = &qns_llcc, 1649 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1650 }; 1651 1652 static const struct regmap_config hawi_gem_noc_regmap_config = { 1653 .reg_bits = 32, 1654 .reg_stride = 4, 1655 .val_bits = 32, 1656 .max_register = 0x160200, 1657 .fast_io = true, 1658 }; 1659 1660 static const struct qcom_icc_desc hawi_gem_noc = { 1661 .config = &hawi_gem_noc_regmap_config, 1662 .nodes = gem_noc_nodes, 1663 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1664 .bcms = gem_noc_bcms, 1665 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1666 }; 1667 1668 static struct qcom_icc_bcm * const llclpi_noc_bcms[] = { 1669 &bcm_lp0, 1670 }; 1671 1672 static struct qcom_icc_node * const llclpi_noc_nodes[] = { 1673 [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc, 1674 [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc, 1675 [SLAVE_LLCC_ISLAND] = &qns_lb, 1676 [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc, 1677 [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx, 1678 }; 1679 1680 static const struct regmap_config hawi_llclpi_noc_regmap_config = { 1681 .reg_bits = 32, 1682 .reg_stride = 4, 1683 .val_bits = 32, 1684 .max_register = 0x17200, 1685 .fast_io = true, 1686 }; 1687 1688 static const struct qcom_icc_desc hawi_llclpi_noc = { 1689 .config = &hawi_llclpi_noc_regmap_config, 1690 .nodes = llclpi_noc_nodes, 1691 .num_nodes = ARRAY_SIZE(llclpi_noc_nodes), 1692 .bcms = llclpi_noc_bcms, 1693 .num_bcms = ARRAY_SIZE(llclpi_noc_bcms), 1694 }; 1695 1696 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1697 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 1698 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 1699 }; 1700 1701 static const struct regmap_config hawi_lpass_ag_noc_regmap_config = { 1702 .reg_bits = 32, 1703 .reg_stride = 4, 1704 .val_bits = 32, 1705 .max_register = 0xc080, 1706 .fast_io = true, 1707 }; 1708 1709 static const struct qcom_icc_desc hawi_lpass_ag_noc = { 1710 .config = &hawi_lpass_ag_noc_regmap_config, 1711 .nodes = lpass_ag_noc_nodes, 1712 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1713 }; 1714 1715 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 1716 &bcm_lp0, 1717 }; 1718 1719 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 1720 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 1721 [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc, 1722 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 1723 }; 1724 1725 static const struct regmap_config hawi_lpass_lpiaon_noc_regmap_config = { 1726 .reg_bits = 32, 1727 .reg_stride = 4, 1728 .val_bits = 32, 1729 .max_register = 0x19080, 1730 .fast_io = true, 1731 }; 1732 1733 static const struct qcom_icc_desc hawi_lpass_lpiaon_noc = { 1734 .config = &hawi_lpass_lpiaon_noc_regmap_config, 1735 .nodes = lpass_lpiaon_noc_nodes, 1736 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 1737 .bcms = lpass_lpiaon_noc_bcms, 1738 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 1739 }; 1740 1741 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 1742 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, 1743 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 1744 }; 1745 1746 static const struct regmap_config hawi_lpass_lpicx_noc_regmap_config = { 1747 .reg_bits = 32, 1748 .reg_stride = 4, 1749 .val_bits = 32, 1750 .max_register = 0x46080, 1751 .fast_io = true, 1752 }; 1753 1754 static const struct qcom_icc_desc hawi_lpass_lpicx_noc = { 1755 .config = &hawi_lpass_lpicx_noc_regmap_config, 1756 .nodes = lpass_lpicx_noc_nodes, 1757 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 1758 }; 1759 1760 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1761 &bcm_acv, 1762 &bcm_mc0, 1763 &bcm_mc5, 1764 }; 1765 1766 static struct qcom_icc_node * const mc_virt_nodes[] = { 1767 [MASTER_LLCC] = &llcc_mc, 1768 [MASTER_DDR_RT] = &ddr_rt_mc, 1769 [SLAVE_EBI1] = &ebi, 1770 [SLAVE_DDR_RT] = &ddr_rt_slave, 1771 }; 1772 1773 static const struct qcom_icc_desc hawi_mc_virt = { 1774 .nodes = mc_virt_nodes, 1775 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1776 .bcms = mc_virt_bcms, 1777 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1778 }; 1779 1780 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1781 &bcm_mm0, 1782 &bcm_mm1, 1783 }; 1784 1785 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1786 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1787 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, 1788 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, 1789 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1790 [MASTER_MDP] = &qnm_mdp, 1791 [MASTER_MDSS_DCP] = &qnm_mdss_dcp, 1792 [MASTER_CDSP_HCP] = &qnm_vapss_hcp, 1793 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1794 [MASTER_VIDEO_EVA] = &qnm_video_eva, 1795 [MASTER_VIDEO_MVP] = &qnm_video_mvp, 1796 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1797 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1798 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1799 }; 1800 1801 static const struct regmap_config hawi_mmss_noc_regmap_config = { 1802 .reg_bits = 32, 1803 .reg_stride = 4, 1804 .val_bits = 32, 1805 .max_register = 0x5f800, 1806 .fast_io = true, 1807 }; 1808 1809 static const struct qcom_icc_desc hawi_mmss_noc = { 1810 .config = &hawi_mmss_noc_regmap_config, 1811 .nodes = mmss_noc_nodes, 1812 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1813 .bcms = mmss_noc_bcms, 1814 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1815 }; 1816 1817 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1818 &bcm_co0, 1819 }; 1820 1821 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1822 [MASTER_CDSP_PROC] = &qnm_nsp, 1823 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1824 }; 1825 1826 static const struct regmap_config hawi_nsp_noc_regmap_config = { 1827 .reg_bits = 32, 1828 .reg_stride = 4, 1829 .val_bits = 32, 1830 .max_register = 0x21280, 1831 .fast_io = true, 1832 }; 1833 1834 static const struct qcom_icc_desc hawi_nsp_noc = { 1835 .config = &hawi_nsp_noc_regmap_config, 1836 .nodes = nsp_noc_nodes, 1837 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1838 .bcms = nsp_noc_bcms, 1839 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1840 }; 1841 1842 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1843 &bcm_sn3, 1844 }; 1845 1846 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1847 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, 1848 [MASTER_PCIE_0] = &xm_pcie, 1849 [MASTER_PCIE_1] = &xm_pcie_g4x1, 1850 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, 1851 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1852 }; 1853 1854 static const struct regmap_config hawi_pcie_anoc_regmap_config = { 1855 .reg_bits = 32, 1856 .reg_stride = 4, 1857 .val_bits = 32, 1858 .max_register = 0x12400, 1859 .fast_io = true, 1860 }; 1861 1862 static const struct qcom_icc_desc hawi_pcie_anoc = { 1863 .config = &hawi_pcie_anoc_regmap_config, 1864 .nodes = pcie_anoc_nodes, 1865 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1866 .bcms = pcie_anoc_bcms, 1867 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1868 .qos_requires_clocks = true, 1869 }; 1870 1871 static struct qcom_icc_bcm * const stdst_cfg_bcms[] = { 1872 &bcm_cn0, 1873 &bcm_cn1, 1874 }; 1875 1876 static struct qcom_icc_node * const stdst_cfg_nodes[] = { 1877 [MASTER_CFG_CENTER] = &qsm_cfg_center, 1878 [MASTER_CFG_EAST] = &qsm_cfg_east, 1879 [MASTER_CFG_MM] = &qsm_cfg_mm, 1880 [MASTER_CFG_NORTH] = &qsm_cfg_north, 1881 [MASTER_CFG_SOUTH] = &qsm_cfg_south, 1882 [MASTER_CFG_SOUTHWEST] = &qsm_cfg_southwest, 1883 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1884 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1885 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1886 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1887 [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg, 1888 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1889 [SLAVE_EVA_CFG] = &qhs_eva_cfg, 1890 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1891 [SLAVE_I2C] = &qhs_i2c, 1892 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1893 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1894 [SLAVE_IRIS_CFG] = &qhs_iris_cfg, 1895 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1896 [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg, 1897 [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg, 1898 [SLAVE_PRNG] = &qhs_prng, 1899 [SLAVE_QSPI_0] = &qhs_qspi, 1900 [SLAVE_QUP_1] = &qhs_qup1, 1901 [SLAVE_QUP_2] = &qhs_qup2, 1902 [SLAVE_QUP_3] = &qhs_qup3, 1903 [SLAVE_QUP_4] = &qhs_qup4, 1904 [SLAVE_SDCC_2] = &qhs_sdc2, 1905 [SLAVE_SDCC_4] = &qhs_sdc4, 1906 [SLAVE_TLMM] = &qhs_tlmm, 1907 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1908 [SLAVE_USB3] = &qhs_usb3, 1909 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1910 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, 1911 [SLAVE_QDSS_CFG] = &qss_qdss_cfg, 1912 [SLAVE_QDSS_STM] = &qss_qdss_stm, 1913 [SLAVE_TCSR] = &qss_tcsr, 1914 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1915 }; 1916 1917 static const struct regmap_config hawi_stdst_cfg_regmap_config = { 1918 .reg_bits = 32, 1919 .reg_stride = 4, 1920 .val_bits = 32, 1921 .max_register = 0xb1000, 1922 .fast_io = true, 1923 }; 1924 1925 static const struct qcom_icc_desc hawi_stdst_cfg = { 1926 .config = &hawi_stdst_cfg_regmap_config, 1927 .nodes = stdst_cfg_nodes, 1928 .num_nodes = ARRAY_SIZE(stdst_cfg_nodes), 1929 .bcms = stdst_cfg_bcms, 1930 .num_bcms = ARRAY_SIZE(stdst_cfg_bcms), 1931 }; 1932 1933 static struct qcom_icc_node * const stdst_main_nodes[] = { 1934 [MASTER_CNOC_STARDUST] = &qsm_cnoc_main, 1935 [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg, 1936 [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg, 1937 [SLAVE_STARDUST_MM_CFG] = &qss_stdst_mm_cfg, 1938 [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg, 1939 [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg, 1940 [SLAVE_STARDUST_SOUTHWEST_CFG] = &qss_stdst_southwest_cfg, 1941 }; 1942 1943 static const struct regmap_config hawi_stdst_main_regmap_config = { 1944 .reg_bits = 32, 1945 .reg_stride = 4, 1946 .val_bits = 32, 1947 .max_register = 0x10000, 1948 .fast_io = true, 1949 }; 1950 1951 static const struct qcom_icc_desc hawi_stdst_main = { 1952 .config = &hawi_stdst_main_regmap_config, 1953 .nodes = stdst_main_nodes, 1954 .num_nodes = ARRAY_SIZE(stdst_main_nodes), 1955 }; 1956 1957 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1958 &bcm_sn0, 1959 &bcm_sn2, 1960 }; 1961 1962 static struct qcom_icc_node * const system_noc_nodes[] = { 1963 [MASTER_A1NOC_SNOC] = &qnm_aggre_noc, 1964 [MASTER_APSS_NOC] = &qnm_apss_noc, 1965 [MASTER_CNOC_SNOC] = &qnm_cnoc_data, 1966 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1967 }; 1968 1969 static const struct regmap_config hawi_system_noc_regmap_config = { 1970 .reg_bits = 32, 1971 .reg_stride = 4, 1972 .val_bits = 32, 1973 .max_register = 0x20080, 1974 .fast_io = true, 1975 }; 1976 1977 static const struct qcom_icc_desc hawi_system_noc = { 1978 .config = &hawi_system_noc_regmap_config, 1979 .nodes = system_noc_nodes, 1980 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1981 .bcms = system_noc_bcms, 1982 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1983 }; 1984 1985 static const struct of_device_id qnoc_of_match[] = { 1986 { .compatible = "qcom,hawi-aggre1-noc", .data = &hawi_aggre1_noc }, 1987 { .compatible = "qcom,hawi-clk-virt", .data = &hawi_clk_virt }, 1988 { .compatible = "qcom,hawi-cnoc-main", .data = &hawi_cnoc_main }, 1989 { .compatible = "qcom,hawi-gem-noc", .data = &hawi_gem_noc }, 1990 { .compatible = "qcom,hawi-llclpi-noc", .data = &hawi_llclpi_noc }, 1991 { .compatible = "qcom,hawi-lpass-ag-noc", .data = &hawi_lpass_ag_noc }, 1992 { .compatible = "qcom,hawi-lpass-lpiaon-noc", .data = &hawi_lpass_lpiaon_noc }, 1993 { .compatible = "qcom,hawi-lpass-lpicx-noc", .data = &hawi_lpass_lpicx_noc }, 1994 { .compatible = "qcom,hawi-mc-virt", .data = &hawi_mc_virt }, 1995 { .compatible = "qcom,hawi-mmss-noc", .data = &hawi_mmss_noc }, 1996 { .compatible = "qcom,hawi-nsp-noc", .data = &hawi_nsp_noc }, 1997 { .compatible = "qcom,hawi-pcie-anoc", .data = &hawi_pcie_anoc }, 1998 { .compatible = "qcom,hawi-stdst-cfg", .data = &hawi_stdst_cfg }, 1999 { .compatible = "qcom,hawi-stdst-main", .data = &hawi_stdst_main }, 2000 { .compatible = "qcom,hawi-system-noc", .data = &hawi_system_noc }, 2001 { } 2002 }; 2003 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2004 2005 static struct platform_driver qnoc_driver = { 2006 .probe = qcom_icc_rpmh_probe, 2007 .remove = qcom_icc_rpmh_remove, 2008 .driver = { 2009 .name = "qnoc-hawi", 2010 .of_match_table = qnoc_of_match, 2011 .sync_state = icc_sync_state, 2012 }, 2013 }; 2014 2015 static int __init qnoc_driver_init(void) 2016 { 2017 return platform_driver_register(&qnoc_driver); 2018 } 2019 core_initcall(qnoc_driver_init); 2020 2021 static void __exit qnoc_driver_exit(void) 2022 { 2023 platform_driver_unregister(&qnoc_driver); 2024 } 2025 module_exit(qnoc_driver_exit); 2026 2027 MODULE_DESCRIPTION("Qualcomm Hawi NoC driver"); 2028 MODULE_LICENSE("GPL"); 2029