1 /* 2 * Copyright (c) 2013 Intel Corporation. All rights reserved. 3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. 4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /* 35 * This file contains all of the code that is specific to the SerDes 36 * on the QLogic_IB 7220 chip. 37 */ 38 39 #include <linux/pci.h> 40 #include <linux/delay.h> 41 #include <linux/module.h> 42 #include <linux/firmware.h> 43 44 #include "qib.h" 45 #include "qib_7220.h" 46 47 #define SD7220_FW_NAME "qlogic/sd7220.fw" 48 MODULE_FIRMWARE(SD7220_FW_NAME); 49 50 /* 51 * Same as in qib_iba7220.c, but just the registers needed here. 52 * Could move whole set to qib_7220.h, but decided better to keep 53 * local. 54 */ 55 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64)) 56 #define kr_hwerrclear KREG_IDX(HwErrClear) 57 #define kr_hwerrmask KREG_IDX(HwErrMask) 58 #define kr_hwerrstatus KREG_IDX(HwErrStatus) 59 #define kr_ibcstatus KREG_IDX(IBCStatus) 60 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl) 61 #define kr_scratch KREG_IDX(Scratch) 62 #define kr_xgxs_cfg KREG_IDX(XGXSCfg) 63 /* these are used only here, not in qib_iba7220.c */ 64 #define kr_ibsd_epb_access_ctrl KREG_IDX(ibsd_epb_access_ctrl) 65 #define kr_ibsd_epb_transaction_reg KREG_IDX(ibsd_epb_transaction_reg) 66 #define kr_pciesd_epb_transaction_reg KREG_IDX(pciesd_epb_transaction_reg) 67 #define kr_pciesd_epb_access_ctrl KREG_IDX(pciesd_epb_access_ctrl) 68 #define kr_serdes_ddsrxeq0 KREG_IDX(SerDes_DDSRXEQ0) 69 70 /* 71 * The IBSerDesMappTable is a memory that holds values to be stored in 72 * various SerDes registers by IBC. 73 */ 74 #define kr_serdes_maptable KREG_IDX(IBSerDesMappTable) 75 76 /* 77 * Below used for sdnum parameter, selecting one of the two sections 78 * used for PCIe, or the single SerDes used for IB. 79 */ 80 #define PCIE_SERDES0 0 81 #define PCIE_SERDES1 1 82 83 /* 84 * The EPB requires addressing in a particular form. EPB_LOC() is intended 85 * to make #definitions a little more readable. 86 */ 87 #define EPB_ADDR_SHF 8 88 #define EPB_LOC(chn, elt, reg) \ 89 (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \ 90 EPB_ADDR_SHF) 91 #define EPB_IB_QUAD0_CS_SHF (25) 92 #define EPB_IB_QUAD0_CS (1U << EPB_IB_QUAD0_CS_SHF) 93 #define EPB_IB_UC_CS_SHF (26) 94 #define EPB_PCIE_UC_CS_SHF (27) 95 #define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8)) 96 97 /* Forward declarations. */ 98 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc, 99 u32 data, u32 mask); 100 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, 101 int mask); 102 static int qib_sd_trimdone_poll(struct qib_devdata *dd); 103 static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where); 104 static int qib_sd_setvals(struct qib_devdata *dd); 105 static int qib_sd_early(struct qib_devdata *dd); 106 static int qib_sd_dactrim(struct qib_devdata *dd); 107 static int qib_internal_presets(struct qib_devdata *dd); 108 /* Tweak the register (CMUCTRL5) that contains the TRIMSELF controls */ 109 static int qib_sd_trimself(struct qib_devdata *dd, int val); 110 static int epb_access(struct qib_devdata *dd, int sdnum, int claim); 111 static int qib_sd7220_ib_load(struct qib_devdata *dd, 112 const struct firmware *fw); 113 static int qib_sd7220_ib_vfy(struct qib_devdata *dd, 114 const struct firmware *fw); 115 116 /* 117 * Below keeps track of whether the "once per power-on" initialization has 118 * been done, because uC code Version 1.32.17 or higher allows the uC to 119 * be reset at will, and Automatic Equalization may require it. So the 120 * state of the reset "pin", is no longer valid. Instead, we check for the 121 * actual uC code having been loaded. 122 */ 123 static int qib_ibsd_ucode_loaded(struct qib_pportdata *ppd, 124 const struct firmware *fw) 125 { 126 struct qib_devdata *dd = ppd->dd; 127 128 if (!dd->cspec->serdes_first_init_done && 129 qib_sd7220_ib_vfy(dd, fw) > 0) 130 dd->cspec->serdes_first_init_done = 1; 131 return dd->cspec->serdes_first_init_done; 132 } 133 134 /* repeat #define for local use. "Real" #define is in qib_iba7220.c */ 135 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL 136 #define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF)) 137 #define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF)) 138 #define UC_PAR_CLR_D 8 139 #define UC_PAR_CLR_M 0xC 140 #define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS) 141 #define START_EQ1(chan) EPB_LOC(chan, 7, 0x27) 142 143 void qib_sd7220_clr_ibpar(struct qib_devdata *dd) 144 { 145 int ret; 146 147 /* clear, then re-enable parity errs */ 148 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 149 UC_PAR_CLR_D, UC_PAR_CLR_M); 150 if (ret < 0) { 151 qib_dev_err(dd, "Failed clearing IBSerDes Parity err\n"); 152 goto bail; 153 } 154 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0, 155 UC_PAR_CLR_M); 156 157 qib_read_kreg32(dd, kr_scratch); 158 udelay(4); 159 qib_write_kreg(dd, kr_hwerrclear, 160 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR); 161 qib_read_kreg32(dd, kr_scratch); 162 bail: 163 return; 164 } 165 166 /* 167 * After a reset or other unusual event, the epb interface may need 168 * to be re-synchronized, between the host and the uC. 169 * returns <0 for failure to resync within IBSD_RESYNC_TRIES (not expected) 170 */ 171 #define IBSD_RESYNC_TRIES 3 172 #define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS) 173 #define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS) 174 175 static int qib_resync_ibepb(struct qib_devdata *dd) 176 { 177 int ret, pat, tries, chn; 178 u32 loc; 179 180 ret = -1; 181 chn = 0; 182 for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) { 183 loc = IB_PGUDP(chn); 184 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0); 185 if (ret < 0) { 186 qib_dev_err(dd, "Failed read in resync\n"); 187 continue; 188 } 189 if (ret != 0xF0 && ret != 0x55 && tries == 0) 190 qib_dev_err(dd, "unexpected pattern in resync\n"); 191 pat = ret ^ 0xA5; /* alternate F0 and 55 */ 192 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF); 193 if (ret < 0) { 194 qib_dev_err(dd, "Failed write in resync\n"); 195 continue; 196 } 197 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0); 198 if (ret < 0) { 199 qib_dev_err(dd, "Failed re-read in resync\n"); 200 continue; 201 } 202 if (ret != pat) { 203 qib_dev_err(dd, "Failed compare1 in resync\n"); 204 continue; 205 } 206 loc = IB_CMUDONE(chn); 207 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0); 208 if (ret < 0) { 209 qib_dev_err(dd, "Failed CMUDONE rd in resync\n"); 210 continue; 211 } 212 if ((ret & 0x70) != ((chn << 4) | 0x40)) { 213 qib_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n", 214 ret, chn); 215 continue; 216 } 217 if (++chn == 4) 218 break; /* Success */ 219 } 220 return (ret > 0) ? 0 : ret; 221 } 222 223 /* 224 * Localize the stuff that should be done to change IB uC reset 225 * returns <0 for errors. 226 */ 227 static int qib_ibsd_reset(struct qib_devdata *dd, int assert_rst) 228 { 229 u64 rst_val; 230 int ret = 0; 231 unsigned long flags; 232 233 rst_val = qib_read_kreg64(dd, kr_ibserdesctrl); 234 if (assert_rst) { 235 /* 236 * Vendor recommends "interrupting" uC before reset, to 237 * minimize possible glitches. 238 */ 239 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); 240 epb_access(dd, IB_7220_SERDES, 1); 241 rst_val |= 1ULL; 242 /* Squelch possible parity error from _asserting_ reset */ 243 qib_write_kreg(dd, kr_hwerrmask, 244 dd->cspec->hwerrmask & 245 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR); 246 qib_write_kreg(dd, kr_ibserdesctrl, rst_val); 247 /* flush write, delay to ensure it took effect */ 248 qib_read_kreg32(dd, kr_scratch); 249 udelay(2); 250 /* once it's reset, can remove interrupt */ 251 epb_access(dd, IB_7220_SERDES, -1); 252 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); 253 } else { 254 /* 255 * Before we de-assert reset, we need to deal with 256 * possible glitch on the Parity-error line. 257 * Suppress it around the reset, both in chip-level 258 * hwerrmask and in IB uC control reg. uC will allow 259 * it again during startup. 260 */ 261 u64 val; 262 263 rst_val &= ~(1ULL); 264 qib_write_kreg(dd, kr_hwerrmask, 265 dd->cspec->hwerrmask & 266 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR); 267 268 ret = qib_resync_ibepb(dd); 269 if (ret < 0) 270 qib_dev_err(dd, "unable to re-sync IB EPB\n"); 271 272 /* set uC control regs to suppress parity errs */ 273 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1); 274 if (ret < 0) 275 goto bail; 276 /* IB uC code past Version 1.32.17 allow suppression of wdog */ 277 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 278 0x80); 279 if (ret < 0) { 280 qib_dev_err(dd, "Failed to set WDOG disable\n"); 281 goto bail; 282 } 283 qib_write_kreg(dd, kr_ibserdesctrl, rst_val); 284 /* flush write, delay for startup */ 285 qib_read_kreg32(dd, kr_scratch); 286 udelay(1); 287 /* clear, then re-enable parity errs */ 288 qib_sd7220_clr_ibpar(dd); 289 val = qib_read_kreg64(dd, kr_hwerrstatus); 290 if (val & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR) { 291 qib_dev_err(dd, "IBUC Parity still set after RST\n"); 292 dd->cspec->hwerrmask &= 293 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR; 294 } 295 qib_write_kreg(dd, kr_hwerrmask, 296 dd->cspec->hwerrmask); 297 } 298 299 bail: 300 return ret; 301 } 302 303 static void qib_sd_trimdone_monitor(struct qib_devdata *dd, 304 const char *where) 305 { 306 int ret, chn, baduns; 307 u64 val; 308 309 if (!where) 310 where = "?"; 311 312 /* give time for reset to settle out in EPB */ 313 udelay(2); 314 315 ret = qib_resync_ibepb(dd); 316 if (ret < 0) 317 qib_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where); 318 319 /* Do "sacrificial read" to get EPB in sane state after reset */ 320 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0); 321 if (ret < 0) 322 qib_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where); 323 324 /* Check/show "summary" Trim-done bit in IBCStatus */ 325 val = qib_read_kreg64(dd, kr_ibcstatus); 326 if (!(val & (1ULL << 11))) 327 qib_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where); 328 /* 329 * Do "dummy read/mod/wr" to get EPB in sane state after reset 330 * The default value for MPREG6 is 0. 331 */ 332 udelay(2); 333 334 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80); 335 if (ret < 0) 336 qib_dev_err(dd, "Failed Dummy RMW, (%s)\n", where); 337 udelay(10); 338 339 baduns = 0; 340 341 for (chn = 3; chn >= 0; --chn) { 342 /* Read CTRL reg for each channel to check TRIMDONE */ 343 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, 344 IB_CTRL2(chn), 0, 0); 345 if (ret < 0) 346 qib_dev_err(dd, 347 "Failed checking TRIMDONE, chn %d (%s)\n", 348 chn, where); 349 350 if (!(ret & 0x10)) { 351 int probe; 352 353 baduns |= (1 << chn); 354 qib_dev_err(dd, 355 "TRIMDONE cleared on chn %d (%02X). (%s)\n", 356 chn, ret, where); 357 probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES, 358 IB_PGUDP(0), 0, 0); 359 qib_dev_err(dd, "probe is %d (%02X)\n", 360 probe, probe); 361 probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES, 362 IB_CTRL2(chn), 0, 0); 363 qib_dev_err(dd, "re-read: %d (%02X)\n", 364 probe, probe); 365 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, 366 IB_CTRL2(chn), 0x10, 0x10); 367 if (ret < 0) 368 qib_dev_err(dd, 369 "Err on TRIMDONE rewrite1\n"); 370 } 371 } 372 for (chn = 3; chn >= 0; --chn) { 373 /* Read CTRL reg for each channel to check TRIMDONE */ 374 if (baduns & (1 << chn)) { 375 qib_dev_err(dd, 376 "Resetting TRIMDONE on chn %d (%s)\n", 377 chn, where); 378 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, 379 IB_CTRL2(chn), 0x10, 0x10); 380 if (ret < 0) 381 qib_dev_err(dd, 382 "Failed re-setting TRIMDONE, chn %d (%s)\n", 383 chn, where); 384 } 385 } 386 } 387 388 /* 389 * Below is portion of IBA7220-specific bringup_serdes() that actually 390 * deals with registers and memory within the SerDes itself. 391 * Post IB uC code version 1.32.17, was_reset being 1 is not really 392 * informative, so we double-check. 393 */ 394 int qib_sd7220_init(struct qib_devdata *dd) 395 { 396 const struct firmware *fw; 397 int ret = 1; /* default to failure */ 398 int first_reset, was_reset; 399 400 /* SERDES MPU reset recorded in D0 */ 401 was_reset = (qib_read_kreg64(dd, kr_ibserdesctrl) & 1); 402 if (!was_reset) { 403 /* entered with reset not asserted, we need to do it */ 404 qib_ibsd_reset(dd, 1); 405 qib_sd_trimdone_monitor(dd, "Driver-reload"); 406 } 407 408 ret = request_firmware(&fw, SD7220_FW_NAME, &dd->pcidev->dev); 409 if (ret) { 410 qib_dev_err(dd, "Failed to load IB SERDES image\n"); 411 goto done; 412 } 413 414 /* Substitute our deduced value for was_reset */ 415 ret = qib_ibsd_ucode_loaded(dd->pport, fw); 416 if (ret < 0) 417 goto bail; 418 419 first_reset = !ret; /* First reset if IBSD uCode not yet loaded */ 420 /* 421 * Alter some regs per vendor latest doc, reset-defaults 422 * are not right for IB. 423 */ 424 ret = qib_sd_early(dd); 425 if (ret < 0) { 426 qib_dev_err(dd, "Failed to set IB SERDES early defaults\n"); 427 goto bail; 428 } 429 /* 430 * Set DAC manual trim IB. 431 * We only do this once after chip has been reset (usually 432 * same as once per system boot). 433 */ 434 if (first_reset) { 435 ret = qib_sd_dactrim(dd); 436 if (ret < 0) { 437 qib_dev_err(dd, "Failed IB SERDES DAC trim\n"); 438 goto bail; 439 } 440 } 441 /* 442 * Set various registers (DDS and RXEQ) that will be 443 * controlled by IBC (in 1.2 mode) to reasonable preset values 444 * Calling the "internal" version avoids the "check for needed" 445 * and "trimdone monitor" that might be counter-productive. 446 */ 447 ret = qib_internal_presets(dd); 448 if (ret < 0) { 449 qib_dev_err(dd, "Failed to set IB SERDES presets\n"); 450 goto bail; 451 } 452 ret = qib_sd_trimself(dd, 0x80); 453 if (ret < 0) { 454 qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n"); 455 goto bail; 456 } 457 458 /* Load image, then try to verify */ 459 ret = 0; /* Assume success */ 460 if (first_reset) { 461 int vfy; 462 int trim_done; 463 464 ret = qib_sd7220_ib_load(dd, fw); 465 if (ret < 0) { 466 qib_dev_err(dd, "Failed to load IB SERDES image\n"); 467 goto bail; 468 } else { 469 /* Loaded image, try to verify */ 470 vfy = qib_sd7220_ib_vfy(dd, fw); 471 if (vfy != ret) { 472 qib_dev_err(dd, "SERDES PRAM VFY failed\n"); 473 goto bail; 474 } /* end if verified */ 475 } /* end if loaded */ 476 477 /* 478 * Loaded and verified. Almost good... 479 * hold "success" in ret 480 */ 481 ret = 0; 482 /* 483 * Prev steps all worked, continue bringup 484 * De-assert RESET to uC, only in first reset, to allow 485 * trimming. 486 * 487 * Since our default setup sets START_EQ1 to 488 * PRESET, we need to clear that for this very first run. 489 */ 490 ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38); 491 if (ret < 0) { 492 qib_dev_err(dd, "Failed clearing START_EQ1\n"); 493 goto bail; 494 } 495 496 qib_ibsd_reset(dd, 0); 497 /* 498 * If this is not the first reset, trimdone should be set 499 * already. We may need to check about this. 500 */ 501 trim_done = qib_sd_trimdone_poll(dd); 502 /* 503 * Whether or not trimdone succeeded, we need to put the 504 * uC back into reset to avoid a possible fight with the 505 * IBC state-machine. 506 */ 507 qib_ibsd_reset(dd, 1); 508 509 if (!trim_done) { 510 qib_dev_err(dd, "No TRIMDONE seen\n"); 511 goto bail; 512 } 513 /* 514 * DEBUG: check each time we reset if trimdone bits have 515 * gotten cleared, and re-set them. 516 */ 517 qib_sd_trimdone_monitor(dd, "First-reset"); 518 /* Remember so we do not re-do the load, dactrim, etc. */ 519 dd->cspec->serdes_first_init_done = 1; 520 } 521 /* 522 * setup for channel training and load values for 523 * RxEq and DDS in tables used by IBC in IB1.2 mode 524 */ 525 ret = 0; 526 if (qib_sd_setvals(dd) >= 0) 527 goto done; 528 bail: 529 ret = 1; 530 done: 531 /* start relock timer regardless, but start at 1 second */ 532 set_7220_relock_poll(dd, -1); 533 534 release_firmware(fw); 535 return ret; 536 } 537 538 #define EPB_ACC_REQ 1 539 #define EPB_ACC_GNT 0x100 540 #define EPB_DATA_MASK 0xFF 541 #define EPB_RD (1ULL << 24) 542 #define EPB_TRANS_RDY (1ULL << 31) 543 #define EPB_TRANS_ERR (1ULL << 30) 544 #define EPB_TRANS_TRIES 5 545 546 /* 547 * query, claim, release ownership of the EPB (External Parallel Bus) 548 * for a specified SERDES. 549 * the "claim" parameter is >0 to claim, <0 to release, 0 to query. 550 * Returns <0 for errors, >0 if we had ownership, else 0. 551 */ 552 static int epb_access(struct qib_devdata *dd, int sdnum, int claim) 553 { 554 u16 acc; 555 u64 accval; 556 int owned = 0; 557 u64 oct_sel = 0; 558 559 switch (sdnum) { 560 case IB_7220_SERDES: 561 /* 562 * The IB SERDES "ownership" is fairly simple. A single each 563 * request/grant. 564 */ 565 acc = kr_ibsd_epb_access_ctrl; 566 break; 567 568 case PCIE_SERDES0: 569 case PCIE_SERDES1: 570 /* PCIe SERDES has two "octants", need to select which */ 571 acc = kr_pciesd_epb_access_ctrl; 572 oct_sel = (2 << (sdnum - PCIE_SERDES0)); 573 break; 574 575 default: 576 return 0; 577 } 578 579 /* Make sure any outstanding transaction was seen */ 580 qib_read_kreg32(dd, kr_scratch); 581 udelay(15); 582 583 accval = qib_read_kreg32(dd, acc); 584 585 owned = !!(accval & EPB_ACC_GNT); 586 if (claim < 0) { 587 /* Need to release */ 588 u64 pollval; 589 /* 590 * The only writable bits are the request and CS. 591 * Both should be clear 592 */ 593 u64 newval = 0; 594 595 qib_write_kreg(dd, acc, newval); 596 /* First read after write is not trustworthy */ 597 pollval = qib_read_kreg32(dd, acc); 598 udelay(5); 599 pollval = qib_read_kreg32(dd, acc); 600 if (pollval & EPB_ACC_GNT) 601 owned = -1; 602 } else if (claim > 0) { 603 /* Need to claim */ 604 u64 pollval; 605 u64 newval = EPB_ACC_REQ | oct_sel; 606 607 qib_write_kreg(dd, acc, newval); 608 /* First read after write is not trustworthy */ 609 pollval = qib_read_kreg32(dd, acc); 610 udelay(5); 611 pollval = qib_read_kreg32(dd, acc); 612 if (!(pollval & EPB_ACC_GNT)) 613 owned = -1; 614 } 615 return owned; 616 } 617 618 /* 619 * Lemma to deal with race condition of write..read to epb regs 620 */ 621 static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp) 622 { 623 int tries; 624 u64 transval; 625 626 qib_write_kreg(dd, reg, i_val); 627 /* Throw away first read, as RDY bit may be stale */ 628 transval = qib_read_kreg64(dd, reg); 629 630 for (tries = EPB_TRANS_TRIES; tries; --tries) { 631 transval = qib_read_kreg32(dd, reg); 632 if (transval & EPB_TRANS_RDY) 633 break; 634 udelay(5); 635 } 636 if (transval & EPB_TRANS_ERR) 637 return -1; 638 if (tries > 0 && o_vp) 639 *o_vp = transval; 640 return tries; 641 } 642 643 /** 644 * qib_sd7220_reg_mod - modify SERDES register 645 * @dd: the qlogic_ib device 646 * @sdnum: which SERDES to access 647 * @loc: location - channel, element, register, as packed by EPB_LOC() macro. 648 * @wd: Write Data - value to set in register 649 * @mask: ones where data should be spliced into reg. 650 * 651 * Basic register read/modify/write, with un-needed acesses elided. That is, 652 * a mask of zero will prevent write, while a mask of 0xFF will prevent read. 653 * returns current (presumed, if a write was done) contents of selected 654 * register, or <0 if errors. 655 */ 656 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc, 657 u32 wd, u32 mask) 658 { 659 u16 trans; 660 u64 transval; 661 int owned; 662 int tries, ret; 663 unsigned long flags; 664 665 switch (sdnum) { 666 case IB_7220_SERDES: 667 trans = kr_ibsd_epb_transaction_reg; 668 break; 669 670 case PCIE_SERDES0: 671 case PCIE_SERDES1: 672 trans = kr_pciesd_epb_transaction_reg; 673 break; 674 675 default: 676 return -1; 677 } 678 679 /* 680 * All access is locked in software (vs other host threads) and 681 * hardware (vs uC access). 682 */ 683 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); 684 685 owned = epb_access(dd, sdnum, 1); 686 if (owned < 0) { 687 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); 688 return -1; 689 } 690 for (tries = EPB_TRANS_TRIES; tries; --tries) { 691 transval = qib_read_kreg32(dd, trans); 692 if (transval & EPB_TRANS_RDY) 693 break; 694 udelay(5); 695 } 696 697 if (tries > 0) { 698 tries = 1; /* to make read-skip work */ 699 if (mask != 0xFF) { 700 /* 701 * Not a pure write, so need to read. 702 * loc encodes chip-select as well as address 703 */ 704 transval = loc | EPB_RD; 705 tries = epb_trans(dd, trans, transval, &transval); 706 } 707 if (tries > 0 && mask != 0) { 708 /* 709 * Not a pure read, so need to write. 710 */ 711 wd = (wd & mask) | (transval & ~mask); 712 transval = loc | (wd & EPB_DATA_MASK); 713 tries = epb_trans(dd, trans, transval, &transval); 714 } 715 } 716 /* else, failed to see ready, what error-handling? */ 717 718 /* 719 * Release bus. Failure is an error. 720 */ 721 if (epb_access(dd, sdnum, -1) < 0) 722 ret = -1; 723 else 724 ret = transval & EPB_DATA_MASK; 725 726 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); 727 if (tries <= 0) 728 ret = -1; 729 return ret; 730 } 731 732 #define EPB_ROM_R (2) 733 #define EPB_ROM_W (1) 734 /* 735 * Below, all uC-related, use appropriate UC_CS, depending 736 * on which SerDes is used. 737 */ 738 #define EPB_UC_CTL EPB_LOC(6, 0, 0) 739 #define EPB_MADDRL EPB_LOC(6, 0, 2) 740 #define EPB_MADDRH EPB_LOC(6, 0, 3) 741 #define EPB_ROMDATA EPB_LOC(6, 0, 4) 742 #define EPB_RAMDATA EPB_LOC(6, 0, 5) 743 744 /* Transfer date to/from uC Program RAM of IB or PCIe SerDes */ 745 static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc, 746 u8 *buf, int cnt, int rd_notwr) 747 { 748 u16 trans; 749 u64 transval; 750 u64 csbit; 751 int owned; 752 int tries; 753 int sofar; 754 int addr; 755 int ret; 756 unsigned long flags; 757 758 /* Pick appropriate transaction reg and "Chip select" for this serdes */ 759 switch (sdnum) { 760 case IB_7220_SERDES: 761 csbit = 1ULL << EPB_IB_UC_CS_SHF; 762 trans = kr_ibsd_epb_transaction_reg; 763 break; 764 765 case PCIE_SERDES0: 766 case PCIE_SERDES1: 767 /* PCIe SERDES has uC "chip select" in different bit, too */ 768 csbit = 1ULL << EPB_PCIE_UC_CS_SHF; 769 trans = kr_pciesd_epb_transaction_reg; 770 break; 771 772 default: 773 return -1; 774 } 775 776 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); 777 778 owned = epb_access(dd, sdnum, 1); 779 if (owned < 0) { 780 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); 781 return -1; 782 } 783 784 /* 785 * In future code, we may need to distinguish several address ranges, 786 * and select various memories based on this. For now, just trim 787 * "loc" (location including address and memory select) to 788 * "addr" (address within memory). we will only support PRAM 789 * The memory is 8KB. 790 */ 791 addr = loc & 0x1FFF; 792 for (tries = EPB_TRANS_TRIES; tries; --tries) { 793 transval = qib_read_kreg32(dd, trans); 794 if (transval & EPB_TRANS_RDY) 795 break; 796 udelay(5); 797 } 798 799 sofar = 0; 800 if (tries > 0) { 801 /* 802 * Every "memory" access is doubly-indirect. 803 * We set two bytes of address, then read/write 804 * one or mores bytes of data. 805 */ 806 807 /* First, we set control to "Read" or "Write" */ 808 transval = csbit | EPB_UC_CTL | 809 (rd_notwr ? EPB_ROM_R : EPB_ROM_W); 810 tries = epb_trans(dd, trans, transval, &transval); 811 while (tries > 0 && sofar < cnt) { 812 if (!sofar) { 813 /* Only set address at start of chunk */ 814 int addrbyte = (addr + sofar) >> 8; 815 816 transval = csbit | EPB_MADDRH | addrbyte; 817 tries = epb_trans(dd, trans, transval, 818 &transval); 819 if (tries <= 0) 820 break; 821 addrbyte = (addr + sofar) & 0xFF; 822 transval = csbit | EPB_MADDRL | addrbyte; 823 tries = epb_trans(dd, trans, transval, 824 &transval); 825 if (tries <= 0) 826 break; 827 } 828 829 if (rd_notwr) 830 transval = csbit | EPB_ROMDATA | EPB_RD; 831 else 832 transval = csbit | EPB_ROMDATA | buf[sofar]; 833 tries = epb_trans(dd, trans, transval, &transval); 834 if (tries <= 0) 835 break; 836 if (rd_notwr) 837 buf[sofar] = transval & EPB_DATA_MASK; 838 ++sofar; 839 } 840 /* Finally, clear control-bit for Read or Write */ 841 transval = csbit | EPB_UC_CTL; 842 tries = epb_trans(dd, trans, transval, &transval); 843 } 844 845 ret = sofar; 846 /* Release bus. Failure is an error */ 847 if (epb_access(dd, sdnum, -1) < 0) 848 ret = -1; 849 850 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); 851 if (tries <= 0) 852 ret = -1; 853 return ret; 854 } 855 856 #define PROG_CHUNK 64 857 858 static int qib_sd7220_prog_ld(struct qib_devdata *dd, int sdnum, 859 const u8 *img, int len, int offset) 860 { 861 int cnt, sofar, req; 862 863 sofar = 0; 864 while (sofar < len) { 865 req = len - sofar; 866 if (req > PROG_CHUNK) 867 req = PROG_CHUNK; 868 cnt = qib_sd7220_ram_xfer(dd, sdnum, offset + sofar, 869 (u8 *)img + sofar, req, 0); 870 if (cnt < req) { 871 sofar = -1; 872 break; 873 } 874 sofar += req; 875 } 876 return sofar; 877 } 878 879 #define VFY_CHUNK 64 880 #define SD_PRAM_ERROR_LIMIT 42 881 882 static int qib_sd7220_prog_vfy(struct qib_devdata *dd, int sdnum, 883 const u8 *img, int len, int offset) 884 { 885 int cnt, sofar, req, idx, errors; 886 unsigned char readback[VFY_CHUNK]; 887 888 errors = 0; 889 sofar = 0; 890 while (sofar < len) { 891 req = len - sofar; 892 if (req > VFY_CHUNK) 893 req = VFY_CHUNK; 894 cnt = qib_sd7220_ram_xfer(dd, sdnum, sofar + offset, 895 readback, req, 1); 896 if (cnt < req) { 897 /* failed in read itself */ 898 sofar = -1; 899 break; 900 } 901 for (idx = 0; idx < cnt; ++idx) { 902 if (readback[idx] != img[idx+sofar]) 903 ++errors; 904 } 905 sofar += cnt; 906 } 907 return errors ? -errors : sofar; 908 } 909 910 static int 911 qib_sd7220_ib_load(struct qib_devdata *dd, const struct firmware *fw) 912 { 913 return qib_sd7220_prog_ld(dd, IB_7220_SERDES, fw->data, fw->size, 0); 914 } 915 916 static int 917 qib_sd7220_ib_vfy(struct qib_devdata *dd, const struct firmware *fw) 918 { 919 return qib_sd7220_prog_vfy(dd, IB_7220_SERDES, fw->data, fw->size, 0); 920 } 921 922 /* 923 * IRQ not set up at this point in init, so we poll. 924 */ 925 #define IB_SERDES_TRIM_DONE (1ULL << 11) 926 #define TRIM_TMO (15) 927 928 static int qib_sd_trimdone_poll(struct qib_devdata *dd) 929 { 930 int trim_tmo, ret; 931 uint64_t val; 932 933 /* 934 * Default to failure, so IBC will not start 935 * without IB_SERDES_TRIM_DONE. 936 */ 937 ret = 0; 938 for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) { 939 val = qib_read_kreg64(dd, kr_ibcstatus); 940 if (val & IB_SERDES_TRIM_DONE) { 941 ret = 1; 942 break; 943 } 944 msleep(20); 945 } 946 if (trim_tmo >= TRIM_TMO) { 947 qib_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo); 948 ret = 0; 949 } 950 return ret; 951 } 952 953 #define TX_FAST_ELT (9) 954 955 /* 956 * Set the "negotiation" values for SERDES. These are used by the IB1.2 957 * link negotiation. Macros below are attempt to keep the values a 958 * little more human-editable. 959 * First, values related to Drive De-emphasis Settings. 960 */ 961 962 #define NUM_DDS_REGS 6 963 #define DDS_REG_MAP 0x76A910 /* LSB-first list of regs (in elt 9) to mod */ 964 965 #define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \ 966 { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \ 967 (main_d << 3) | 4 | (ipre_d >> 2), \ 968 (main_s << 3) | 4 | (ipre_s >> 2), \ 969 ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \ 970 ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } } 971 972 static struct dds_init { 973 uint8_t reg_vals[NUM_DDS_REGS]; 974 } dds_init_vals[] = { 975 /* DDR(FDR) SDR(HDR) */ 976 /* Vendor recommends below for 3m cable */ 977 #define DDS_3M 0 978 DDS_VAL(31, 19, 12, 0, 29, 22, 9, 0), 979 DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1), 980 DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0), 981 DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0), 982 DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0), 983 DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0), 984 DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0), 985 DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0), 986 DDS_VAL(31, 20, 11, 0, 28, 23, 8, 0), 987 DDS_VAL(31, 21, 10, 0, 27, 24, 7, 0), 988 DDS_VAL(31, 22, 9, 0, 26, 25, 6, 0), 989 DDS_VAL(30, 23, 8, 0, 25, 26, 5, 0), 990 DDS_VAL(29, 24, 7, 0, 23, 27, 4, 0), 991 /* Vendor recommends below for 1m cable */ 992 #define DDS_1M 13 993 DDS_VAL(28, 25, 6, 0, 21, 28, 3, 0), 994 DDS_VAL(27, 26, 5, 0, 19, 29, 2, 0), 995 DDS_VAL(25, 27, 4, 0, 17, 30, 1, 0) 996 }; 997 998 /* 999 * Now the RXEQ section of the table. 1000 */ 1001 /* Hardware packs an element number and register address thus: */ 1002 #define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4)) 1003 #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \ 1004 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} } 1005 1006 #define RXEQ_VAL_ALL(elt, adr, val) \ 1007 {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} } 1008 1009 #define RXEQ_SDR_DFELTH 0 1010 #define RXEQ_SDR_TLTH 0 1011 #define RXEQ_SDR_G1CNT_Z1CNT 0x11 1012 #define RXEQ_SDR_ZCNT 23 1013 1014 static struct rxeq_init { 1015 u16 rdesc; /* in form used in SerDesDDSRXEQ */ 1016 u8 rdata[4]; 1017 } rxeq_init_vals[] = { 1018 /* Set Rcv Eq. to Preset node */ 1019 RXEQ_VAL_ALL(7, 0x27, 0x10), 1020 /* Set DFELTHFDR/HDR thresholds */ 1021 RXEQ_VAL(7, 8, 0, 0, 0, 0), /* FDR, was 0, 1, 2, 3 */ 1022 RXEQ_VAL(7, 0x21, 0, 0, 0, 0), /* HDR */ 1023 /* Set TLTHFDR/HDR theshold */ 1024 RXEQ_VAL(7, 9, 2, 2, 2, 2), /* FDR, was 0, 2, 4, 6 */ 1025 RXEQ_VAL(7, 0x23, 2, 2, 2, 2), /* HDR, was 0, 1, 2, 3 */ 1026 /* Set Preamp setting 2 (ZFR/ZCNT) */ 1027 RXEQ_VAL(7, 0x1B, 12, 12, 12, 12), /* FDR, was 12, 16, 20, 24 */ 1028 RXEQ_VAL(7, 0x1C, 12, 12, 12, 12), /* HDR, was 12, 16, 20, 24 */ 1029 /* Set Preamp DC gain and Setting 1 (GFR/GHR) */ 1030 RXEQ_VAL(7, 0x1E, 16, 16, 16, 16), /* FDR, was 16, 17, 18, 20 */ 1031 RXEQ_VAL(7, 0x1F, 16, 16, 16, 16), /* HDR, was 16, 17, 18, 20 */ 1032 /* Toggle RELOCK (in VCDL_CTRL0) to lock to data */ 1033 RXEQ_VAL_ALL(6, 6, 0x20), /* Set D5 High */ 1034 RXEQ_VAL_ALL(6, 6, 0), /* Set D5 Low */ 1035 }; 1036 1037 /* There are 17 values from vendor, but IBC only accesses the first 16 */ 1038 #define DDS_ROWS (16) 1039 #define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals) 1040 1041 static int qib_sd_setvals(struct qib_devdata *dd) 1042 { 1043 int idx, midx; 1044 int min_idx; /* Minimum index for this portion of table */ 1045 uint32_t dds_reg_map; 1046 u64 __iomem *taddr, *iaddr; 1047 uint64_t data; 1048 uint64_t sdctl; 1049 1050 taddr = dd->kregbase + kr_serdes_maptable; 1051 iaddr = dd->kregbase + kr_serdes_ddsrxeq0; 1052 1053 /* 1054 * Init the DDS section of the table. 1055 * Each "row" of the table provokes NUM_DDS_REG writes, to the 1056 * registers indicated in DDS_REG_MAP. 1057 */ 1058 sdctl = qib_read_kreg64(dd, kr_ibserdesctrl); 1059 sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8); 1060 sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13); 1061 qib_write_kreg(dd, kr_ibserdesctrl, sdctl); 1062 1063 /* 1064 * Iterate down table within loop for each register to store. 1065 */ 1066 dds_reg_map = DDS_REG_MAP; 1067 for (idx = 0; idx < NUM_DDS_REGS; ++idx) { 1068 data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT; 1069 writeq(data, iaddr + idx); 1070 qib_read_kreg32(dd, kr_scratch); 1071 dds_reg_map >>= 4; 1072 for (midx = 0; midx < DDS_ROWS; ++midx) { 1073 u64 __iomem *daddr = taddr + ((midx << 4) + idx); 1074 1075 data = dds_init_vals[midx].reg_vals[idx]; 1076 writeq(data, daddr); 1077 qib_read_kreg32(dd, kr_scratch); 1078 } /* End inner for (vals for this reg, each row) */ 1079 } /* end outer for (regs to be stored) */ 1080 1081 /* 1082 * Init the RXEQ section of the table. 1083 * This runs in a different order, as the pattern of 1084 * register references is more complex, but there are only 1085 * four "data" values per register. 1086 */ 1087 min_idx = idx; /* RXEQ indices pick up where DDS left off */ 1088 taddr += 0x100; /* RXEQ data is in second half of table */ 1089 /* Iterate through RXEQ register addresses */ 1090 for (idx = 0; idx < RXEQ_ROWS; ++idx) { 1091 int didx; /* "destination" */ 1092 int vidx; 1093 1094 /* didx is offset by min_idx to address RXEQ range of regs */ 1095 didx = idx + min_idx; 1096 /* Store the next RXEQ register address */ 1097 writeq(rxeq_init_vals[idx].rdesc, iaddr + didx); 1098 qib_read_kreg32(dd, kr_scratch); 1099 /* Iterate through RXEQ values */ 1100 for (vidx = 0; vidx < 4; vidx++) { 1101 data = rxeq_init_vals[idx].rdata[vidx]; 1102 writeq(data, taddr + (vidx << 6) + idx); 1103 qib_read_kreg32(dd, kr_scratch); 1104 } 1105 } /* end outer for (Reg-writes for RXEQ) */ 1106 return 0; 1107 } 1108 1109 #define CMUCTRL5 EPB_LOC(7, 0, 0x15) 1110 #define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0) 1111 #define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5) 1112 #define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6) 1113 #define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8) 1114 #define START_EQ2(chan) EPB_LOC(chan, 7, 0x28) 1115 1116 /* 1117 * Repeat a "store" across all channels of the IB SerDes. 1118 * Although nominally it inherits the "read value" of the last 1119 * channel it modified, the only really useful return is <0 for 1120 * failure, >= 0 for success. The parameter 'loc' is assumed to 1121 * be the location in some channel of the register to be modified 1122 * The caller can specify use of the "gang write" option of EPB, 1123 * in which case we use the specified channel data for any fields 1124 * not explicitely written. 1125 */ 1126 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, 1127 int mask) 1128 { 1129 int ret = -1; 1130 int chnl; 1131 1132 if (loc & EPB_GLOBAL_WR) { 1133 /* 1134 * Our caller has assured us that we can set all four 1135 * channels at once. Trust that. If mask is not 0xFF, 1136 * we will read the _specified_ channel for our starting 1137 * value. 1138 */ 1139 loc |= (1U << EPB_IB_QUAD0_CS_SHF); 1140 chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7; 1141 if (mask != 0xFF) { 1142 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, 1143 loc & ~EPB_GLOBAL_WR, 0, 0); 1144 if (ret < 0) { 1145 int sloc = loc >> EPB_ADDR_SHF; 1146 1147 qib_dev_err(dd, 1148 "pre-read failed: elt %d, addr 0x%X, chnl %d\n", 1149 (sloc & 0xF), 1150 (sloc >> 9) & 0x3f, chnl); 1151 return ret; 1152 } 1153 val = (ret & ~mask) | (val & mask); 1154 } 1155 loc &= ~(7 << (4+EPB_ADDR_SHF)); 1156 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF); 1157 if (ret < 0) { 1158 int sloc = loc >> EPB_ADDR_SHF; 1159 1160 qib_dev_err(dd, 1161 "Global WR failed: elt %d, addr 0x%X, val %02X\n", 1162 (sloc & 0xF), (sloc >> 9) & 0x3f, val); 1163 } 1164 return ret; 1165 } 1166 /* Clear "channel" and set CS so we can simply iterate */ 1167 loc &= ~(7 << (4+EPB_ADDR_SHF)); 1168 loc |= (1U << EPB_IB_QUAD0_CS_SHF); 1169 for (chnl = 0; chnl < 4; ++chnl) { 1170 int cloc = loc | (chnl << (4+EPB_ADDR_SHF)); 1171 1172 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask); 1173 if (ret < 0) { 1174 int sloc = loc >> EPB_ADDR_SHF; 1175 1176 qib_dev_err(dd, 1177 "Write failed: elt %d, addr 0x%X, chnl %d, val 0x%02X, mask 0x%02X\n", 1178 (sloc & 0xF), (sloc >> 9) & 0x3f, chnl, 1179 val & 0xFF, mask & 0xFF); 1180 break; 1181 } 1182 } 1183 return ret; 1184 } 1185 1186 /* 1187 * Set the Tx values normally modified by IBC in IB1.2 mode to default 1188 * values, as gotten from first row of init table. 1189 */ 1190 static int set_dds_vals(struct qib_devdata *dd, struct dds_init *ddi) 1191 { 1192 int ret; 1193 int idx, reg, data; 1194 uint32_t regmap; 1195 1196 regmap = DDS_REG_MAP; 1197 for (idx = 0; idx < NUM_DDS_REGS; ++idx) { 1198 reg = (regmap & 0xF); 1199 regmap >>= 4; 1200 data = ddi->reg_vals[idx]; 1201 /* Vendor says RMW not needed for these regs, use 0xFF mask */ 1202 ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF); 1203 if (ret < 0) 1204 break; 1205 } 1206 return ret; 1207 } 1208 1209 /* 1210 * Set the Rx values normally modified by IBC in IB1.2 mode to default 1211 * values, as gotten from selected column of init table. 1212 */ 1213 static int set_rxeq_vals(struct qib_devdata *dd, int vsel) 1214 { 1215 int ret; 1216 int ridx; 1217 int cnt = ARRAY_SIZE(rxeq_init_vals); 1218 1219 for (ridx = 0; ridx < cnt; ++ridx) { 1220 int elt, reg, val, loc; 1221 1222 elt = rxeq_init_vals[ridx].rdesc & 0xF; 1223 reg = rxeq_init_vals[ridx].rdesc >> 4; 1224 loc = EPB_LOC(0, elt, reg); 1225 val = rxeq_init_vals[ridx].rdata[vsel]; 1226 /* mask of 0xFF, because hardware does full-byte store. */ 1227 ret = ibsd_mod_allchnls(dd, loc, val, 0xFF); 1228 if (ret < 0) 1229 break; 1230 } 1231 return ret; 1232 } 1233 1234 /* 1235 * Set the default values (row 0) for DDR Driver Demphasis. 1236 * we do this initially and whenever we turn off IB-1.2 1237 * 1238 * The "default" values for Rx equalization are also stored to 1239 * SerDes registers. Formerly (and still default), we used set 2. 1240 * For experimenting with cables and link-partners, we allow changing 1241 * that via a module parameter. 1242 */ 1243 static unsigned qib_rxeq_set = 2; 1244 module_param_named(rxeq_default_set, qib_rxeq_set, uint, 1245 S_IWUSR | S_IRUGO); 1246 MODULE_PARM_DESC(rxeq_default_set, 1247 "Which set [0..3] of Rx Equalization values is default"); 1248 1249 static int qib_internal_presets(struct qib_devdata *dd) 1250 { 1251 int ret = 0; 1252 1253 ret = set_dds_vals(dd, dds_init_vals + DDS_3M); 1254 1255 if (ret < 0) 1256 qib_dev_err(dd, "Failed to set default DDS values\n"); 1257 ret = set_rxeq_vals(dd, qib_rxeq_set & 3); 1258 if (ret < 0) 1259 qib_dev_err(dd, "Failed to set default RXEQ values\n"); 1260 return ret; 1261 } 1262 1263 int qib_sd7220_presets(struct qib_devdata *dd) 1264 { 1265 int ret = 0; 1266 1267 if (!dd->cspec->presets_needed) 1268 return ret; 1269 dd->cspec->presets_needed = 0; 1270 /* Assert uC reset, so we don't clash with it. */ 1271 qib_ibsd_reset(dd, 1); 1272 udelay(2); 1273 qib_sd_trimdone_monitor(dd, "link-down"); 1274 1275 ret = qib_internal_presets(dd); 1276 return ret; 1277 } 1278 1279 static int qib_sd_trimself(struct qib_devdata *dd, int val) 1280 { 1281 int loc = CMUCTRL5 | (1U << EPB_IB_QUAD0_CS_SHF); 1282 1283 return qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF); 1284 } 1285 1286 static int qib_sd_early(struct qib_devdata *dd) 1287 { 1288 int ret; 1289 1290 ret = ibsd_mod_allchnls(dd, RXHSCTRL0(0) | EPB_GLOBAL_WR, 0xD4, 0xFF); 1291 if (ret < 0) 1292 goto bail; 1293 ret = ibsd_mod_allchnls(dd, START_EQ1(0) | EPB_GLOBAL_WR, 0x10, 0xFF); 1294 if (ret < 0) 1295 goto bail; 1296 ret = ibsd_mod_allchnls(dd, START_EQ2(0) | EPB_GLOBAL_WR, 0x30, 0xFF); 1297 bail: 1298 return ret; 1299 } 1300 1301 #define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E) 1302 #define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6) 1303 #define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF) 1304 1305 static int qib_sd_dactrim(struct qib_devdata *dd) 1306 { 1307 int ret; 1308 1309 ret = ibsd_mod_allchnls(dd, VCDL_DAC2(0) | EPB_GLOBAL_WR, 0x2D, 0xFF); 1310 if (ret < 0) 1311 goto bail; 1312 1313 /* more fine-tuning of what will be default */ 1314 ret = ibsd_mod_allchnls(dd, VCDL_CTRL2(0), 3, 0xF); 1315 if (ret < 0) 1316 goto bail; 1317 1318 ret = ibsd_mod_allchnls(dd, BACTRL(0) | EPB_GLOBAL_WR, 0x40, 0xFF); 1319 if (ret < 0) 1320 goto bail; 1321 1322 ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x04, 0xFF); 1323 if (ret < 0) 1324 goto bail; 1325 1326 ret = ibsd_mod_allchnls(dd, RXHSSTATUS(0) | EPB_GLOBAL_WR, 0x04, 0xFF); 1327 if (ret < 0) 1328 goto bail; 1329 1330 /* 1331 * Delay for max possible number of steps, with slop. 1332 * Each step is about 4usec. 1333 */ 1334 udelay(415); 1335 1336 ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x00, 0xFF); 1337 1338 bail: 1339 return ret; 1340 } 1341 1342 #define RELOCK_FIRST_MS 3 1343 #define RXLSPPM(chan) EPB_LOC(chan, 0, 2) 1344 void toggle_7220_rclkrls(struct qib_devdata *dd) 1345 { 1346 int loc = RXLSPPM(0) | EPB_GLOBAL_WR; 1347 int ret; 1348 1349 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80); 1350 if (ret < 0) 1351 qib_dev_err(dd, "RCLKRLS failed to clear D7\n"); 1352 else { 1353 udelay(1); 1354 ibsd_mod_allchnls(dd, loc, 0x80, 0x80); 1355 } 1356 /* And again for good measure */ 1357 udelay(1); 1358 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80); 1359 if (ret < 0) 1360 qib_dev_err(dd, "RCLKRLS failed to clear D7\n"); 1361 else { 1362 udelay(1); 1363 ibsd_mod_allchnls(dd, loc, 0x80, 0x80); 1364 } 1365 /* Now reset xgxs and IBC to complete the recovery */ 1366 dd->f_xgxs_reset(dd->pport); 1367 } 1368 1369 /* 1370 * Shut down the timer that polls for relock occasions, if needed 1371 * this is "hooked" from qib_7220_quiet_serdes(), which is called 1372 * just before qib_shutdown_device() in qib_driver.c shuts down all 1373 * the other timers 1374 */ 1375 void shutdown_7220_relock_poll(struct qib_devdata *dd) 1376 { 1377 if (dd->cspec->relock_timer_active) 1378 del_timer_sync(&dd->cspec->relock_timer); 1379 } 1380 1381 static unsigned qib_relock_by_timer = 1; 1382 module_param_named(relock_by_timer, qib_relock_by_timer, uint, 1383 S_IWUSR | S_IRUGO); 1384 MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up"); 1385 1386 static void qib_run_relock(struct timer_list *t) 1387 { 1388 struct qib_chip_specific *cs = from_timer(cs, t, relock_timer); 1389 struct qib_devdata *dd = cs->dd; 1390 struct qib_pportdata *ppd = dd->pport; 1391 int timeoff; 1392 1393 /* 1394 * Check link-training state for "stuck" state, when down. 1395 * if found, try relock and schedule another try at 1396 * exponentially growing delay, maxed at one second. 1397 * if not stuck, our work is done. 1398 */ 1399 if ((dd->flags & QIB_INITTED) && !(ppd->lflags & 1400 (QIBL_IB_AUTONEG_INPROG | QIBL_LINKINIT | QIBL_LINKARMED | 1401 QIBL_LINKACTIVE))) { 1402 if (qib_relock_by_timer) { 1403 if (!(ppd->lflags & QIBL_IB_LINK_DISABLED)) 1404 toggle_7220_rclkrls(dd); 1405 } 1406 /* re-set timer for next check */ 1407 timeoff = cs->relock_interval << 1; 1408 if (timeoff > HZ) 1409 timeoff = HZ; 1410 cs->relock_interval = timeoff; 1411 } else 1412 timeoff = HZ; 1413 mod_timer(&cs->relock_timer, jiffies + timeoff); 1414 } 1415 1416 void set_7220_relock_poll(struct qib_devdata *dd, int ibup) 1417 { 1418 struct qib_chip_specific *cs = dd->cspec; 1419 1420 if (ibup) { 1421 /* We are now up, relax timer to 1 second interval */ 1422 if (cs->relock_timer_active) { 1423 cs->relock_interval = HZ; 1424 mod_timer(&cs->relock_timer, jiffies + HZ); 1425 } 1426 } else { 1427 /* Transition to down, (re-)set timer to short interval. */ 1428 unsigned int timeout; 1429 1430 timeout = msecs_to_jiffies(RELOCK_FIRST_MS); 1431 if (timeout == 0) 1432 timeout = 1; 1433 /* If timer has not yet been started, do so. */ 1434 if (!cs->relock_timer_active) { 1435 cs->relock_timer_active = 1; 1436 timer_setup(&cs->relock_timer, qib_run_relock, 0); 1437 cs->relock_interval = timeout; 1438 cs->relock_timer.expires = jiffies + timeout; 1439 add_timer(&cs->relock_timer); 1440 } else { 1441 cs->relock_interval = timeout; 1442 mod_timer(&cs->relock_timer, jiffies + timeout); 1443 } 1444 } 1445 } 1446