1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "2.2-1" 65 #define DRV_RELDATE "Feb 2014" 66 67 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 68 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 69 #define MLX4_IB_CARD_REV_A0 0xA0 70 71 MODULE_AUTHOR("Roland Dreier"); 72 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 73 MODULE_LICENSE("Dual BSD/GPL"); 74 MODULE_VERSION(DRV_VERSION); 75 76 int mlx4_ib_sm_guid_assign = 0; 77 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 78 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 79 80 static const char mlx4_ib_version[] = 81 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 82 DRV_VERSION " (" DRV_RELDATE ")\n"; 83 84 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 else 223 memset(&gid_tbl[i].gid, 0, 12); 224 } 225 } 226 227 err = mlx4_cmd(dev, mailbox->dma, 228 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 229 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 230 MLX4_CMD_WRAPPED); 231 if (mlx4_is_bonded(dev)) 232 err += mlx4_cmd(dev, mailbox->dma, 233 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 234 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 235 MLX4_CMD_WRAPPED); 236 237 mlx4_free_cmd_mailbox(dev, mailbox); 238 return err; 239 } 240 241 static int mlx4_ib_update_gids(struct gid_entry *gids, 242 struct mlx4_ib_dev *ibdev, 243 u8 port_num) 244 { 245 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 246 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 247 248 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 249 } 250 251 static int mlx4_ib_add_gid(struct ib_device *device, 252 u8 port_num, 253 unsigned int index, 254 const union ib_gid *gid, 255 const struct ib_gid_attr *attr, 256 void **context) 257 { 258 struct mlx4_ib_dev *ibdev = to_mdev(device); 259 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 260 struct mlx4_port_gid_table *port_gid_table; 261 int free = -1, found = -1; 262 int ret = 0; 263 int hw_update = 0; 264 int i; 265 struct gid_entry *gids = NULL; 266 267 if (!rdma_cap_roce_gid_table(device, port_num)) 268 return -EINVAL; 269 270 if (port_num > MLX4_MAX_PORTS) 271 return -EINVAL; 272 273 if (!context) 274 return -EINVAL; 275 276 port_gid_table = &iboe->gids[port_num - 1]; 277 spin_lock_bh(&iboe->lock); 278 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 279 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) && 280 (port_gid_table->gids[i].gid_type == attr->gid_type)) { 281 found = i; 282 break; 283 } 284 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid))) 285 free = i; /* HW has space */ 286 } 287 288 if (found < 0) { 289 if (free < 0) { 290 ret = -ENOSPC; 291 } else { 292 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 293 if (!port_gid_table->gids[free].ctx) { 294 ret = -ENOMEM; 295 } else { 296 *context = port_gid_table->gids[free].ctx; 297 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid)); 298 port_gid_table->gids[free].gid_type = attr->gid_type; 299 port_gid_table->gids[free].ctx->real_index = free; 300 port_gid_table->gids[free].ctx->refcount = 1; 301 hw_update = 1; 302 } 303 } 304 } else { 305 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 306 *context = ctx; 307 ctx->refcount++; 308 } 309 if (!ret && hw_update) { 310 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); 311 if (!gids) { 312 ret = -ENOMEM; 313 } else { 314 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 315 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 316 gids[i].gid_type = port_gid_table->gids[i].gid_type; 317 } 318 } 319 } 320 spin_unlock_bh(&iboe->lock); 321 322 if (!ret && hw_update) { 323 ret = mlx4_ib_update_gids(gids, ibdev, port_num); 324 kfree(gids); 325 } 326 327 return ret; 328 } 329 330 static int mlx4_ib_del_gid(struct ib_device *device, 331 u8 port_num, 332 unsigned int index, 333 void **context) 334 { 335 struct gid_cache_context *ctx = *context; 336 struct mlx4_ib_dev *ibdev = to_mdev(device); 337 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 338 struct mlx4_port_gid_table *port_gid_table; 339 int ret = 0; 340 int hw_update = 0; 341 struct gid_entry *gids = NULL; 342 343 if (!rdma_cap_roce_gid_table(device, port_num)) 344 return -EINVAL; 345 346 if (port_num > MLX4_MAX_PORTS) 347 return -EINVAL; 348 349 port_gid_table = &iboe->gids[port_num - 1]; 350 spin_lock_bh(&iboe->lock); 351 if (ctx) { 352 ctx->refcount--; 353 if (!ctx->refcount) { 354 unsigned int real_index = ctx->real_index; 355 356 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid)); 357 kfree(port_gid_table->gids[real_index].ctx); 358 port_gid_table->gids[real_index].ctx = NULL; 359 hw_update = 1; 360 } 361 } 362 if (!ret && hw_update) { 363 int i; 364 365 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); 366 if (!gids) { 367 ret = -ENOMEM; 368 } else { 369 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) 370 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 371 } 372 } 373 spin_unlock_bh(&iboe->lock); 374 375 if (!ret && hw_update) { 376 ret = mlx4_ib_update_gids(gids, ibdev, port_num); 377 kfree(gids); 378 } 379 return ret; 380 } 381 382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 383 u8 port_num, int index) 384 { 385 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 386 struct gid_cache_context *ctx = NULL; 387 union ib_gid gid; 388 struct mlx4_port_gid_table *port_gid_table; 389 int real_index = -EINVAL; 390 int i; 391 int ret; 392 unsigned long flags; 393 struct ib_gid_attr attr; 394 395 if (port_num > MLX4_MAX_PORTS) 396 return -EINVAL; 397 398 if (mlx4_is_bonded(ibdev->dev)) 399 port_num = 1; 400 401 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 402 return index; 403 404 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr); 405 if (ret) 406 return ret; 407 408 if (attr.ndev) 409 dev_put(attr.ndev); 410 411 if (!memcmp(&gid, &zgid, sizeof(gid))) 412 return -EINVAL; 413 414 spin_lock_irqsave(&iboe->lock, flags); 415 port_gid_table = &iboe->gids[port_num - 1]; 416 417 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 418 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) && 419 attr.gid_type == port_gid_table->gids[i].gid_type) { 420 ctx = port_gid_table->gids[i].ctx; 421 break; 422 } 423 if (ctx) 424 real_index = ctx->real_index; 425 spin_unlock_irqrestore(&iboe->lock, flags); 426 return real_index; 427 } 428 429 static int mlx4_ib_query_device(struct ib_device *ibdev, 430 struct ib_device_attr *props, 431 struct ib_udata *uhw) 432 { 433 struct mlx4_ib_dev *dev = to_mdev(ibdev); 434 struct ib_smp *in_mad = NULL; 435 struct ib_smp *out_mad = NULL; 436 int err; 437 int have_ib_ports; 438 struct mlx4_uverbs_ex_query_device cmd; 439 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 440 struct mlx4_clock_params clock_params; 441 442 if (uhw->inlen) { 443 if (uhw->inlen < sizeof(cmd)) 444 return -EINVAL; 445 446 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 447 if (err) 448 return err; 449 450 if (cmd.comp_mask) 451 return -EINVAL; 452 453 if (cmd.reserved) 454 return -EINVAL; 455 } 456 457 resp.response_length = offsetof(typeof(resp), response_length) + 458 sizeof(resp.response_length); 459 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 460 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 461 err = -ENOMEM; 462 if (!in_mad || !out_mad) 463 goto out; 464 465 init_query_mad(in_mad); 466 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 467 468 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 469 1, NULL, NULL, in_mad, out_mad); 470 if (err) 471 goto out; 472 473 memset(props, 0, sizeof *props); 474 475 have_ib_ports = num_ib_ports(dev->dev); 476 477 props->fw_ver = dev->dev->caps.fw_ver; 478 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 479 IB_DEVICE_PORT_ACTIVE_EVENT | 480 IB_DEVICE_SYS_IMAGE_GUID | 481 IB_DEVICE_RC_RNR_NAK_GEN | 482 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 484 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 486 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 488 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 489 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 490 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 491 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 492 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 493 if (dev->dev->caps.max_gso_sz && 494 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 495 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 496 props->device_cap_flags |= IB_DEVICE_UD_TSO; 497 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 498 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 499 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 500 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 501 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 502 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 503 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 504 props->device_cap_flags |= IB_DEVICE_XRC; 505 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 506 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 507 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 508 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 509 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 510 else 511 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 512 } 513 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 514 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 515 516 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 517 518 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 519 0xffffff; 520 props->vendor_part_id = dev->dev->persist->pdev->device; 521 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 522 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 523 524 props->max_mr_size = ~0ull; 525 props->page_size_cap = dev->dev->caps.page_size_cap; 526 props->max_qp = dev->dev->quotas.qp; 527 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 528 props->max_sge = min(dev->dev->caps.max_sq_sg, 529 dev->dev->caps.max_rq_sg); 530 props->max_sge_rd = MLX4_MAX_SGE_RD; 531 props->max_cq = dev->dev->quotas.cq; 532 props->max_cqe = dev->dev->caps.max_cqes; 533 props->max_mr = dev->dev->quotas.mpt; 534 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 535 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 536 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 537 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 538 props->max_srq = dev->dev->quotas.srq; 539 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 540 props->max_srq_sge = dev->dev->caps.max_srq_sge; 541 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 542 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 543 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 544 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 545 props->masked_atomic_cap = props->atomic_cap; 546 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 547 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 548 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 549 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 550 props->max_mcast_grp; 551 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 552 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 553 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 554 props->max_ah = INT_MAX; 555 556 if (!mlx4_is_slave(dev->dev)) 557 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 558 559 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 560 resp.response_length += sizeof(resp.hca_core_clock_offset); 561 if (!err && !mlx4_is_slave(dev->dev)) { 562 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP; 563 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 564 } 565 } 566 567 if (uhw->outlen) { 568 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 569 if (err) 570 goto out; 571 } 572 out: 573 kfree(in_mad); 574 kfree(out_mad); 575 576 return err; 577 } 578 579 static enum rdma_link_layer 580 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 581 { 582 struct mlx4_dev *dev = to_mdev(device)->dev; 583 584 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 585 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 586 } 587 588 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 589 struct ib_port_attr *props, int netw_view) 590 { 591 struct ib_smp *in_mad = NULL; 592 struct ib_smp *out_mad = NULL; 593 int ext_active_speed; 594 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 595 int err = -ENOMEM; 596 597 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 598 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 599 if (!in_mad || !out_mad) 600 goto out; 601 602 init_query_mad(in_mad); 603 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 604 in_mad->attr_mod = cpu_to_be32(port); 605 606 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 607 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 608 609 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 610 in_mad, out_mad); 611 if (err) 612 goto out; 613 614 615 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 616 props->lmc = out_mad->data[34] & 0x7; 617 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 618 props->sm_sl = out_mad->data[36] & 0xf; 619 props->state = out_mad->data[32] & 0xf; 620 props->phys_state = out_mad->data[33] >> 4; 621 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 622 if (netw_view) 623 props->gid_tbl_len = out_mad->data[50]; 624 else 625 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 626 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 627 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 628 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 629 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 630 props->active_width = out_mad->data[31] & 0xf; 631 props->active_speed = out_mad->data[35] >> 4; 632 props->max_mtu = out_mad->data[41] & 0xf; 633 props->active_mtu = out_mad->data[36] >> 4; 634 props->subnet_timeout = out_mad->data[51] & 0x1f; 635 props->max_vl_num = out_mad->data[37] >> 4; 636 props->init_type_reply = out_mad->data[41] >> 4; 637 638 /* Check if extended speeds (EDR/FDR/...) are supported */ 639 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 640 ext_active_speed = out_mad->data[62] >> 4; 641 642 switch (ext_active_speed) { 643 case 1: 644 props->active_speed = IB_SPEED_FDR; 645 break; 646 case 2: 647 props->active_speed = IB_SPEED_EDR; 648 break; 649 } 650 } 651 652 /* If reported active speed is QDR, check if is FDR-10 */ 653 if (props->active_speed == IB_SPEED_QDR) { 654 init_query_mad(in_mad); 655 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 656 in_mad->attr_mod = cpu_to_be32(port); 657 658 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 659 NULL, NULL, in_mad, out_mad); 660 if (err) 661 goto out; 662 663 /* Checking LinkSpeedActive for FDR-10 */ 664 if (out_mad->data[15] & 0x1) 665 props->active_speed = IB_SPEED_FDR10; 666 } 667 668 /* Avoid wrong speed value returned by FW if the IB link is down. */ 669 if (props->state == IB_PORT_DOWN) 670 props->active_speed = IB_SPEED_SDR; 671 672 out: 673 kfree(in_mad); 674 kfree(out_mad); 675 return err; 676 } 677 678 static u8 state_to_phys_state(enum ib_port_state state) 679 { 680 return state == IB_PORT_ACTIVE ? 5 : 3; 681 } 682 683 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 684 struct ib_port_attr *props) 685 { 686 687 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 688 struct mlx4_ib_iboe *iboe = &mdev->iboe; 689 struct net_device *ndev; 690 enum ib_mtu tmp; 691 struct mlx4_cmd_mailbox *mailbox; 692 int err = 0; 693 int is_bonded = mlx4_is_bonded(mdev->dev); 694 695 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 696 if (IS_ERR(mailbox)) 697 return PTR_ERR(mailbox); 698 699 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 700 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 701 MLX4_CMD_WRAPPED); 702 if (err) 703 goto out; 704 705 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 706 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 707 IB_WIDTH_4X : IB_WIDTH_1X; 708 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 709 IB_SPEED_FDR : IB_SPEED_QDR; 710 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS; 711 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 712 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 713 props->pkey_tbl_len = 1; 714 props->max_mtu = IB_MTU_4096; 715 props->max_vl_num = 2; 716 props->state = IB_PORT_DOWN; 717 props->phys_state = state_to_phys_state(props->state); 718 props->active_mtu = IB_MTU_256; 719 spin_lock_bh(&iboe->lock); 720 ndev = iboe->netdevs[port - 1]; 721 if (ndev && is_bonded) { 722 rcu_read_lock(); /* required to get upper dev */ 723 ndev = netdev_master_upper_dev_get_rcu(ndev); 724 rcu_read_unlock(); 725 } 726 if (!ndev) 727 goto out_unlock; 728 729 tmp = iboe_get_mtu(ndev->mtu); 730 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 731 732 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 733 IB_PORT_ACTIVE : IB_PORT_DOWN; 734 props->phys_state = state_to_phys_state(props->state); 735 out_unlock: 736 spin_unlock_bh(&iboe->lock); 737 out: 738 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 739 return err; 740 } 741 742 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 743 struct ib_port_attr *props, int netw_view) 744 { 745 int err; 746 747 /* props being zeroed by the caller, avoid zeroing it here */ 748 749 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 750 ib_link_query_port(ibdev, port, props, netw_view) : 751 eth_link_query_port(ibdev, port, props); 752 753 return err; 754 } 755 756 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 757 struct ib_port_attr *props) 758 { 759 /* returns host view */ 760 return __mlx4_ib_query_port(ibdev, port, props, 0); 761 } 762 763 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 764 union ib_gid *gid, int netw_view) 765 { 766 struct ib_smp *in_mad = NULL; 767 struct ib_smp *out_mad = NULL; 768 int err = -ENOMEM; 769 struct mlx4_ib_dev *dev = to_mdev(ibdev); 770 int clear = 0; 771 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 772 773 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 774 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 775 if (!in_mad || !out_mad) 776 goto out; 777 778 init_query_mad(in_mad); 779 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 780 in_mad->attr_mod = cpu_to_be32(port); 781 782 if (mlx4_is_mfunc(dev->dev) && netw_view) 783 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 784 785 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 786 if (err) 787 goto out; 788 789 memcpy(gid->raw, out_mad->data + 8, 8); 790 791 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 792 if (index) { 793 /* For any index > 0, return the null guid */ 794 err = 0; 795 clear = 1; 796 goto out; 797 } 798 } 799 800 init_query_mad(in_mad); 801 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 802 in_mad->attr_mod = cpu_to_be32(index / 8); 803 804 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 805 NULL, NULL, in_mad, out_mad); 806 if (err) 807 goto out; 808 809 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 810 811 out: 812 if (clear) 813 memset(gid->raw + 8, 0, 8); 814 kfree(in_mad); 815 kfree(out_mad); 816 return err; 817 } 818 819 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 820 union ib_gid *gid) 821 { 822 int ret; 823 824 if (rdma_protocol_ib(ibdev, port)) 825 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 826 827 if (!rdma_protocol_roce(ibdev, port)) 828 return -ENODEV; 829 830 if (!rdma_cap_roce_gid_table(ibdev, port)) 831 return -ENODEV; 832 833 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL); 834 if (ret == -EAGAIN) { 835 memcpy(gid, &zgid, sizeof(*gid)); 836 return 0; 837 } 838 839 return ret; 840 } 841 842 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 843 { 844 union sl2vl_tbl_to_u64 sl2vl64; 845 struct ib_smp *in_mad = NULL; 846 struct ib_smp *out_mad = NULL; 847 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 848 int err = -ENOMEM; 849 int jj; 850 851 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 852 *sl2vl_tbl = 0; 853 return 0; 854 } 855 856 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 857 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 858 if (!in_mad || !out_mad) 859 goto out; 860 861 init_query_mad(in_mad); 862 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 863 in_mad->attr_mod = 0; 864 865 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 866 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 867 868 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 869 in_mad, out_mad); 870 if (err) 871 goto out; 872 873 for (jj = 0; jj < 8; jj++) 874 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 875 *sl2vl_tbl = sl2vl64.sl64; 876 877 out: 878 kfree(in_mad); 879 kfree(out_mad); 880 return err; 881 } 882 883 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 884 { 885 u64 sl2vl; 886 int i; 887 int err; 888 889 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 890 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 891 continue; 892 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 893 if (err) { 894 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 895 i, err); 896 sl2vl = 0; 897 } 898 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 899 } 900 } 901 902 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 903 u16 *pkey, int netw_view) 904 { 905 struct ib_smp *in_mad = NULL; 906 struct ib_smp *out_mad = NULL; 907 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 908 int err = -ENOMEM; 909 910 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 911 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 912 if (!in_mad || !out_mad) 913 goto out; 914 915 init_query_mad(in_mad); 916 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 917 in_mad->attr_mod = cpu_to_be32(index / 32); 918 919 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 920 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 921 922 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 923 in_mad, out_mad); 924 if (err) 925 goto out; 926 927 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 928 929 out: 930 kfree(in_mad); 931 kfree(out_mad); 932 return err; 933 } 934 935 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 936 { 937 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 938 } 939 940 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 941 struct ib_device_modify *props) 942 { 943 struct mlx4_cmd_mailbox *mailbox; 944 unsigned long flags; 945 946 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 947 return -EOPNOTSUPP; 948 949 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 950 return 0; 951 952 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 953 return -EOPNOTSUPP; 954 955 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 956 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 957 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 958 959 /* 960 * If possible, pass node desc to FW, so it can generate 961 * a 144 trap. If cmd fails, just ignore. 962 */ 963 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 964 if (IS_ERR(mailbox)) 965 return 0; 966 967 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 968 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 969 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 970 971 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 972 973 return 0; 974 } 975 976 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 977 u32 cap_mask) 978 { 979 struct mlx4_cmd_mailbox *mailbox; 980 int err; 981 982 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 983 if (IS_ERR(mailbox)) 984 return PTR_ERR(mailbox); 985 986 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 987 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 988 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 989 } else { 990 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 991 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 992 } 993 994 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 995 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 996 MLX4_CMD_WRAPPED); 997 998 mlx4_free_cmd_mailbox(dev->dev, mailbox); 999 return err; 1000 } 1001 1002 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1003 struct ib_port_modify *props) 1004 { 1005 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1006 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1007 struct ib_port_attr attr; 1008 u32 cap_mask; 1009 int err; 1010 1011 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1012 * of whether port link layer is ETH or IB. For ETH ports, qkey 1013 * violations and port capabilities are not meaningful. 1014 */ 1015 if (is_eth) 1016 return 0; 1017 1018 mutex_lock(&mdev->cap_mask_mutex); 1019 1020 err = ib_query_port(ibdev, port, &attr); 1021 if (err) 1022 goto out; 1023 1024 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1025 ~props->clr_port_cap_mask; 1026 1027 err = mlx4_ib_SET_PORT(mdev, port, 1028 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1029 cap_mask); 1030 1031 out: 1032 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1033 return err; 1034 } 1035 1036 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1037 struct ib_udata *udata) 1038 { 1039 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1040 struct mlx4_ib_ucontext *context; 1041 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1042 struct mlx4_ib_alloc_ucontext_resp resp; 1043 int err; 1044 1045 if (!dev->ib_active) 1046 return ERR_PTR(-EAGAIN); 1047 1048 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1049 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1050 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1051 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1052 } else { 1053 resp.dev_caps = dev->dev->caps.userspace_caps; 1054 resp.qp_tab_size = dev->dev->caps.num_qps; 1055 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1056 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1057 resp.cqe_size = dev->dev->caps.cqe_size; 1058 } 1059 1060 context = kzalloc(sizeof(*context), GFP_KERNEL); 1061 if (!context) 1062 return ERR_PTR(-ENOMEM); 1063 1064 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1065 if (err) { 1066 kfree(context); 1067 return ERR_PTR(err); 1068 } 1069 1070 INIT_LIST_HEAD(&context->db_page_list); 1071 mutex_init(&context->db_page_mutex); 1072 1073 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1074 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1075 else 1076 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1077 1078 if (err) { 1079 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1080 kfree(context); 1081 return ERR_PTR(-EFAULT); 1082 } 1083 1084 return &context->ibucontext; 1085 } 1086 1087 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1088 { 1089 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1090 1091 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1092 kfree(context); 1093 1094 return 0; 1095 } 1096 1097 static void mlx4_ib_vma_open(struct vm_area_struct *area) 1098 { 1099 /* vma_open is called when a new VMA is created on top of our VMA. 1100 * This is done through either mremap flow or split_vma (usually due 1101 * to mlock, madvise, munmap, etc.). We do not support a clone of the 1102 * vma, as this VMA is strongly hardware related. Therefore we set the 1103 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1104 * calling us again and trying to do incorrect actions. We assume that 1105 * the original vma size is exactly a single page that there will be no 1106 * "splitting" operations on. 1107 */ 1108 area->vm_ops = NULL; 1109 } 1110 1111 static void mlx4_ib_vma_close(struct vm_area_struct *area) 1112 { 1113 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; 1114 1115 /* It's guaranteed that all VMAs opened on a FD are closed before the 1116 * file itself is closed, therefore no sync is needed with the regular 1117 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync 1118 * with accessing the vma as part of mlx4_ib_disassociate_ucontext. 1119 * The close operation is usually called under mm->mmap_sem except when 1120 * process is exiting. The exiting case is handled explicitly as part 1121 * of mlx4_ib_disassociate_ucontext. 1122 */ 1123 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) 1124 area->vm_private_data; 1125 1126 /* set the vma context pointer to null in the mlx4_ib driver's private 1127 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). 1128 */ 1129 mlx4_ib_vma_priv_data->vma = NULL; 1130 } 1131 1132 static const struct vm_operations_struct mlx4_ib_vm_ops = { 1133 .open = mlx4_ib_vma_open, 1134 .close = mlx4_ib_vma_close 1135 }; 1136 1137 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1138 { 1139 int i; 1140 int ret = 0; 1141 struct vm_area_struct *vma; 1142 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1143 struct task_struct *owning_process = NULL; 1144 struct mm_struct *owning_mm = NULL; 1145 1146 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1147 if (!owning_process) 1148 return; 1149 1150 owning_mm = get_task_mm(owning_process); 1151 if (!owning_mm) { 1152 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1153 while (1) { 1154 /* make sure that task is dead before returning, it may 1155 * prevent a rare case of module down in parallel to a 1156 * call to mlx4_ib_vma_close. 1157 */ 1158 put_task_struct(owning_process); 1159 msleep(1); 1160 owning_process = get_pid_task(ibcontext->tgid, 1161 PIDTYPE_PID); 1162 if (!owning_process || 1163 owning_process->state == TASK_DEAD) { 1164 pr_info("disassociate ucontext done, task was terminated\n"); 1165 /* in case task was dead need to release the task struct */ 1166 if (owning_process) 1167 put_task_struct(owning_process); 1168 return; 1169 } 1170 } 1171 } 1172 1173 /* need to protect from a race on closing the vma as part of 1174 * mlx4_ib_vma_close(). 1175 */ 1176 down_write(&owning_mm->mmap_sem); 1177 for (i = 0; i < HW_BAR_COUNT; i++) { 1178 vma = context->hw_bar_info[i].vma; 1179 if (!vma) 1180 continue; 1181 1182 ret = zap_vma_ptes(context->hw_bar_info[i].vma, 1183 context->hw_bar_info[i].vma->vm_start, 1184 PAGE_SIZE); 1185 if (ret) { 1186 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret); 1187 BUG_ON(1); 1188 } 1189 1190 context->hw_bar_info[i].vma->vm_flags &= 1191 ~(VM_SHARED | VM_MAYSHARE); 1192 /* context going to be destroyed, should not access ops any more */ 1193 context->hw_bar_info[i].vma->vm_ops = NULL; 1194 } 1195 1196 up_write(&owning_mm->mmap_sem); 1197 mmput(owning_mm); 1198 put_task_struct(owning_process); 1199 } 1200 1201 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, 1202 struct mlx4_ib_vma_private_data *vma_private_data) 1203 { 1204 vma_private_data->vma = vma; 1205 vma->vm_private_data = vma_private_data; 1206 vma->vm_ops = &mlx4_ib_vm_ops; 1207 } 1208 1209 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1210 { 1211 struct mlx4_ib_dev *dev = to_mdev(context->device); 1212 struct mlx4_ib_ucontext *mucontext = to_mucontext(context); 1213 1214 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1215 return -EINVAL; 1216 1217 if (vma->vm_pgoff == 0) { 1218 /* We prevent double mmaping on same context */ 1219 if (mucontext->hw_bar_info[HW_BAR_DB].vma) 1220 return -EINVAL; 1221 1222 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1223 1224 if (io_remap_pfn_range(vma, vma->vm_start, 1225 to_mucontext(context)->uar.pfn, 1226 PAGE_SIZE, vma->vm_page_prot)) 1227 return -EAGAIN; 1228 1229 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); 1230 1231 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 1232 /* We prevent double mmaping on same context */ 1233 if (mucontext->hw_bar_info[HW_BAR_BF].vma) 1234 return -EINVAL; 1235 1236 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1237 1238 if (io_remap_pfn_range(vma, vma->vm_start, 1239 to_mucontext(context)->uar.pfn + 1240 dev->dev->caps.num_uars, 1241 PAGE_SIZE, vma->vm_page_prot)) 1242 return -EAGAIN; 1243 1244 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); 1245 1246 } else if (vma->vm_pgoff == 3) { 1247 struct mlx4_clock_params params; 1248 int ret; 1249 1250 /* We prevent double mmaping on same context */ 1251 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) 1252 return -EINVAL; 1253 1254 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1255 1256 if (ret) 1257 return ret; 1258 1259 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1260 if (io_remap_pfn_range(vma, vma->vm_start, 1261 (pci_resource_start(dev->dev->persist->pdev, 1262 params.bar) + 1263 params.offset) 1264 >> PAGE_SHIFT, 1265 PAGE_SIZE, vma->vm_page_prot)) 1266 return -EAGAIN; 1267 1268 mlx4_ib_set_vma_data(vma, 1269 &mucontext->hw_bar_info[HW_BAR_CLOCK]); 1270 } else { 1271 return -EINVAL; 1272 } 1273 1274 return 0; 1275 } 1276 1277 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1278 struct ib_ucontext *context, 1279 struct ib_udata *udata) 1280 { 1281 struct mlx4_ib_pd *pd; 1282 int err; 1283 1284 pd = kmalloc(sizeof *pd, GFP_KERNEL); 1285 if (!pd) 1286 return ERR_PTR(-ENOMEM); 1287 1288 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1289 if (err) { 1290 kfree(pd); 1291 return ERR_PTR(err); 1292 } 1293 1294 if (context) 1295 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1296 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1297 kfree(pd); 1298 return ERR_PTR(-EFAULT); 1299 } 1300 1301 return &pd->ibpd; 1302 } 1303 1304 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1305 { 1306 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1307 kfree(pd); 1308 1309 return 0; 1310 } 1311 1312 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1313 struct ib_ucontext *context, 1314 struct ib_udata *udata) 1315 { 1316 struct mlx4_ib_xrcd *xrcd; 1317 struct ib_cq_init_attr cq_attr = {}; 1318 int err; 1319 1320 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1321 return ERR_PTR(-ENOSYS); 1322 1323 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1324 if (!xrcd) 1325 return ERR_PTR(-ENOMEM); 1326 1327 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1328 if (err) 1329 goto err1; 1330 1331 xrcd->pd = ib_alloc_pd(ibdev, 0); 1332 if (IS_ERR(xrcd->pd)) { 1333 err = PTR_ERR(xrcd->pd); 1334 goto err2; 1335 } 1336 1337 cq_attr.cqe = 1; 1338 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1339 if (IS_ERR(xrcd->cq)) { 1340 err = PTR_ERR(xrcd->cq); 1341 goto err3; 1342 } 1343 1344 return &xrcd->ibxrcd; 1345 1346 err3: 1347 ib_dealloc_pd(xrcd->pd); 1348 err2: 1349 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1350 err1: 1351 kfree(xrcd); 1352 return ERR_PTR(err); 1353 } 1354 1355 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1356 { 1357 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1358 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1359 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1360 kfree(xrcd); 1361 1362 return 0; 1363 } 1364 1365 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1366 { 1367 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1368 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1369 struct mlx4_ib_gid_entry *ge; 1370 1371 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1372 if (!ge) 1373 return -ENOMEM; 1374 1375 ge->gid = *gid; 1376 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1377 ge->port = mqp->port; 1378 ge->added = 1; 1379 } 1380 1381 mutex_lock(&mqp->mutex); 1382 list_add_tail(&ge->list, &mqp->gid_list); 1383 mutex_unlock(&mqp->mutex); 1384 1385 return 0; 1386 } 1387 1388 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1389 struct mlx4_ib_counters *ctr_table) 1390 { 1391 struct counter_index *counter, *tmp_count; 1392 1393 mutex_lock(&ctr_table->mutex); 1394 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1395 list) { 1396 if (counter->allocated) 1397 mlx4_counter_free(ibdev->dev, counter->index); 1398 list_del(&counter->list); 1399 kfree(counter); 1400 } 1401 mutex_unlock(&ctr_table->mutex); 1402 } 1403 1404 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1405 union ib_gid *gid) 1406 { 1407 struct net_device *ndev; 1408 int ret = 0; 1409 1410 if (!mqp->port) 1411 return 0; 1412 1413 spin_lock_bh(&mdev->iboe.lock); 1414 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1415 if (ndev) 1416 dev_hold(ndev); 1417 spin_unlock_bh(&mdev->iboe.lock); 1418 1419 if (ndev) { 1420 ret = 1; 1421 dev_put(ndev); 1422 } 1423 1424 return ret; 1425 } 1426 1427 struct mlx4_ib_steering { 1428 struct list_head list; 1429 struct mlx4_flow_reg_id reg_id; 1430 union ib_gid gid; 1431 }; 1432 1433 #define LAST_ETH_FIELD vlan_tag 1434 #define LAST_IB_FIELD sl 1435 #define LAST_IPV4_FIELD dst_ip 1436 #define LAST_TCP_UDP_FIELD src_port 1437 1438 /* Field is the last supported field */ 1439 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1440 memchr_inv((void *)&filter.field +\ 1441 sizeof(filter.field), 0,\ 1442 sizeof(filter) -\ 1443 offsetof(typeof(filter), field) -\ 1444 sizeof(filter.field)) 1445 1446 static int parse_flow_attr(struct mlx4_dev *dev, 1447 u32 qp_num, 1448 union ib_flow_spec *ib_spec, 1449 struct _rule_hw *mlx4_spec) 1450 { 1451 enum mlx4_net_trans_rule_id type; 1452 1453 switch (ib_spec->type) { 1454 case IB_FLOW_SPEC_ETH: 1455 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1456 return -ENOTSUPP; 1457 1458 type = MLX4_NET_TRANS_RULE_ID_ETH; 1459 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1460 ETH_ALEN); 1461 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1462 ETH_ALEN); 1463 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1464 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1465 break; 1466 case IB_FLOW_SPEC_IB: 1467 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1468 return -ENOTSUPP; 1469 1470 type = MLX4_NET_TRANS_RULE_ID_IB; 1471 mlx4_spec->ib.l3_qpn = 1472 cpu_to_be32(qp_num); 1473 mlx4_spec->ib.qpn_mask = 1474 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1475 break; 1476 1477 1478 case IB_FLOW_SPEC_IPV4: 1479 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1480 return -ENOTSUPP; 1481 1482 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1483 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1484 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1485 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1486 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1487 break; 1488 1489 case IB_FLOW_SPEC_TCP: 1490 case IB_FLOW_SPEC_UDP: 1491 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1492 return -ENOTSUPP; 1493 1494 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1495 MLX4_NET_TRANS_RULE_ID_TCP : 1496 MLX4_NET_TRANS_RULE_ID_UDP; 1497 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1498 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1499 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1500 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1501 break; 1502 1503 default: 1504 return -EINVAL; 1505 } 1506 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1507 mlx4_hw_rule_sz(dev, type) < 0) 1508 return -EINVAL; 1509 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1510 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1511 return mlx4_hw_rule_sz(dev, type); 1512 } 1513 1514 struct default_rules { 1515 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1516 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1517 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1518 __u8 link_layer; 1519 }; 1520 static const struct default_rules default_table[] = { 1521 { 1522 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1523 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1524 .rules_create_list = {IB_FLOW_SPEC_IB}, 1525 .link_layer = IB_LINK_LAYER_INFINIBAND 1526 } 1527 }; 1528 1529 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1530 struct ib_flow_attr *flow_attr) 1531 { 1532 int i, j, k; 1533 void *ib_flow; 1534 const struct default_rules *pdefault_rules = default_table; 1535 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1536 1537 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1538 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1539 memset(&field_types, 0, sizeof(field_types)); 1540 1541 if (link_layer != pdefault_rules->link_layer) 1542 continue; 1543 1544 ib_flow = flow_attr + 1; 1545 /* we assume the specs are sorted */ 1546 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1547 j < flow_attr->num_of_specs; k++) { 1548 union ib_flow_spec *current_flow = 1549 (union ib_flow_spec *)ib_flow; 1550 1551 /* same layer but different type */ 1552 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1553 (pdefault_rules->mandatory_fields[k] & 1554 IB_FLOW_SPEC_LAYER_MASK)) && 1555 (current_flow->type != 1556 pdefault_rules->mandatory_fields[k])) 1557 goto out; 1558 1559 /* same layer, try match next one */ 1560 if (current_flow->type == 1561 pdefault_rules->mandatory_fields[k]) { 1562 j++; 1563 ib_flow += 1564 ((union ib_flow_spec *)ib_flow)->size; 1565 } 1566 } 1567 1568 ib_flow = flow_attr + 1; 1569 for (j = 0; j < flow_attr->num_of_specs; 1570 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1571 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1572 /* same layer and same type */ 1573 if (((union ib_flow_spec *)ib_flow)->type == 1574 pdefault_rules->mandatory_not_fields[k]) 1575 goto out; 1576 1577 return i; 1578 } 1579 out: 1580 return -1; 1581 } 1582 1583 static int __mlx4_ib_create_default_rules( 1584 struct mlx4_ib_dev *mdev, 1585 struct ib_qp *qp, 1586 const struct default_rules *pdefault_rules, 1587 struct _rule_hw *mlx4_spec) { 1588 int size = 0; 1589 int i; 1590 1591 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1592 int ret; 1593 union ib_flow_spec ib_spec; 1594 switch (pdefault_rules->rules_create_list[i]) { 1595 case 0: 1596 /* no rule */ 1597 continue; 1598 case IB_FLOW_SPEC_IB: 1599 ib_spec.type = IB_FLOW_SPEC_IB; 1600 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1601 1602 break; 1603 default: 1604 /* invalid rule */ 1605 return -EINVAL; 1606 } 1607 /* We must put empty rule, qpn is being ignored */ 1608 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1609 mlx4_spec); 1610 if (ret < 0) { 1611 pr_info("invalid parsing\n"); 1612 return -EINVAL; 1613 } 1614 1615 mlx4_spec = (void *)mlx4_spec + ret; 1616 size += ret; 1617 } 1618 return size; 1619 } 1620 1621 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1622 int domain, 1623 enum mlx4_net_trans_promisc_mode flow_type, 1624 u64 *reg_id) 1625 { 1626 int ret, i; 1627 int size = 0; 1628 void *ib_flow; 1629 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1630 struct mlx4_cmd_mailbox *mailbox; 1631 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1632 int default_flow; 1633 1634 static const u16 __mlx4_domain[] = { 1635 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1636 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1637 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1638 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1639 }; 1640 1641 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1642 pr_err("Invalid priority value %d\n", flow_attr->priority); 1643 return -EINVAL; 1644 } 1645 1646 if (domain >= IB_FLOW_DOMAIN_NUM) { 1647 pr_err("Invalid domain value %d\n", domain); 1648 return -EINVAL; 1649 } 1650 1651 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1652 return -EINVAL; 1653 1654 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1655 if (IS_ERR(mailbox)) 1656 return PTR_ERR(mailbox); 1657 ctrl = mailbox->buf; 1658 1659 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1660 flow_attr->priority); 1661 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1662 ctrl->port = flow_attr->port; 1663 ctrl->qpn = cpu_to_be32(qp->qp_num); 1664 1665 ib_flow = flow_attr + 1; 1666 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1667 /* Add default flows */ 1668 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1669 if (default_flow >= 0) { 1670 ret = __mlx4_ib_create_default_rules( 1671 mdev, qp, default_table + default_flow, 1672 mailbox->buf + size); 1673 if (ret < 0) { 1674 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1675 return -EINVAL; 1676 } 1677 size += ret; 1678 } 1679 for (i = 0; i < flow_attr->num_of_specs; i++) { 1680 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1681 mailbox->buf + size); 1682 if (ret < 0) { 1683 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1684 return -EINVAL; 1685 } 1686 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1687 size += ret; 1688 } 1689 1690 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1691 flow_attr->num_of_specs == 1) { 1692 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1693 enum ib_flow_spec_type header_spec = 1694 ((union ib_flow_spec *)(flow_attr + 1))->type; 1695 1696 if (header_spec == IB_FLOW_SPEC_ETH) 1697 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1698 } 1699 1700 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1701 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1702 MLX4_CMD_NATIVE); 1703 if (ret == -ENOMEM) 1704 pr_err("mcg table is full. Fail to register network rule.\n"); 1705 else if (ret == -ENXIO) 1706 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1707 else if (ret) 1708 pr_err("Invalid argument. Fail to register network rule.\n"); 1709 1710 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1711 return ret; 1712 } 1713 1714 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1715 { 1716 int err; 1717 err = mlx4_cmd(dev, reg_id, 0, 0, 1718 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1719 MLX4_CMD_NATIVE); 1720 if (err) 1721 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1722 reg_id); 1723 return err; 1724 } 1725 1726 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1727 u64 *reg_id) 1728 { 1729 void *ib_flow; 1730 union ib_flow_spec *ib_spec; 1731 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1732 int err = 0; 1733 1734 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1735 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1736 return 0; /* do nothing */ 1737 1738 ib_flow = flow_attr + 1; 1739 ib_spec = (union ib_flow_spec *)ib_flow; 1740 1741 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1742 return 0; /* do nothing */ 1743 1744 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1745 flow_attr->port, qp->qp_num, 1746 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1747 reg_id); 1748 return err; 1749 } 1750 1751 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1752 struct ib_flow_attr *flow_attr, 1753 enum mlx4_net_trans_promisc_mode *type) 1754 { 1755 int err = 0; 1756 1757 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1758 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1759 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1760 return -EOPNOTSUPP; 1761 } 1762 1763 if (flow_attr->num_of_specs == 0) { 1764 type[0] = MLX4_FS_MC_SNIFFER; 1765 type[1] = MLX4_FS_UC_SNIFFER; 1766 } else { 1767 union ib_flow_spec *ib_spec; 1768 1769 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1770 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1771 return -EINVAL; 1772 1773 /* if all is zero than MC and UC */ 1774 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1775 type[0] = MLX4_FS_MC_SNIFFER; 1776 type[1] = MLX4_FS_UC_SNIFFER; 1777 } else { 1778 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1779 ib_spec->eth.mask.dst_mac[1], 1780 ib_spec->eth.mask.dst_mac[2], 1781 ib_spec->eth.mask.dst_mac[3], 1782 ib_spec->eth.mask.dst_mac[4], 1783 ib_spec->eth.mask.dst_mac[5]}; 1784 1785 /* Above xor was only on MC bit, non empty mask is valid 1786 * only if this bit is set and rest are zero. 1787 */ 1788 if (!is_zero_ether_addr(&mac[0])) 1789 return -EINVAL; 1790 1791 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1792 type[0] = MLX4_FS_MC_SNIFFER; 1793 else 1794 type[0] = MLX4_FS_UC_SNIFFER; 1795 } 1796 } 1797 1798 return err; 1799 } 1800 1801 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1802 struct ib_flow_attr *flow_attr, 1803 int domain) 1804 { 1805 int err = 0, i = 0, j = 0; 1806 struct mlx4_ib_flow *mflow; 1807 enum mlx4_net_trans_promisc_mode type[2]; 1808 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1809 int is_bonded = mlx4_is_bonded(dev); 1810 1811 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1812 return ERR_PTR(-EINVAL); 1813 1814 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1815 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1816 return ERR_PTR(-EOPNOTSUPP); 1817 1818 memset(type, 0, sizeof(type)); 1819 1820 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1821 if (!mflow) { 1822 err = -ENOMEM; 1823 goto err_free; 1824 } 1825 1826 switch (flow_attr->type) { 1827 case IB_FLOW_ATTR_NORMAL: 1828 /* If dont trap flag (continue match) is set, under specific 1829 * condition traffic be replicated to given qp, 1830 * without stealing it 1831 */ 1832 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1833 err = mlx4_ib_add_dont_trap_rule(dev, 1834 flow_attr, 1835 type); 1836 if (err) 1837 goto err_free; 1838 } else { 1839 type[0] = MLX4_FS_REGULAR; 1840 } 1841 break; 1842 1843 case IB_FLOW_ATTR_ALL_DEFAULT: 1844 type[0] = MLX4_FS_ALL_DEFAULT; 1845 break; 1846 1847 case IB_FLOW_ATTR_MC_DEFAULT: 1848 type[0] = MLX4_FS_MC_DEFAULT; 1849 break; 1850 1851 case IB_FLOW_ATTR_SNIFFER: 1852 type[0] = MLX4_FS_MIRROR_RX_PORT; 1853 type[1] = MLX4_FS_MIRROR_SX_PORT; 1854 break; 1855 1856 default: 1857 err = -EINVAL; 1858 goto err_free; 1859 } 1860 1861 while (i < ARRAY_SIZE(type) && type[i]) { 1862 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1863 &mflow->reg_id[i].id); 1864 if (err) 1865 goto err_create_flow; 1866 if (is_bonded) { 1867 /* Application always sees one port so the mirror rule 1868 * must be on port #2 1869 */ 1870 flow_attr->port = 2; 1871 err = __mlx4_ib_create_flow(qp, flow_attr, 1872 domain, type[j], 1873 &mflow->reg_id[j].mirror); 1874 flow_attr->port = 1; 1875 if (err) 1876 goto err_create_flow; 1877 j++; 1878 } 1879 1880 i++; 1881 } 1882 1883 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1884 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1885 &mflow->reg_id[i].id); 1886 if (err) 1887 goto err_create_flow; 1888 1889 if (is_bonded) { 1890 flow_attr->port = 2; 1891 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1892 &mflow->reg_id[j].mirror); 1893 flow_attr->port = 1; 1894 if (err) 1895 goto err_create_flow; 1896 j++; 1897 } 1898 /* function to create mirror rule */ 1899 i++; 1900 } 1901 1902 return &mflow->ibflow; 1903 1904 err_create_flow: 1905 while (i) { 1906 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1907 mflow->reg_id[i].id); 1908 i--; 1909 } 1910 1911 while (j) { 1912 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1913 mflow->reg_id[j].mirror); 1914 j--; 1915 } 1916 err_free: 1917 kfree(mflow); 1918 return ERR_PTR(err); 1919 } 1920 1921 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1922 { 1923 int err, ret = 0; 1924 int i = 0; 1925 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1926 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1927 1928 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1929 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1930 if (err) 1931 ret = err; 1932 if (mflow->reg_id[i].mirror) { 1933 err = __mlx4_ib_destroy_flow(mdev->dev, 1934 mflow->reg_id[i].mirror); 1935 if (err) 1936 ret = err; 1937 } 1938 i++; 1939 } 1940 1941 kfree(mflow); 1942 return ret; 1943 } 1944 1945 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1946 { 1947 int err; 1948 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1949 struct mlx4_dev *dev = mdev->dev; 1950 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1951 struct mlx4_ib_steering *ib_steering = NULL; 1952 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1953 struct mlx4_flow_reg_id reg_id; 1954 1955 if (mdev->dev->caps.steering_mode == 1956 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1957 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1958 if (!ib_steering) 1959 return -ENOMEM; 1960 } 1961 1962 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1963 !!(mqp->flags & 1964 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1965 prot, ®_id.id); 1966 if (err) { 1967 pr_err("multicast attach op failed, err %d\n", err); 1968 goto err_malloc; 1969 } 1970 1971 reg_id.mirror = 0; 1972 if (mlx4_is_bonded(dev)) { 1973 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1974 (mqp->port == 1) ? 2 : 1, 1975 !!(mqp->flags & 1976 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1977 prot, ®_id.mirror); 1978 if (err) 1979 goto err_add; 1980 } 1981 1982 err = add_gid_entry(ibqp, gid); 1983 if (err) 1984 goto err_add; 1985 1986 if (ib_steering) { 1987 memcpy(ib_steering->gid.raw, gid->raw, 16); 1988 ib_steering->reg_id = reg_id; 1989 mutex_lock(&mqp->mutex); 1990 list_add(&ib_steering->list, &mqp->steering_rules); 1991 mutex_unlock(&mqp->mutex); 1992 } 1993 return 0; 1994 1995 err_add: 1996 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1997 prot, reg_id.id); 1998 if (reg_id.mirror) 1999 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2000 prot, reg_id.mirror); 2001 err_malloc: 2002 kfree(ib_steering); 2003 2004 return err; 2005 } 2006 2007 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 2008 { 2009 struct mlx4_ib_gid_entry *ge; 2010 struct mlx4_ib_gid_entry *tmp; 2011 struct mlx4_ib_gid_entry *ret = NULL; 2012 2013 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 2014 if (!memcmp(raw, ge->gid.raw, 16)) { 2015 ret = ge; 2016 break; 2017 } 2018 } 2019 2020 return ret; 2021 } 2022 2023 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2024 { 2025 int err; 2026 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2027 struct mlx4_dev *dev = mdev->dev; 2028 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2029 struct net_device *ndev; 2030 struct mlx4_ib_gid_entry *ge; 2031 struct mlx4_flow_reg_id reg_id = {0, 0}; 2032 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2033 2034 if (mdev->dev->caps.steering_mode == 2035 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2036 struct mlx4_ib_steering *ib_steering; 2037 2038 mutex_lock(&mqp->mutex); 2039 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 2040 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 2041 list_del(&ib_steering->list); 2042 break; 2043 } 2044 } 2045 mutex_unlock(&mqp->mutex); 2046 if (&ib_steering->list == &mqp->steering_rules) { 2047 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 2048 return -EINVAL; 2049 } 2050 reg_id = ib_steering->reg_id; 2051 kfree(ib_steering); 2052 } 2053 2054 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2055 prot, reg_id.id); 2056 if (err) 2057 return err; 2058 2059 if (mlx4_is_bonded(dev)) { 2060 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2061 prot, reg_id.mirror); 2062 if (err) 2063 return err; 2064 } 2065 2066 mutex_lock(&mqp->mutex); 2067 ge = find_gid_entry(mqp, gid->raw); 2068 if (ge) { 2069 spin_lock_bh(&mdev->iboe.lock); 2070 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 2071 if (ndev) 2072 dev_hold(ndev); 2073 spin_unlock_bh(&mdev->iboe.lock); 2074 if (ndev) 2075 dev_put(ndev); 2076 list_del(&ge->list); 2077 kfree(ge); 2078 } else 2079 pr_warn("could not find mgid entry\n"); 2080 2081 mutex_unlock(&mqp->mutex); 2082 2083 return 0; 2084 } 2085 2086 static int init_node_data(struct mlx4_ib_dev *dev) 2087 { 2088 struct ib_smp *in_mad = NULL; 2089 struct ib_smp *out_mad = NULL; 2090 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2091 int err = -ENOMEM; 2092 2093 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2094 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2095 if (!in_mad || !out_mad) 2096 goto out; 2097 2098 init_query_mad(in_mad); 2099 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2100 if (mlx4_is_master(dev->dev)) 2101 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2102 2103 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2104 if (err) 2105 goto out; 2106 2107 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2108 2109 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2110 2111 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2112 if (err) 2113 goto out; 2114 2115 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2116 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2117 2118 out: 2119 kfree(in_mad); 2120 kfree(out_mad); 2121 return err; 2122 } 2123 2124 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2125 char *buf) 2126 { 2127 struct mlx4_ib_dev *dev = 2128 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2129 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2130 } 2131 2132 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2133 char *buf) 2134 { 2135 struct mlx4_ib_dev *dev = 2136 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2137 return sprintf(buf, "%x\n", dev->dev->rev_id); 2138 } 2139 2140 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2141 char *buf) 2142 { 2143 struct mlx4_ib_dev *dev = 2144 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2145 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2146 dev->dev->board_id); 2147 } 2148 2149 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2150 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2151 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2152 2153 static struct device_attribute *mlx4_class_attributes[] = { 2154 &dev_attr_hw_rev, 2155 &dev_attr_hca_type, 2156 &dev_attr_board_id 2157 }; 2158 2159 struct diag_counter { 2160 const char *name; 2161 u32 offset; 2162 }; 2163 2164 #define DIAG_COUNTER(_name, _offset) \ 2165 { .name = #_name, .offset = _offset } 2166 2167 static const struct diag_counter diag_basic[] = { 2168 DIAG_COUNTER(rq_num_lle, 0x00), 2169 DIAG_COUNTER(sq_num_lle, 0x04), 2170 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2171 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2172 DIAG_COUNTER(rq_num_lpe, 0x18), 2173 DIAG_COUNTER(sq_num_lpe, 0x1C), 2174 DIAG_COUNTER(rq_num_wrfe, 0x20), 2175 DIAG_COUNTER(sq_num_wrfe, 0x24), 2176 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2177 DIAG_COUNTER(sq_num_bre, 0x34), 2178 DIAG_COUNTER(sq_num_rire, 0x44), 2179 DIAG_COUNTER(rq_num_rire, 0x48), 2180 DIAG_COUNTER(sq_num_rae, 0x4C), 2181 DIAG_COUNTER(rq_num_rae, 0x50), 2182 DIAG_COUNTER(sq_num_roe, 0x54), 2183 DIAG_COUNTER(sq_num_tree, 0x5C), 2184 DIAG_COUNTER(sq_num_rree, 0x64), 2185 DIAG_COUNTER(rq_num_rnr, 0x68), 2186 DIAG_COUNTER(sq_num_rnr, 0x6C), 2187 DIAG_COUNTER(rq_num_oos, 0x100), 2188 DIAG_COUNTER(sq_num_oos, 0x104), 2189 }; 2190 2191 static const struct diag_counter diag_ext[] = { 2192 DIAG_COUNTER(rq_num_dup, 0x130), 2193 DIAG_COUNTER(sq_num_to, 0x134), 2194 }; 2195 2196 static const struct diag_counter diag_device_only[] = { 2197 DIAG_COUNTER(num_cqovf, 0x1A0), 2198 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2199 }; 2200 2201 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2202 u8 port_num) 2203 { 2204 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2205 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2206 2207 if (!diag[!!port_num].name) 2208 return NULL; 2209 2210 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2211 diag[!!port_num].num_counters, 2212 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2213 } 2214 2215 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2216 struct rdma_hw_stats *stats, 2217 u8 port, int index) 2218 { 2219 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2220 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2221 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2222 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2223 int ret; 2224 int i; 2225 2226 ret = mlx4_query_diag_counters(dev->dev, 2227 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2228 diag[!!port].offset, hw_value, 2229 diag[!!port].num_counters, port); 2230 2231 if (ret) 2232 return ret; 2233 2234 for (i = 0; i < diag[!!port].num_counters; i++) 2235 stats->value[i] = hw_value[i]; 2236 2237 return diag[!!port].num_counters; 2238 } 2239 2240 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2241 const char ***name, 2242 u32 **offset, 2243 u32 *num, 2244 bool port) 2245 { 2246 u32 num_counters; 2247 2248 num_counters = ARRAY_SIZE(diag_basic); 2249 2250 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2251 num_counters += ARRAY_SIZE(diag_ext); 2252 2253 if (!port) 2254 num_counters += ARRAY_SIZE(diag_device_only); 2255 2256 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2257 if (!*name) 2258 return -ENOMEM; 2259 2260 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2261 if (!*offset) 2262 goto err_name; 2263 2264 *num = num_counters; 2265 2266 return 0; 2267 2268 err_name: 2269 kfree(*name); 2270 return -ENOMEM; 2271 } 2272 2273 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2274 const char **name, 2275 u32 *offset, 2276 bool port) 2277 { 2278 int i; 2279 int j; 2280 2281 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2282 name[i] = diag_basic[i].name; 2283 offset[i] = diag_basic[i].offset; 2284 } 2285 2286 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2287 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2288 name[j] = diag_ext[i].name; 2289 offset[j] = diag_ext[i].offset; 2290 } 2291 } 2292 2293 if (!port) { 2294 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2295 name[j] = diag_device_only[i].name; 2296 offset[j] = diag_device_only[i].offset; 2297 } 2298 } 2299 } 2300 2301 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2302 { 2303 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2304 int i; 2305 int ret; 2306 bool per_port = !!(ibdev->dev->caps.flags2 & 2307 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2308 2309 if (mlx4_is_slave(ibdev->dev)) 2310 return 0; 2311 2312 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2313 /* i == 1 means we are building port counters */ 2314 if (i && !per_port) 2315 continue; 2316 2317 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2318 &diag[i].offset, 2319 &diag[i].num_counters, i); 2320 if (ret) 2321 goto err_alloc; 2322 2323 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2324 diag[i].offset, i); 2325 } 2326 2327 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2328 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2329 2330 return 0; 2331 2332 err_alloc: 2333 if (i) { 2334 kfree(diag[i - 1].name); 2335 kfree(diag[i - 1].offset); 2336 } 2337 2338 return ret; 2339 } 2340 2341 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2342 { 2343 int i; 2344 2345 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2346 kfree(ibdev->diag_counters[i].offset); 2347 kfree(ibdev->diag_counters[i].name); 2348 } 2349 } 2350 2351 #define MLX4_IB_INVALID_MAC ((u64)-1) 2352 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2353 struct net_device *dev, 2354 int port) 2355 { 2356 u64 new_smac = 0; 2357 u64 release_mac = MLX4_IB_INVALID_MAC; 2358 struct mlx4_ib_qp *qp; 2359 2360 read_lock(&dev_base_lock); 2361 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2362 read_unlock(&dev_base_lock); 2363 2364 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2365 2366 /* no need for update QP1 and mac registration in non-SRIOV */ 2367 if (!mlx4_is_mfunc(ibdev->dev)) 2368 return; 2369 2370 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2371 qp = ibdev->qp1_proxy[port - 1]; 2372 if (qp) { 2373 int new_smac_index; 2374 u64 old_smac; 2375 struct mlx4_update_qp_params update_params; 2376 2377 mutex_lock(&qp->mutex); 2378 old_smac = qp->pri.smac; 2379 if (new_smac == old_smac) 2380 goto unlock; 2381 2382 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2383 2384 if (new_smac_index < 0) 2385 goto unlock; 2386 2387 update_params.smac_index = new_smac_index; 2388 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2389 &update_params)) { 2390 release_mac = new_smac; 2391 goto unlock; 2392 } 2393 /* if old port was zero, no mac was yet registered for this QP */ 2394 if (qp->pri.smac_port) 2395 release_mac = old_smac; 2396 qp->pri.smac = new_smac; 2397 qp->pri.smac_port = port; 2398 qp->pri.smac_index = new_smac_index; 2399 } 2400 2401 unlock: 2402 if (release_mac != MLX4_IB_INVALID_MAC) 2403 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2404 if (qp) 2405 mutex_unlock(&qp->mutex); 2406 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2407 } 2408 2409 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2410 struct net_device *dev, 2411 unsigned long event) 2412 2413 { 2414 struct mlx4_ib_iboe *iboe; 2415 int update_qps_port = -1; 2416 int port; 2417 2418 ASSERT_RTNL(); 2419 2420 iboe = &ibdev->iboe; 2421 2422 spin_lock_bh(&iboe->lock); 2423 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2424 2425 iboe->netdevs[port - 1] = 2426 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2427 2428 if (dev == iboe->netdevs[port - 1] && 2429 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2430 event == NETDEV_UP || event == NETDEV_CHANGE)) 2431 update_qps_port = port; 2432 2433 } 2434 spin_unlock_bh(&iboe->lock); 2435 2436 if (update_qps_port > 0) 2437 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2438 } 2439 2440 static int mlx4_ib_netdev_event(struct notifier_block *this, 2441 unsigned long event, void *ptr) 2442 { 2443 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2444 struct mlx4_ib_dev *ibdev; 2445 2446 if (!net_eq(dev_net(dev), &init_net)) 2447 return NOTIFY_DONE; 2448 2449 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2450 mlx4_ib_scan_netdevs(ibdev, dev, event); 2451 2452 return NOTIFY_DONE; 2453 } 2454 2455 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2456 { 2457 int port; 2458 int slave; 2459 int i; 2460 2461 if (mlx4_is_master(ibdev->dev)) { 2462 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2463 ++slave) { 2464 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2465 for (i = 0; 2466 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2467 ++i) { 2468 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2469 /* master has the identity virt2phys pkey mapping */ 2470 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2471 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2472 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2473 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2474 } 2475 } 2476 } 2477 /* initialize pkey cache */ 2478 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2479 for (i = 0; 2480 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2481 ++i) 2482 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2483 (i) ? 0 : 0xFFFF; 2484 } 2485 } 2486 } 2487 2488 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2489 { 2490 int i, j, eq = 0, total_eqs = 0; 2491 2492 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2493 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2494 if (!ibdev->eq_table) 2495 return; 2496 2497 for (i = 1; i <= dev->caps.num_ports; i++) { 2498 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2499 j++, total_eqs++) { 2500 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2501 continue; 2502 ibdev->eq_table[eq] = total_eqs; 2503 if (!mlx4_assign_eq(dev, i, 2504 &ibdev->eq_table[eq])) 2505 eq++; 2506 else 2507 ibdev->eq_table[eq] = -1; 2508 } 2509 } 2510 2511 for (i = eq; i < dev->caps.num_comp_vectors; 2512 ibdev->eq_table[i++] = -1) 2513 ; 2514 2515 /* Advertise the new number of EQs to clients */ 2516 ibdev->ib_dev.num_comp_vectors = eq; 2517 } 2518 2519 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2520 { 2521 int i; 2522 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2523 2524 /* no eqs were allocated */ 2525 if (!ibdev->eq_table) 2526 return; 2527 2528 /* Reset the advertised EQ number */ 2529 ibdev->ib_dev.num_comp_vectors = 0; 2530 2531 for (i = 0; i < total_eqs; i++) 2532 mlx4_release_eq(dev, ibdev->eq_table[i]); 2533 2534 kfree(ibdev->eq_table); 2535 ibdev->eq_table = NULL; 2536 } 2537 2538 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2539 struct ib_port_immutable *immutable) 2540 { 2541 struct ib_port_attr attr; 2542 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2543 int err; 2544 2545 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2546 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2547 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2548 } else { 2549 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2550 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2551 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2552 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2553 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2554 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2555 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2556 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2557 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2558 } 2559 2560 err = ib_query_port(ibdev, port_num, &attr); 2561 if (err) 2562 return err; 2563 2564 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2565 immutable->gid_tbl_len = attr.gid_tbl_len; 2566 2567 return 0; 2568 } 2569 2570 static void get_fw_ver_str(struct ib_device *device, char *str, 2571 size_t str_len) 2572 { 2573 struct mlx4_ib_dev *dev = 2574 container_of(device, struct mlx4_ib_dev, ib_dev); 2575 snprintf(str, str_len, "%d.%d.%d", 2576 (int) (dev->dev->caps.fw_ver >> 32), 2577 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2578 (int) dev->dev->caps.fw_ver & 0xffff); 2579 } 2580 2581 static void *mlx4_ib_add(struct mlx4_dev *dev) 2582 { 2583 struct mlx4_ib_dev *ibdev; 2584 int num_ports = 0; 2585 int i, j; 2586 int err; 2587 struct mlx4_ib_iboe *iboe; 2588 int ib_num_ports = 0; 2589 int num_req_counters; 2590 int allocated; 2591 u32 counter_index; 2592 struct counter_index *new_counter_index = NULL; 2593 2594 pr_info_once("%s", mlx4_ib_version); 2595 2596 num_ports = 0; 2597 mlx4_foreach_ib_transport_port(i, dev) 2598 num_ports++; 2599 2600 /* No point in registering a device with no ports... */ 2601 if (num_ports == 0) 2602 return NULL; 2603 2604 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2605 if (!ibdev) { 2606 dev_err(&dev->persist->pdev->dev, 2607 "Device struct alloc failed\n"); 2608 return NULL; 2609 } 2610 2611 iboe = &ibdev->iboe; 2612 2613 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2614 goto err_dealloc; 2615 2616 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2617 goto err_pd; 2618 2619 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2620 PAGE_SIZE); 2621 if (!ibdev->uar_map) 2622 goto err_uar; 2623 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2624 2625 ibdev->dev = dev; 2626 ibdev->bond_next_port = 0; 2627 2628 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); 2629 ibdev->ib_dev.owner = THIS_MODULE; 2630 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2631 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2632 ibdev->num_ports = num_ports; 2633 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2634 1 : ibdev->num_ports; 2635 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2636 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2637 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2638 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2639 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2640 2641 if (dev->caps.userspace_caps) 2642 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2643 else 2644 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2645 2646 ibdev->ib_dev.uverbs_cmd_mask = 2647 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2648 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2649 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2650 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2651 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2652 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2653 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2654 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2655 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2656 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2657 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2658 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2659 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2660 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2661 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2662 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2663 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2664 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2665 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2666 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2667 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2668 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2669 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2670 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2671 2672 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2673 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2674 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2675 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2676 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2677 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2678 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2679 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2680 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2681 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2682 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2683 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2684 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2685 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2686 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2687 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2688 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2689 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2690 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2691 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2692 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2693 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2694 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2695 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2696 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2697 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2698 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2699 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2700 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2701 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2702 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2703 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2704 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2705 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2706 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2707 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2708 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2709 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2710 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2711 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2712 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2713 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2714 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2715 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2716 2717 if (!mlx4_is_slave(ibdev->dev)) { 2718 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2719 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2720 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2721 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2722 } 2723 2724 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2725 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2726 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2727 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2728 2729 ibdev->ib_dev.uverbs_cmd_mask |= 2730 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2731 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2732 } 2733 2734 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2735 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2736 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2737 ibdev->ib_dev.uverbs_cmd_mask |= 2738 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2739 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2740 } 2741 2742 if (check_flow_steering_support(dev)) { 2743 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2744 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2745 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2746 2747 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2748 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2749 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2750 } 2751 2752 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2753 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2754 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2755 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2756 2757 mlx4_ib_alloc_eqs(dev, ibdev); 2758 2759 spin_lock_init(&iboe->lock); 2760 2761 if (init_node_data(ibdev)) 2762 goto err_map; 2763 mlx4_init_sl2vl_tbl(ibdev); 2764 2765 for (i = 0; i < ibdev->num_ports; ++i) { 2766 mutex_init(&ibdev->counters_table[i].mutex); 2767 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2768 } 2769 2770 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2771 for (i = 0; i < num_req_counters; ++i) { 2772 mutex_init(&ibdev->qp1_proxy_lock[i]); 2773 allocated = 0; 2774 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2775 IB_LINK_LAYER_ETHERNET) { 2776 err = mlx4_counter_alloc(ibdev->dev, &counter_index); 2777 /* if failed to allocate a new counter, use default */ 2778 if (err) 2779 counter_index = 2780 mlx4_get_default_counter_index(dev, 2781 i + 1); 2782 else 2783 allocated = 1; 2784 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2785 counter_index = mlx4_get_default_counter_index(dev, 2786 i + 1); 2787 } 2788 new_counter_index = kmalloc(sizeof(*new_counter_index), 2789 GFP_KERNEL); 2790 if (!new_counter_index) { 2791 if (allocated) 2792 mlx4_counter_free(ibdev->dev, counter_index); 2793 goto err_counter; 2794 } 2795 new_counter_index->index = counter_index; 2796 new_counter_index->allocated = allocated; 2797 list_add_tail(&new_counter_index->list, 2798 &ibdev->counters_table[i].counters_list); 2799 ibdev->counters_table[i].default_counter = counter_index; 2800 pr_info("counter index %d for port %d allocated %d\n", 2801 counter_index, i + 1, allocated); 2802 } 2803 if (mlx4_is_bonded(dev)) 2804 for (i = 1; i < ibdev->num_ports ; ++i) { 2805 new_counter_index = 2806 kmalloc(sizeof(struct counter_index), 2807 GFP_KERNEL); 2808 if (!new_counter_index) 2809 goto err_counter; 2810 new_counter_index->index = counter_index; 2811 new_counter_index->allocated = 0; 2812 list_add_tail(&new_counter_index->list, 2813 &ibdev->counters_table[i].counters_list); 2814 ibdev->counters_table[i].default_counter = 2815 counter_index; 2816 } 2817 2818 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2819 ib_num_ports++; 2820 2821 spin_lock_init(&ibdev->sm_lock); 2822 mutex_init(&ibdev->cap_mask_mutex); 2823 INIT_LIST_HEAD(&ibdev->qp_list); 2824 spin_lock_init(&ibdev->reset_flow_resource_lock); 2825 2826 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2827 ib_num_ports) { 2828 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2829 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2830 MLX4_IB_UC_STEER_QPN_ALIGN, 2831 &ibdev->steer_qpn_base, 0); 2832 if (err) 2833 goto err_counter; 2834 2835 ibdev->ib_uc_qpns_bitmap = 2836 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) * 2837 sizeof(long), 2838 GFP_KERNEL); 2839 if (!ibdev->ib_uc_qpns_bitmap) 2840 goto err_steer_qp_release; 2841 2842 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2843 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2844 ibdev->steer_qpn_count); 2845 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2846 dev, ibdev->steer_qpn_base, 2847 ibdev->steer_qpn_base + 2848 ibdev->steer_qpn_count - 1); 2849 if (err) 2850 goto err_steer_free_bitmap; 2851 } else { 2852 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2853 ibdev->steer_qpn_count); 2854 } 2855 } 2856 2857 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2858 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2859 2860 if (mlx4_ib_alloc_diag_counters(ibdev)) 2861 goto err_steer_free_bitmap; 2862 2863 if (ib_register_device(&ibdev->ib_dev, NULL)) 2864 goto err_diag_counters; 2865 2866 if (mlx4_ib_mad_init(ibdev)) 2867 goto err_reg; 2868 2869 if (mlx4_ib_init_sriov(ibdev)) 2870 goto err_mad; 2871 2872 if (!iboe->nb.notifier_call) { 2873 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2874 err = register_netdevice_notifier(&iboe->nb); 2875 if (err) { 2876 iboe->nb.notifier_call = NULL; 2877 goto err_notif; 2878 } 2879 } 2880 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2881 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2882 if (err) 2883 goto err_notif; 2884 } 2885 2886 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { 2887 if (device_create_file(&ibdev->ib_dev.dev, 2888 mlx4_class_attributes[j])) 2889 goto err_notif; 2890 } 2891 2892 ibdev->ib_active = true; 2893 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2894 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2895 &ibdev->ib_dev); 2896 2897 if (mlx4_is_mfunc(ibdev->dev)) 2898 init_pkeys(ibdev); 2899 2900 /* create paravirt contexts for any VFs which are active */ 2901 if (mlx4_is_master(ibdev->dev)) { 2902 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2903 if (j == mlx4_master_func_num(ibdev->dev)) 2904 continue; 2905 if (mlx4_is_slave_active(ibdev->dev, j)) 2906 do_slave_init(ibdev, j, 1); 2907 } 2908 } 2909 return ibdev; 2910 2911 err_notif: 2912 if (ibdev->iboe.nb.notifier_call) { 2913 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2914 pr_warn("failure unregistering notifier\n"); 2915 ibdev->iboe.nb.notifier_call = NULL; 2916 } 2917 flush_workqueue(wq); 2918 2919 mlx4_ib_close_sriov(ibdev); 2920 2921 err_mad: 2922 mlx4_ib_mad_cleanup(ibdev); 2923 2924 err_reg: 2925 ib_unregister_device(&ibdev->ib_dev); 2926 2927 err_diag_counters: 2928 mlx4_ib_diag_cleanup(ibdev); 2929 2930 err_steer_free_bitmap: 2931 kfree(ibdev->ib_uc_qpns_bitmap); 2932 2933 err_steer_qp_release: 2934 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 2935 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2936 ibdev->steer_qpn_count); 2937 err_counter: 2938 for (i = 0; i < ibdev->num_ports; ++i) 2939 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2940 2941 err_map: 2942 mlx4_ib_free_eqs(dev, ibdev); 2943 iounmap(ibdev->uar_map); 2944 2945 err_uar: 2946 mlx4_uar_free(dev, &ibdev->priv_uar); 2947 2948 err_pd: 2949 mlx4_pd_free(dev, ibdev->priv_pdn); 2950 2951 err_dealloc: 2952 ib_dealloc_device(&ibdev->ib_dev); 2953 2954 return NULL; 2955 } 2956 2957 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2958 { 2959 int offset; 2960 2961 WARN_ON(!dev->ib_uc_qpns_bitmap); 2962 2963 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 2964 dev->steer_qpn_count, 2965 get_count_order(count)); 2966 if (offset < 0) 2967 return offset; 2968 2969 *qpn = dev->steer_qpn_base + offset; 2970 return 0; 2971 } 2972 2973 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 2974 { 2975 if (!qpn || 2976 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 2977 return; 2978 2979 BUG_ON(qpn < dev->steer_qpn_base); 2980 2981 bitmap_release_region(dev->ib_uc_qpns_bitmap, 2982 qpn - dev->steer_qpn_base, 2983 get_count_order(count)); 2984 } 2985 2986 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 2987 int is_attach) 2988 { 2989 int err; 2990 size_t flow_size; 2991 struct ib_flow_attr *flow = NULL; 2992 struct ib_flow_spec_ib *ib_spec; 2993 2994 if (is_attach) { 2995 flow_size = sizeof(struct ib_flow_attr) + 2996 sizeof(struct ib_flow_spec_ib); 2997 flow = kzalloc(flow_size, GFP_KERNEL); 2998 if (!flow) 2999 return -ENOMEM; 3000 flow->port = mqp->port; 3001 flow->num_of_specs = 1; 3002 flow->size = flow_size; 3003 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3004 ib_spec->type = IB_FLOW_SPEC_IB; 3005 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3006 /* Add an empty rule for IB L2 */ 3007 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3008 3009 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3010 IB_FLOW_DOMAIN_NIC, 3011 MLX4_FS_REGULAR, 3012 &mqp->reg_id); 3013 } else { 3014 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3015 } 3016 kfree(flow); 3017 return err; 3018 } 3019 3020 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3021 { 3022 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3023 int p; 3024 int i; 3025 3026 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3027 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3028 ibdev->ib_active = false; 3029 flush_workqueue(wq); 3030 3031 mlx4_ib_close_sriov(ibdev); 3032 mlx4_ib_mad_cleanup(ibdev); 3033 ib_unregister_device(&ibdev->ib_dev); 3034 mlx4_ib_diag_cleanup(ibdev); 3035 if (ibdev->iboe.nb.notifier_call) { 3036 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3037 pr_warn("failure unregistering notifier\n"); 3038 ibdev->iboe.nb.notifier_call = NULL; 3039 } 3040 3041 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) { 3042 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3043 ibdev->steer_qpn_count); 3044 kfree(ibdev->ib_uc_qpns_bitmap); 3045 } 3046 3047 iounmap(ibdev->uar_map); 3048 for (p = 0; p < ibdev->num_ports; ++p) 3049 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3050 3051 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3052 mlx4_CLOSE_PORT(dev, p); 3053 3054 mlx4_ib_free_eqs(dev, ibdev); 3055 3056 mlx4_uar_free(dev, &ibdev->priv_uar); 3057 mlx4_pd_free(dev, ibdev->priv_pdn); 3058 ib_dealloc_device(&ibdev->ib_dev); 3059 } 3060 3061 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3062 { 3063 struct mlx4_ib_demux_work **dm = NULL; 3064 struct mlx4_dev *dev = ibdev->dev; 3065 int i; 3066 unsigned long flags; 3067 struct mlx4_active_ports actv_ports; 3068 unsigned int ports; 3069 unsigned int first_port; 3070 3071 if (!mlx4_is_master(dev)) 3072 return; 3073 3074 actv_ports = mlx4_get_active_ports(dev, slave); 3075 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3076 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3077 3078 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3079 if (!dm) 3080 return; 3081 3082 for (i = 0; i < ports; i++) { 3083 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3084 if (!dm[i]) { 3085 while (--i >= 0) 3086 kfree(dm[i]); 3087 goto out; 3088 } 3089 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3090 dm[i]->port = first_port + i + 1; 3091 dm[i]->slave = slave; 3092 dm[i]->do_init = do_init; 3093 dm[i]->dev = ibdev; 3094 } 3095 /* initialize or tear down tunnel QPs for the slave */ 3096 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3097 if (!ibdev->sriov.is_going_down) { 3098 for (i = 0; i < ports; i++) 3099 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3100 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3101 } else { 3102 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3103 for (i = 0; i < ports; i++) 3104 kfree(dm[i]); 3105 } 3106 out: 3107 kfree(dm); 3108 return; 3109 } 3110 3111 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3112 { 3113 struct mlx4_ib_qp *mqp; 3114 unsigned long flags_qp; 3115 unsigned long flags_cq; 3116 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3117 struct list_head cq_notify_list; 3118 struct mlx4_cq *mcq; 3119 unsigned long flags; 3120 3121 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3122 INIT_LIST_HEAD(&cq_notify_list); 3123 3124 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3125 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3126 3127 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3128 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3129 if (mqp->sq.tail != mqp->sq.head) { 3130 send_mcq = to_mcq(mqp->ibqp.send_cq); 3131 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3132 if (send_mcq->mcq.comp && 3133 mqp->ibqp.send_cq->comp_handler) { 3134 if (!send_mcq->mcq.reset_notify_added) { 3135 send_mcq->mcq.reset_notify_added = 1; 3136 list_add_tail(&send_mcq->mcq.reset_notify, 3137 &cq_notify_list); 3138 } 3139 } 3140 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3141 } 3142 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3143 /* Now, handle the QP's receive queue */ 3144 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3145 /* no handling is needed for SRQ */ 3146 if (!mqp->ibqp.srq) { 3147 if (mqp->rq.tail != mqp->rq.head) { 3148 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3149 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3150 if (recv_mcq->mcq.comp && 3151 mqp->ibqp.recv_cq->comp_handler) { 3152 if (!recv_mcq->mcq.reset_notify_added) { 3153 recv_mcq->mcq.reset_notify_added = 1; 3154 list_add_tail(&recv_mcq->mcq.reset_notify, 3155 &cq_notify_list); 3156 } 3157 } 3158 spin_unlock_irqrestore(&recv_mcq->lock, 3159 flags_cq); 3160 } 3161 } 3162 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3163 } 3164 3165 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3166 mcq->comp(mcq); 3167 } 3168 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3169 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3170 } 3171 3172 static void handle_bonded_port_state_event(struct work_struct *work) 3173 { 3174 struct ib_event_work *ew = 3175 container_of(work, struct ib_event_work, work); 3176 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3177 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3178 int i; 3179 struct ib_event ibev; 3180 3181 kfree(ew); 3182 spin_lock_bh(&ibdev->iboe.lock); 3183 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3184 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3185 enum ib_port_state curr_port_state; 3186 3187 if (!curr_netdev) 3188 continue; 3189 3190 curr_port_state = 3191 (netif_running(curr_netdev) && 3192 netif_carrier_ok(curr_netdev)) ? 3193 IB_PORT_ACTIVE : IB_PORT_DOWN; 3194 3195 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3196 curr_port_state : IB_PORT_ACTIVE; 3197 } 3198 spin_unlock_bh(&ibdev->iboe.lock); 3199 3200 ibev.device = &ibdev->ib_dev; 3201 ibev.element.port_num = 1; 3202 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3203 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3204 3205 ib_dispatch_event(&ibev); 3206 } 3207 3208 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3209 { 3210 u64 sl2vl; 3211 int err; 3212 3213 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3214 if (err) { 3215 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3216 port, err); 3217 sl2vl = 0; 3218 } 3219 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3220 } 3221 3222 static void ib_sl2vl_update_work(struct work_struct *work) 3223 { 3224 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3225 struct mlx4_ib_dev *mdev = ew->ib_dev; 3226 int port = ew->port; 3227 3228 mlx4_ib_sl2vl_update(mdev, port); 3229 3230 kfree(ew); 3231 } 3232 3233 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3234 int port) 3235 { 3236 struct ib_event_work *ew; 3237 3238 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3239 if (ew) { 3240 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3241 ew->port = port; 3242 ew->ib_dev = ibdev; 3243 queue_work(wq, &ew->work); 3244 } 3245 } 3246 3247 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3248 enum mlx4_dev_event event, unsigned long param) 3249 { 3250 struct ib_event ibev; 3251 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3252 struct mlx4_eqe *eqe = NULL; 3253 struct ib_event_work *ew; 3254 int p = 0; 3255 3256 if (mlx4_is_bonded(dev) && 3257 ((event == MLX4_DEV_EVENT_PORT_UP) || 3258 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3259 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3260 if (!ew) 3261 return; 3262 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3263 ew->ib_dev = ibdev; 3264 queue_work(wq, &ew->work); 3265 return; 3266 } 3267 3268 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3269 eqe = (struct mlx4_eqe *)param; 3270 else 3271 p = (int) param; 3272 3273 switch (event) { 3274 case MLX4_DEV_EVENT_PORT_UP: 3275 if (p > ibdev->num_ports) 3276 return; 3277 if (!mlx4_is_slave(dev) && 3278 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3279 IB_LINK_LAYER_INFINIBAND) { 3280 if (mlx4_is_master(dev)) 3281 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3282 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3283 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3284 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3285 } 3286 ibev.event = IB_EVENT_PORT_ACTIVE; 3287 break; 3288 3289 case MLX4_DEV_EVENT_PORT_DOWN: 3290 if (p > ibdev->num_ports) 3291 return; 3292 ibev.event = IB_EVENT_PORT_ERR; 3293 break; 3294 3295 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3296 ibdev->ib_active = false; 3297 ibev.event = IB_EVENT_DEVICE_FATAL; 3298 mlx4_ib_handle_catas_error(ibdev); 3299 break; 3300 3301 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3302 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3303 if (!ew) 3304 break; 3305 3306 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3307 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3308 ew->ib_dev = ibdev; 3309 /* need to queue only for port owner, which uses GEN_EQE */ 3310 if (mlx4_is_master(dev)) 3311 queue_work(wq, &ew->work); 3312 else 3313 handle_port_mgmt_change_event(&ew->work); 3314 return; 3315 3316 case MLX4_DEV_EVENT_SLAVE_INIT: 3317 /* here, p is the slave id */ 3318 do_slave_init(ibdev, p, 1); 3319 if (mlx4_is_master(dev)) { 3320 int i; 3321 3322 for (i = 1; i <= ibdev->num_ports; i++) { 3323 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3324 == IB_LINK_LAYER_INFINIBAND) 3325 mlx4_ib_slave_alias_guid_event(ibdev, 3326 p, i, 3327 1); 3328 } 3329 } 3330 return; 3331 3332 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3333 if (mlx4_is_master(dev)) { 3334 int i; 3335 3336 for (i = 1; i <= ibdev->num_ports; i++) { 3337 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3338 == IB_LINK_LAYER_INFINIBAND) 3339 mlx4_ib_slave_alias_guid_event(ibdev, 3340 p, i, 3341 0); 3342 } 3343 } 3344 /* here, p is the slave id */ 3345 do_slave_init(ibdev, p, 0); 3346 return; 3347 3348 default: 3349 return; 3350 } 3351 3352 ibev.device = ibdev_ptr; 3353 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3354 3355 ib_dispatch_event(&ibev); 3356 } 3357 3358 static struct mlx4_interface mlx4_ib_interface = { 3359 .add = mlx4_ib_add, 3360 .remove = mlx4_ib_remove, 3361 .event = mlx4_ib_event, 3362 .protocol = MLX4_PROT_IB_IPV6, 3363 .flags = MLX4_INTFF_BONDING 3364 }; 3365 3366 static int __init mlx4_ib_init(void) 3367 { 3368 int err; 3369 3370 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3371 if (!wq) 3372 return -ENOMEM; 3373 3374 err = mlx4_ib_mcg_init(); 3375 if (err) 3376 goto clean_wq; 3377 3378 err = mlx4_register_interface(&mlx4_ib_interface); 3379 if (err) 3380 goto clean_mcg; 3381 3382 return 0; 3383 3384 clean_mcg: 3385 mlx4_ib_mcg_destroy(); 3386 3387 clean_wq: 3388 destroy_workqueue(wq); 3389 return err; 3390 } 3391 3392 static void __exit mlx4_ib_cleanup(void) 3393 { 3394 mlx4_unregister_interface(&mlx4_ib_interface); 3395 mlx4_ib_mcg_destroy(); 3396 destroy_workqueue(wq); 3397 } 3398 3399 module_init(mlx4_ib_init); 3400 module_exit(mlx4_ib_cleanup); 3401