1d5edd333SMustafa Ismail /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 2d5edd333SMustafa Ismail /* Copyright (c) 2021 - 2024 Intel Corporation */ 3d5edd333SMustafa Ismail #ifndef IG3RDMA_HW_H 4d5edd333SMustafa Ismail #define IG3RDMA_HW_H 5d5edd333SMustafa Ismail 6*7d5a7cc7SChristopher Bednarz #define IG3_MAX_APFS 1 7*7d5a7cc7SChristopher Bednarz #define IG3_MAX_AVFS 0 8*7d5a7cc7SChristopher Bednarz 9d5edd333SMustafa Ismail #define IG3_PF_RDMA_REGION_OFFSET 0xBC00000 10d5edd333SMustafa Ismail #define IG3_PF_RDMA_REGION_LEN 0x401000 11d5edd333SMustafa Ismail #define IG3_VF_RDMA_REGION_OFFSET 0x8C00 12d5edd333SMustafa Ismail #define IG3_VF_RDMA_REGION_LEN 0x8400 13d5edd333SMustafa Ismail 14*7d5a7cc7SChristopher Bednarz enum ig3rdma_device_caps_const { 15*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_WQ_FRAGMENT_COUNT = 14, 16*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_SGE_RD = 14, 17*7d5a7cc7SChristopher Bednarz 18*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_STATS_COUNT = 128, 19*7d5a7cc7SChristopher Bednarz 20*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_IRD_SIZE = 64, 21*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_ORD_SIZE = 64, 22*7d5a7cc7SChristopher Bednarz IG3RDMA_MIN_WQ_SIZE = 16 /* WQEs */, 23*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_INLINE_DATA_SIZE = 216, 24*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_PF_PUSH_PAGE_COUNT = 8192, 25*7d5a7cc7SChristopher Bednarz IG3RDMA_MAX_VF_PUSH_PAGE_COUNT = 16, 26*7d5a7cc7SChristopher Bednarz }; 27*7d5a7cc7SChristopher Bednarz 28*7d5a7cc7SChristopher Bednarz void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset); 29d5edd333SMustafa Ismail int ig3rdma_vchnl_send_sync(struct irdma_sc_dev *dev, u8 *msg, u16 len, 30d5edd333SMustafa Ismail u8 *recv_msg, u16 *recv_len); 31d5edd333SMustafa Ismail 32d5edd333SMustafa Ismail #endif /* IG3RDMA_HW_H*/ 33