1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 2 /* Copyright (c) 2021 - 2024 Intel Corporation */ 3 #ifndef IG3RDMA_HW_H 4 #define IG3RDMA_HW_H 5 6 #define IG3_MAX_APFS 1 7 #define IG3_MAX_AVFS 0 8 9 #define IG3_PF_RDMA_REGION_OFFSET 0xBC00000 10 #define IG3_PF_RDMA_REGION_LEN 0x401000 11 #define IG3_VF_RDMA_REGION_OFFSET 0x8C00 12 #define IG3_VF_RDMA_REGION_LEN 0x8400 13 14 enum ig3rdma_device_caps_const { 15 IG3RDMA_MAX_WQ_FRAGMENT_COUNT = 14, 16 IG3RDMA_MAX_SGE_RD = 14, 17 18 IG3RDMA_MAX_STATS_COUNT = 128, 19 20 IG3RDMA_MAX_IRD_SIZE = 64, 21 IG3RDMA_MAX_ORD_SIZE = 64, 22 IG3RDMA_MIN_WQ_SIZE = 16 /* WQEs */, 23 IG3RDMA_MAX_INLINE_DATA_SIZE = 216, 24 IG3RDMA_MAX_PF_PUSH_PAGE_COUNT = 8192, 25 IG3RDMA_MAX_VF_PUSH_PAGE_COUNT = 16, 26 }; 27 28 void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset); 29 int ig3rdma_vchnl_send_sync(struct irdma_sc_dev *dev, u8 *msg, u16 len, 30 u8 *recv_msg, u16 *recv_len); 31 32 #endif /* IG3RDMA_HW_H*/ 33