1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2018 - 2024 Intel Corporation */ 3 #include "osdep.h" 4 #include "type.h" 5 #include "protos.h" 6 #include "ig3rdma_hw.h" 7 8 /** 9 * ig3rdma_ena_irq - Enable interrupt 10 * @dev: pointer to the device structure 11 * @idx: vector index 12 */ 13 static void ig3rdma_ena_irq(struct irdma_sc_dev *dev, u32 idx) 14 { 15 u32 val; 16 u32 int_stride = 1; /* one u32 per register */ 17 18 if (dev->is_pf) 19 int_stride = 0x400; 20 else 21 idx--; /* VFs use DYN_CTL_N */ 22 23 val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 1) | 24 FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 1); 25 26 writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride)); 27 } 28 29 /** 30 * ig3rdma_disable_irq - Disable interrupt 31 * @dev: pointer to the device structure 32 * @idx: vector index 33 */ 34 static void ig3rdma_disable_irq(struct irdma_sc_dev *dev, u32 idx) 35 { 36 u32 int_stride = 1; /* one u32 per register */ 37 38 if (dev->is_pf) 39 int_stride = 0x400; 40 else 41 idx--; /* VFs use DYN_CTL_N */ 42 43 writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride)); 44 } 45 46 static const struct irdma_irq_ops ig3rdma_irq_ops = { 47 .irdma_dis_irq = ig3rdma_disable_irq, 48 .irdma_en_irq = ig3rdma_ena_irq, 49 }; 50 51 static const struct irdma_hw_stat_map ig3rdma_hw_stat_map[] = { 52 [IRDMA_HW_STAT_INDEX_RXVLANERR] = { 0, 0, 0 }, 53 [IRDMA_HW_STAT_INDEX_IP4RXOCTS] = { 8, 0, 0 }, 54 [IRDMA_HW_STAT_INDEX_IP4RXPKTS] = { 16, 0, 0 }, 55 [IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = { 24, 0, 0 }, 56 [IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = { 32, 0, 0 }, 57 [IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = { 40, 0, 0 }, 58 [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = { 48, 0, 0 }, 59 [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = { 56, 0, 0 }, 60 [IRDMA_HW_STAT_INDEX_IP6RXOCTS] = { 64, 0, 0 }, 61 [IRDMA_HW_STAT_INDEX_IP6RXPKTS] = { 72, 0, 0 }, 62 [IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = { 80, 0, 0 }, 63 [IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = { 88, 0, 0 }, 64 [IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = { 96, 0, 0 }, 65 [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = { 104, 0, 0 }, 66 [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = { 112, 0, 0 }, 67 [IRDMA_HW_STAT_INDEX_IP4TXOCTS] = { 120, 0, 0 }, 68 [IRDMA_HW_STAT_INDEX_IP4TXPKTS] = { 128, 0, 0 }, 69 [IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = { 136, 0, 0 }, 70 [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = { 144, 0, 0 }, 71 [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = { 152, 0, 0 }, 72 [IRDMA_HW_STAT_INDEX_IP6TXOCTS] = { 160, 0, 0 }, 73 [IRDMA_HW_STAT_INDEX_IP6TXPKTS] = { 168, 0, 0 }, 74 [IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = { 176, 0, 0 }, 75 [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = { 184, 0, 0 }, 76 [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = { 192, 0, 0 }, 77 [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = { 200, 0, 0 }, 78 [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = { 208, 0, 0 }, 79 [IRDMA_HW_STAT_INDEX_TCPRTXSEG] = { 216, 0, 0 }, 80 [IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = { 224, 0, 0 }, 81 [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = { 232, 0, 0 }, 82 [IRDMA_HW_STAT_INDEX_TCPTXSEG] = { 240, 0, 0 }, 83 [IRDMA_HW_STAT_INDEX_TCPRXSEGS] = { 248, 0, 0 }, 84 [IRDMA_HW_STAT_INDEX_UDPRXPKTS] = { 256, 0, 0 }, 85 [IRDMA_HW_STAT_INDEX_UDPTXPKTS] = { 264, 0, 0 }, 86 [IRDMA_HW_STAT_INDEX_RDMARXWRS] = { 272, 0, 0 }, 87 [IRDMA_HW_STAT_INDEX_RDMARXRDS] = { 280, 0, 0 }, 88 [IRDMA_HW_STAT_INDEX_RDMARXSNDS] = { 288, 0, 0 }, 89 [IRDMA_HW_STAT_INDEX_RDMATXWRS] = { 296, 0, 0 }, 90 [IRDMA_HW_STAT_INDEX_RDMATXRDS] = { 304, 0, 0 }, 91 [IRDMA_HW_STAT_INDEX_RDMATXSNDS] = { 312, 0, 0 }, 92 [IRDMA_HW_STAT_INDEX_RDMAVBND] = { 320, 0, 0 }, 93 [IRDMA_HW_STAT_INDEX_RDMAVINV] = { 328, 0, 0 }, 94 [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] = { 336, 0, 0 }, 95 [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] = { 344, 0, 0 }, 96 [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] = { 352, 0, 0 }, 97 [IRDMA_HW_STAT_INDEX_TXNPCNPSENT] = { 360, 0, 0 }, 98 [IRDMA_HW_STAT_INDEX_RNR_SENT] = { 368, 0, 0 }, 99 [IRDMA_HW_STAT_INDEX_RNR_RCVD] = { 376, 0, 0 }, 100 [IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT] = { 384, 0, 0 }, 101 [IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT] = { 392, 0, 0 }, 102 [IRDMA_HW_STAT_INDEX_RDMARXATS] = { 408, 0, 0 }, 103 [IRDMA_HW_STAT_INDEX_RDMATXATS] = { 416, 0, 0 }, 104 [IRDMA_HW_STAT_INDEX_NAKSEQERR] = { 424, 0, 0 }, 105 [IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED] = { 432, 0, 0 }, 106 [IRDMA_HW_STAT_INDEX_RTO] = { 440, 0, 0 }, 107 [IRDMA_HW_STAT_INDEX_RXOOOPKTS] = { 448, 0, 0 }, 108 [IRDMA_HW_STAT_INDEX_ICRCERR] = { 456, 0, 0 }, 109 }; 110 111 void ig3rdma_init_hw(struct irdma_sc_dev *dev) 112 { 113 dev->irq_ops = &ig3rdma_irq_ops; 114 dev->hw_stats_map = ig3rdma_hw_stat_map; 115 116 dev->hw_attrs.uk_attrs.hw_rev = IRDMA_GEN_3; 117 dev->hw_attrs.uk_attrs.max_hw_wq_frags = IG3RDMA_MAX_WQ_FRAGMENT_COUNT; 118 dev->hw_attrs.uk_attrs.max_hw_read_sges = IG3RDMA_MAX_SGE_RD; 119 dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR; 120 dev->hw_attrs.first_hw_vf_fpm_id = 0; 121 dev->hw_attrs.max_hw_vf_fpm_id = IG3_MAX_APFS + IG3_MAX_AVFS; 122 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_64_BYTE_CQE; 123 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_CQE_TIMESTAMPING; 124 125 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_SRQ; 126 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE | 127 IRDMA_FEATURE_CQ_RESIZE; 128 dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G; 129 dev->hw_attrs.max_hw_ird = IG3RDMA_MAX_IRD_SIZE; 130 dev->hw_attrs.max_hw_ord = IG3RDMA_MAX_ORD_SIZE; 131 dev->hw_attrs.max_stat_inst = IG3RDMA_MAX_STATS_COUNT; 132 dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_3; 133 dev->hw_attrs.uk_attrs.min_hw_wq_size = IG3RDMA_MIN_WQ_SIZE; 134 dev->hw_attrs.uk_attrs.max_hw_srq_quanta = IRDMA_SRQ_MAX_QUANTA; 135 dev->hw_attrs.uk_attrs.max_hw_inline = IG3RDMA_MAX_INLINE_DATA_SIZE; 136 dev->hw_attrs.max_hw_device_pages = 137 dev->is_pf ? IG3RDMA_MAX_PF_PUSH_PAGE_COUNT : IG3RDMA_MAX_VF_PUSH_PAGE_COUNT; 138 } 139 140 static void __iomem *__ig3rdma_get_reg_addr(struct irdma_mmio_region *region, u64 reg_offset) 141 { 142 if (reg_offset >= region->offset && 143 reg_offset < (region->offset + region->len)) { 144 reg_offset -= region->offset; 145 146 return region->addr + reg_offset; 147 } 148 149 return NULL; 150 } 151 152 void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset) 153 { 154 u8 __iomem *reg_addr; 155 int i; 156 157 reg_addr = __ig3rdma_get_reg_addr(&hw->rdma_reg, reg_offset); 158 if (reg_addr) 159 return reg_addr; 160 161 for (i = 0; i < hw->num_io_regions; i++) { 162 reg_addr = __ig3rdma_get_reg_addr(&hw->io_regs[i], reg_offset); 163 if (reg_addr) 164 return reg_addr; 165 } 166 167 WARN_ON_ONCE(1); 168 169 return NULL; 170 } 171