1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2026 Broadcom */ 3 4 /* DO NOT MODIFY!!! This file is automatically generated. */ 5 6 #ifndef _BNG_RE_HSI_H_ 7 #define _BNG_RE_HSI_H_ 8 9 #include <linux/bnge/hsi.h> 10 11 /* tx_doorbell (size:32b/4B) */ 12 struct tx_doorbell { 13 __le32 key_idx; 14 #define TX_DOORBELL_IDX_MASK 0xffffffUL 15 #define TX_DOORBELL_IDX_SFT 0 16 #define TX_DOORBELL_KEY_MASK 0xf0000000UL 17 #define TX_DOORBELL_KEY_SFT 28 18 #define TX_DOORBELL_KEY_TX (0x0UL << 28) 19 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX 20 }; 21 22 /* rx_doorbell (size:32b/4B) */ 23 struct rx_doorbell { 24 __le32 key_idx; 25 #define RX_DOORBELL_IDX_MASK 0xffffffUL 26 #define RX_DOORBELL_IDX_SFT 0 27 #define RX_DOORBELL_KEY_MASK 0xf0000000UL 28 #define RX_DOORBELL_KEY_SFT 28 29 #define RX_DOORBELL_KEY_RX (0x1UL << 28) 30 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX 31 }; 32 33 /* cmpl_doorbell (size:32b/4B) */ 34 struct cmpl_doorbell { 35 __le32 key_mask_valid_idx; 36 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 37 #define CMPL_DOORBELL_IDX_SFT 0 38 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 39 #define CMPL_DOORBELL_MASK 0x8000000UL 40 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 41 #define CMPL_DOORBELL_KEY_SFT 28 42 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 43 #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL 44 }; 45 46 /* status_doorbell (size:32b/4B) */ 47 struct status_doorbell { 48 __le32 key_idx; 49 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 50 #define STATUS_DOORBELL_IDX_SFT 0 51 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 52 #define STATUS_DOORBELL_KEY_SFT 28 53 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 54 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT 55 }; 56 57 /* cmdq_init (size:128b/16B) */ 58 struct cmdq_init { 59 __le64 cmdq_pbl; 60 __le16 cmdq_size_cmdq_lvl; 61 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 62 #define CMDQ_INIT_CMDQ_LVL_SFT 0 63 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 64 #define CMDQ_INIT_CMDQ_SIZE_SFT 2 65 __le16 creq_ring_id; 66 __le32 prod_idx; 67 }; 68 69 /* cmdq_base (size:128b/16B) */ 70 struct cmdq_base { 71 u8 opcode; 72 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 73 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 74 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 75 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 76 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 77 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 78 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 79 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 80 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 81 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 82 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 83 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 84 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 85 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 86 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 87 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 88 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 89 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 90 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 91 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 92 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 93 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 94 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 95 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 96 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 97 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 98 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 99 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 100 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 101 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 102 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 103 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED 0x89UL 104 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 105 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 106 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL 107 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL 108 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 109 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 110 #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL 111 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL 112 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 113 #define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION 0x93UL 114 #define CMDQ_BASE_OPCODE_CREATE_QP_BATCH 0x94UL 115 #define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH 0x95UL 116 #define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX 0x96UL 117 #define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX 0x97UL 118 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 0x98UL 119 #define CMDQ_BASE_OPCODE_PNO_STATS_CONFIG 0x99UL 120 #define CMDQ_BASE_OPCODE_PNO_DEBUG_TUNNEL_CONFIG 0x9aUL 121 #define CMDQ_BASE_OPCODE_SET_PNO_FABRIC_NEXTHOP_MAC 0x9bUL 122 #define CMDQ_BASE_OPCODE_PNO_PATH_STRPATH_CONFIG 0x9cUL 123 #define CMDQ_BASE_OPCODE_PNO_PATH_QUERY 0x9dUL 124 #define CMDQ_BASE_OPCODE_PNO_PATH_ACCESS_CONTROL 0x9eUL 125 #define CMDQ_BASE_OPCODE_QUERY_PNO_FABRIC_NEXTHOP_IP 0x9fUL 126 #define CMDQ_BASE_OPCODE_PNO_PATH_PLANE_CONFIG 0xa0UL 127 #define CMDQ_BASE_OPCODE_PNO_TUNNEL_CLOSE 0xa1UL 128 #define CMDQ_BASE_OPCODE_PNO_HOST_PROCESSING_DONE 0xa2UL 129 #define CMDQ_BASE_OPCODE_PNO_STATS_QPARAM 0xa3UL 130 #define CMDQ_BASE_OPCODE_PATH_PROBE_CFG 0xa4UL 131 #define CMDQ_BASE_OPCODE_PATH_PROBE_DISABLE 0xa5UL 132 #define CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG 0xa6UL 133 #define CMDQ_BASE_OPCODE_ROCE_CFG 0xa7UL 134 #define CMDQ_BASE_OPCODE_PNO_EV_MONITORING_CONFIG 0xa8UL 135 #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_PNO_EV_MONITORING_CONFIG 136 u8 cmd_size; 137 __le16 flags; 138 __le16 cookie; 139 u8 resp_size; 140 u8 reserved8; 141 __le64 resp_addr; 142 }; 143 144 /* creq_base (size:128b/16B) */ 145 struct creq_base { 146 u8 type; 147 #define CREQ_BASE_TYPE_MASK 0x3fUL 148 #define CREQ_BASE_TYPE_SFT 0 149 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 150 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 151 #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT 152 u8 reserved56[7]; 153 u8 v; 154 #define CREQ_BASE_V 0x1UL 155 u8 event; 156 u8 reserved48[6]; 157 }; 158 159 /* roce_stats_ext_ctx (size:1920b/240B) */ 160 struct roce_stats_ext_ctx { 161 __le64 tx_atomic_req_pkts; 162 __le64 tx_read_req_pkts; 163 __le64 tx_read_res_pkts; 164 __le64 tx_write_req_pkts; 165 __le64 tx_rc_send_req_pkts; 166 __le64 tx_ud_send_req_pkts; 167 __le64 tx_cnp_pkts; 168 __le64 tx_roce_pkts; 169 __le64 tx_roce_bytes; 170 __le64 rx_out_of_buffer_pkts; 171 __le64 rx_out_of_sequence_pkts; 172 __le64 dup_req; 173 __le64 missing_resp; 174 __le64 seq_err_naks_rcvd; 175 __le64 rnr_naks_rcvd; 176 __le64 to_retransmits; 177 __le64 rx_atomic_req_pkts; 178 __le64 rx_read_req_pkts; 179 __le64 rx_read_res_pkts; 180 __le64 rx_write_req_pkts; 181 __le64 rx_rc_send_pkts; 182 __le64 rx_ud_send_pkts; 183 __le64 rx_dcn_payload_cut; 184 __le64 rx_ecn_marked_pkts; 185 __le64 rx_cnp_pkts; 186 __le64 rx_roce_pkts; 187 __le64 rx_roce_bytes; 188 __le64 rx_roce_good_pkts; 189 __le64 rx_roce_good_bytes; 190 __le64 rx_ack_pkts; 191 }; 192 193 /* cmdq_query_version (size:128b/16B) */ 194 struct cmdq_query_version { 195 u8 opcode; 196 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 197 #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 198 u8 cmd_size; 199 __le16 flags; 200 __le16 cookie; 201 u8 resp_size; 202 u8 reserved8; 203 __le64 resp_addr; 204 }; 205 206 /* creq_query_version_resp (size:128b/16B) */ 207 struct creq_query_version_resp { 208 u8 type; 209 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 210 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 211 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 212 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 213 u8 status; 214 __le16 cookie; 215 u8 fw_maj; 216 u8 fw_minor; 217 u8 fw_bld; 218 u8 fw_rsvd; 219 u8 v; 220 #define CREQ_QUERY_VERSION_RESP_V 0x1UL 221 u8 event; 222 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 223 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 224 __le16 reserved16; 225 u8 intf_maj; 226 u8 intf_minor; 227 u8 intf_bld; 228 u8 intf_rsvd; 229 }; 230 231 /* cmdq_initialize_fw (size:1024b/128B) */ 232 struct cmdq_initialize_fw { 233 u8 opcode; 234 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 235 #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 236 u8 cmd_size; 237 __le16 flags; 238 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 239 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL 240 #define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION 0x4UL 241 #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED 0x8UL 242 #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT 0x10UL 243 #define CMDQ_INITIALIZE_FW_FLAGS_DESTROY_CONTEXT_SB_SUPPORTED 0x20UL 244 #define CMDQ_INITIALIZE_FW_FLAGS_DESTROY_UDCC_SESSION_DATA_SB_SUPPORTED 0x40UL 245 #define CMDQ_INITIALIZE_FW_FLAGS_MIRROR_ON_ROCE_SUPPORTED 0x80UL 246 __le16 cookie; 247 u8 resp_size; 248 u8 reserved8; 249 __le64 resp_addr; 250 u8 qpc_pg_size_qpc_lvl; 251 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 252 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 253 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 254 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 255 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 256 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 257 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 258 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 259 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 260 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 261 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 262 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 263 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 264 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 265 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G 266 u8 mrw_pg_size_mrw_lvl; 267 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 268 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 269 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 270 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 271 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 272 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 273 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 274 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 275 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 276 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 277 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 278 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 279 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 280 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 281 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G 282 u8 srq_pg_size_srq_lvl; 283 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 284 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 285 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 286 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 287 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 288 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 289 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 290 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 291 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 292 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 293 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 294 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 295 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 296 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 297 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G 298 u8 cq_pg_size_cq_lvl; 299 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 300 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 301 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 302 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 303 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 304 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 305 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 306 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 307 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 308 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 309 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 310 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 311 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 312 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 313 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G 314 u8 tqm_pg_size_tqm_lvl; 315 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 316 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 317 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 318 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 319 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 320 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 321 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 322 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 323 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 324 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 325 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 326 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 327 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 328 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 329 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G 330 u8 tim_pg_size_tim_lvl; 331 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 332 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 333 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 334 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 335 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 336 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 337 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 338 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 339 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 340 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 341 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 342 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 343 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 344 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 345 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G 346 __le16 log2_dbr_pg_size; 347 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 348 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 349 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 350 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 351 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 352 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 353 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 354 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 355 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 356 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 357 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 358 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 359 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 360 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 361 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 362 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 363 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 364 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 365 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 366 #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL 367 #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 368 __le64 qpc_page_dir; 369 __le64 mrw_page_dir; 370 __le64 srq_page_dir; 371 __le64 cq_page_dir; 372 __le64 tqm_page_dir; 373 __le64 tim_page_dir; 374 __le32 number_of_qp; 375 __le32 number_of_mrw; 376 __le32 number_of_srq; 377 __le32 number_of_cq; 378 __le32 max_qp_per_vf; 379 __le32 max_mrw_per_vf; 380 __le32 max_srq_per_vf; 381 __le32 max_cq_per_vf; 382 __le32 max_gid_per_vf; 383 __le32 stat_ctx_id; 384 u8 drv_hsi_ver_maj; 385 u8 drv_hsi_ver_min; 386 u8 drv_hsi_ver_upd; 387 u8 unused40[5]; 388 __le16 drv_build_ver_maj; 389 __le16 drv_build_ver_min; 390 __le16 drv_build_ver_upd; 391 __le16 drv_build_ver_patch; 392 }; 393 394 /* creq_initialize_fw_resp (size:128b/16B) */ 395 struct creq_initialize_fw_resp { 396 u8 type; 397 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 398 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 399 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 400 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 401 u8 status; 402 __le16 cookie; 403 __le32 reserved32; 404 u8 v; 405 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 406 u8 event; 407 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 408 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 409 u8 udcc_session_size; 410 u8 reserved40[5]; 411 }; 412 413 /* cmdq_deinitialize_fw (size:128b/16B) */ 414 struct cmdq_deinitialize_fw { 415 u8 opcode; 416 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 417 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 418 u8 cmd_size; 419 __le16 flags; 420 __le16 cookie; 421 u8 resp_size; 422 u8 reserved8; 423 __le64 resp_addr; 424 }; 425 426 /* creq_deinitialize_fw_resp (size:128b/16B) */ 427 struct creq_deinitialize_fw_resp { 428 u8 type; 429 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 430 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 431 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 432 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 433 u8 status; 434 __le16 cookie; 435 __le32 reserved32; 436 u8 v; 437 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 438 u8 event; 439 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 440 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 441 u8 reserved48[6]; 442 }; 443 444 /* cmdq_create_qp (size:1152b/144B) */ 445 struct cmdq_create_qp { 446 u8 opcode; 447 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 448 #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP 449 u8 cmd_size; 450 __le16 flags; 451 __le16 cookie; 452 u8 resp_size; 453 u8 reserved8; 454 __le64 resp_addr; 455 __le64 qp_handle; 456 __le32 qp_flags; 457 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 458 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 459 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 460 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 461 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL 462 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL 463 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL 464 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL 465 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED 0x100UL 466 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID 0x200UL 467 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 0x400UL 468 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID 0x800UL 469 #define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID 0x1000UL 470 #define CMDQ_CREATE_QP_QP_FLAGS_EROCE_VALID 0x2000UL 471 #define CMDQ_CREATE_QP_QP_FLAGS_RQ_PBL_PG_SIZE_VALID 0x4000UL 472 #define CMDQ_CREATE_QP_QP_FLAGS_SQ_PBL_PG_SIZE_VALID 0x8000UL 473 #define CMDQ_CREATE_QP_QP_FLAGS_LAST CMDQ_CREATE_QP_QP_FLAGS_SQ_PBL_PG_SIZE_VALID 474 u8 type; 475 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 476 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 477 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 478 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 479 #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI 480 u8 sq_pg_size_sq_lvl; 481 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 482 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 483 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 484 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 485 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 486 #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 487 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 488 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 489 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 490 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 491 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 492 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 493 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 494 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 495 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G 496 u8 rq_pg_size_rq_lvl; 497 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 498 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 499 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 500 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 501 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 502 #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 503 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 504 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 505 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 506 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 507 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 508 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 509 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 510 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 511 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G 512 u8 unused_0; 513 __le32 dpi; 514 __le32 sq_size; 515 __le32 rq_size; 516 __le16 sq_fwo_sq_sge; 517 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 518 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 519 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 520 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 521 __le16 rq_fwo_rq_sge; 522 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 523 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 524 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 525 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 526 __le32 scq_cid; 527 __le32 rcq_cid; 528 __le32 srq_cid; 529 __le32 pd_id; 530 __le64 sq_pbl; 531 __le64 rq_pbl; 532 __le64 irrq_addr; 533 __le64 orrq_addr; 534 __le32 request_xid; 535 __le16 steering_tag; 536 __le16 sq_max_num_wqes; 537 __le32 ext_stats_ctx_id; 538 __le16 schq_id; 539 u8 sq_pbl_pg_size; 540 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_MASK 0xfUL 541 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_SFT 0 542 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_4K 0x0UL 543 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_8K 0x1UL 544 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_64K 0x2UL 545 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_2M 0x3UL 546 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_8M 0x4UL 547 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_1G 0x5UL 548 #define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_1G 549 u8 rq_pbl_pg_size; 550 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_MASK 0xfUL 551 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_SFT 0 552 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_4K 0x0UL 553 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_8K 0x1UL 554 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_64K 0x2UL 555 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_2M 0x3UL 556 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_8M 0x4UL 557 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_1G 0x5UL 558 #define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_1G 559 __le32 msn_iqp; 560 __le32 irrq_iqp; 561 __le32 orrq_iqp; 562 __le32 msn_size; 563 __le32 irrq_size; 564 __le32 orrq_size; 565 __le16 eroce; 566 #define CMDQ_CREATE_QP_EROCE_COS 0x1UL 567 #define CMDQ_CREATE_QP_EROCE_RESERVED_0_MASK 0xeUL 568 #define CMDQ_CREATE_QP_EROCE_RESERVED_0_SFT 1 569 #define CMDQ_CREATE_QP_EROCE_GRP_MASK 0xf0UL 570 #define CMDQ_CREATE_QP_EROCE_GRP_SFT 4 571 #define CMDQ_CREATE_QP_EROCE_CSIG_ENABLED 0x100UL 572 u8 reserved48[6]; 573 }; 574 575 /* creq_create_qp_resp (size:128b/16B) */ 576 struct creq_create_qp_resp { 577 u8 type; 578 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 579 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 580 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 581 #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 582 u8 status; 583 __le16 cookie; 584 __le32 xid; 585 u8 v; 586 #define CREQ_CREATE_QP_RESP_V 0x1UL 587 u8 event; 588 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 589 #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 590 u8 optimized_transmit_enabled; 591 u8 context_size; 592 u8 reserved32[4]; 593 }; 594 595 /* cmdq_destroy_qp (size:192b/24B) */ 596 struct cmdq_destroy_qp { 597 u8 opcode; 598 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 599 #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 600 u8 cmd_size; 601 __le16 flags; 602 __le16 cookie; 603 u8 resp_size; 604 u8 reserved8; 605 __le64 resp_addr; 606 __le32 qp_cid; 607 __le32 unused_0; 608 }; 609 610 /* creq_destroy_qp_resp (size:128b/16B) */ 611 struct creq_destroy_qp_resp { 612 u8 type; 613 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 614 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 615 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 616 #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 617 u8 status; 618 __le16 cookie; 619 __le32 xid; 620 u8 v; 621 #define CREQ_DESTROY_QP_RESP_V 0x1UL 622 u8 event; 623 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 624 #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 625 __le16 udcc_session_id; 626 __le16 udcc_session_data_offset; 627 u8 flags; 628 #define CREQ_DESTROY_QP_RESP_FLAGS_UDCC_SESSION_DATA 0x1UL 629 #define CREQ_DESTROY_QP_RESP_FLAGS_UDCC_RTT_DATA 0x2UL 630 u8 udcc_session_data_size; 631 }; 632 633 /* cmdq_modify_qp (size:1152b/144B) */ 634 struct cmdq_modify_qp { 635 u8 opcode; 636 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 637 #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 638 u8 cmd_size; 639 __le16 flags; 640 #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED 0x1UL 641 #define CMDQ_MODIFY_QP_FLAGS_EXCLUDE_QP_UDCC 0x2UL 642 __le16 cookie; 643 u8 resp_size; 644 u8 qp_type; 645 #define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL 646 #define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL 647 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL 648 #define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL 649 #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI 650 __le64 resp_addr; 651 __le32 modify_mask; 652 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 653 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 654 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 655 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 656 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 657 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 658 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 659 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 660 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 661 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 662 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 663 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL 664 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 665 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 666 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 667 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 668 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 669 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 670 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 671 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 672 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 673 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 674 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 675 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 676 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 677 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 678 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 679 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 680 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 681 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 682 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 683 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 684 __le32 qp_cid; 685 u8 network_type_en_sqd_async_notify_new_state; 686 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 687 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 688 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 689 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 690 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 691 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 692 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 693 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 694 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 695 #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR 696 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 697 #define CMDQ_MODIFY_QP_UNUSED1 0x20UL 698 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 699 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 700 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 701 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 702 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 703 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 704 u8 access; 705 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL 706 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 707 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 708 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 709 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 710 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 711 __le16 pkey; 712 __le32 qkey; 713 __le32 dgid[4]; 714 __le32 flow_label; 715 __le16 sgid_index; 716 u8 hop_limit; 717 u8 traffic_class; 718 __le16 dest_mac[3]; 719 u8 tos_dscp_tos_ecn; 720 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 721 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 722 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 723 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 724 u8 path_mtu_pingpong_push_enable; 725 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL 726 #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL 727 #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 728 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 729 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 730 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 731 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 732 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 733 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 734 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 735 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 736 #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 737 u8 timeout; 738 u8 retry_cnt; 739 u8 rnr_retry; 740 u8 min_rnr_timer; 741 __le32 rq_psn; 742 __le32 sq_psn; 743 u8 max_rd_atomic; 744 u8 max_dest_rd_atomic; 745 __le16 enable_cc; 746 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 747 #define CMDQ_MODIFY_QP_ENH_MODE_MASK 0x6UL 748 #define CMDQ_MODIFY_QP_ENH_MODE_SFT 1 749 #define CMDQ_MODIFY_QP_ENH_COS 0x8UL 750 #define CMDQ_MODIFY_QP_ENH_GRP_MASK 0xf0UL 751 #define CMDQ_MODIFY_QP_ENH_GRP_SFT 4 752 #define CMDQ_MODIFY_QP_UNUSED8_MASK 0xff00UL 753 #define CMDQ_MODIFY_QP_UNUSED8_SFT 8 754 __le32 sq_size; 755 __le32 rq_size; 756 __le16 sq_sge; 757 __le16 rq_sge; 758 __le32 max_inline_data; 759 __le32 dest_qp_id; 760 __le32 pingpong_push_dpi; 761 __le16 src_mac[3]; 762 __le16 vlan_pcp_vlan_dei_vlan_id; 763 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 764 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 765 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 766 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 767 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 768 __le64 irrq_addr; 769 __le64 orrq_addr; 770 __le32 ext_modify_mask; 771 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL 772 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL 773 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_UDP_SRC_PORT_VALID 0x4UL 774 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID 0x8UL 775 __le32 ext_stats_ctx_id; 776 __le16 schq_id; 777 __le16 udp_src_port; 778 __le32 rate_limit; 779 }; 780 781 /* creq_modify_qp_resp (size:128b/16B) */ 782 struct creq_modify_qp_resp { 783 u8 type; 784 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 785 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 786 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 787 #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 788 u8 status; 789 __le16 cookie; 790 __le32 xid; 791 u8 v; 792 #define CREQ_MODIFY_QP_RESP_V 0x1UL 793 u8 event; 794 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 795 #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 796 u8 pingpong_push_state_index_enabled; 797 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL 798 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL 799 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 800 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL 801 u8 shaper_allocation_status; 802 #define CREQ_MODIFY_QP_RESP_SHAPER_ALLOCATED 0x1UL 803 __le16 flags; 804 #define CREQ_MODIFY_QP_RESP_SESSION_ELIGIBLE 0x1UL 805 __le16 reserved16; 806 }; 807 808 /* cmdq_query_qp (size:192b/24B) */ 809 struct cmdq_query_qp { 810 u8 opcode; 811 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 812 #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP 813 u8 cmd_size; 814 __le16 flags; 815 __le16 cookie; 816 u8 resp_size; 817 u8 reserved8; 818 __le64 resp_addr; 819 __le32 qp_cid; 820 __le32 unused_0; 821 }; 822 823 /* creq_query_qp_resp (size:128b/16B) */ 824 struct creq_query_qp_resp { 825 u8 type; 826 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 827 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 828 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 829 #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 830 u8 status; 831 __le16 cookie; 832 __le32 size; 833 u8 v; 834 #define CREQ_QUERY_QP_RESP_V 0x1UL 835 u8 event; 836 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 837 #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 838 u8 reserved48[6]; 839 }; 840 841 /* creq_query_qp_resp_sb (size:896b/112B) */ 842 struct creq_query_qp_resp_sb { 843 u8 opcode; 844 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 845 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 846 u8 status; 847 __le16 cookie; 848 __le16 flags; 849 u8 resp_size; 850 u8 reserved8; 851 __le32 xid; 852 u8 en_sqd_async_notify_state; 853 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 854 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 855 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 856 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 857 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 858 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 859 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 860 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 861 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 862 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR 863 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 864 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL 865 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 866 u8 access; 867 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL 868 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 869 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 870 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 871 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 872 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 873 __le16 pkey; 874 __le32 qkey; 875 __le16 udp_src_port; 876 __le16 reserved16; 877 __le32 dgid[4]; 878 __le32 flow_label; 879 __le16 sgid_index; 880 u8 hop_limit; 881 u8 traffic_class; 882 __le16 dest_mac[3]; 883 __le16 path_mtu_dest_vlan_id; 884 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 885 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 886 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 887 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 888 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 889 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 890 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 891 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 892 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 893 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 894 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 895 u8 timeout; 896 u8 retry_cnt; 897 u8 rnr_retry; 898 u8 min_rnr_timer; 899 __le32 rq_psn; 900 __le32 sq_psn; 901 u8 max_rd_atomic; 902 u8 max_dest_rd_atomic; 903 u8 tos_dscp_tos_ecn; 904 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 905 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 906 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 907 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 908 u8 enable_cc; 909 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 910 __le32 sq_size; 911 __le32 rq_size; 912 __le16 sq_sge; 913 __le16 rq_sge; 914 __le32 max_inline_data; 915 __le32 dest_qp_id; 916 __le16 port_id; 917 u8 unused_0; 918 u8 stat_collection_id; 919 __le16 src_mac[3]; 920 __le16 vlan_pcp_vlan_dei_vlan_id; 921 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 922 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 923 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 924 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 925 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 926 __le32 rate_limit; 927 __le32 reserved32; 928 }; 929 930 /* cmdq_query_qp_extend (size:192b/24B) */ 931 struct cmdq_query_qp_extend { 932 u8 opcode; 933 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL 934 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 935 u8 cmd_size; 936 __le16 flags; 937 __le16 cookie; 938 u8 resp_size; 939 u8 num_qps; 940 __le64 resp_addr; 941 __le32 function_id; 942 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL 943 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 944 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL 945 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 946 #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL 947 __le32 current_index; 948 }; 949 950 /* creq_query_qp_extend_resp (size:128b/16B) */ 951 struct creq_query_qp_extend_resp { 952 u8 type; 953 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL 954 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 955 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL 956 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 957 u8 status; 958 __le16 cookie; 959 __le32 size; 960 u8 v; 961 #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL 962 u8 event; 963 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL 964 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 965 __le16 reserved16; 966 __le32 current_index; 967 }; 968 969 /* creq_query_qp_extend_resp_sb (size:384b/48B) */ 970 struct creq_query_qp_extend_resp_sb { 971 u8 opcode; 972 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL 973 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 974 u8 status; 975 __le16 cookie; 976 __le16 flags; 977 u8 resp_size; 978 u8 reserved8; 979 __le32 xid; 980 u8 state; 981 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL 982 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 983 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL 984 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL 985 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL 986 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL 987 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL 988 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL 989 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL 990 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 991 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL 992 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 993 u8 reserved_8; 994 __le16 port_id; 995 __le32 qkey; 996 __le16 sgid_index; 997 u8 network_type; 998 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL 999 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 1000 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 1001 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 1002 u8 unused_0; 1003 __le32 dgid[4]; 1004 __le32 dest_qp_id; 1005 u8 stat_collection_id; 1006 u8 reserved2_8; 1007 __le16 reserved_16; 1008 }; 1009 1010 /* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ 1011 struct creq_query_qp_extend_resp_sb_tlv { 1012 __le16 cmd_discr; 1013 u8 reserved_8b; 1014 u8 tlv_flags; 1015 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 1016 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 1017 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 1018 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 1019 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 1020 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 1021 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 1022 __le16 tlv_type; 1023 __le16 length; 1024 u8 total_size; 1025 u8 reserved56[7]; 1026 u8 opcode; 1027 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL 1028 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 1029 u8 status; 1030 __le16 cookie; 1031 __le16 flags; 1032 u8 resp_size; 1033 u8 reserved8; 1034 __le32 xid; 1035 u8 state; 1036 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL 1037 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 1038 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL 1039 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL 1040 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL 1041 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL 1042 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL 1043 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL 1044 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL 1045 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 1046 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL 1047 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 1048 u8 reserved_8; 1049 __le16 port_id; 1050 __le32 qkey; 1051 __le16 sgid_index; 1052 u8 network_type; 1053 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL 1054 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 1055 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 1056 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 1057 u8 unused_0; 1058 __le32 dgid[4]; 1059 __le32 dest_qp_id; 1060 u8 stat_collection_id; 1061 u8 reserved2_8; 1062 __le16 reserved_16; 1063 }; 1064 1065 /* cmdq_create_srq (size:512b/64B) */ 1066 struct cmdq_create_srq { 1067 u8 opcode; 1068 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 1069 #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 1070 u8 cmd_size; 1071 __le16 flags; 1072 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL 1073 #define CMDQ_CREATE_SRQ_FLAGS_PBL_PG_SIZE_VALID 0x2UL 1074 __le16 cookie; 1075 u8 resp_size; 1076 u8 reserved8; 1077 __le64 resp_addr; 1078 __le64 srq_handle; 1079 __le16 pg_size_lvl; 1080 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 1081 #define CMDQ_CREATE_SRQ_LVL_SFT 0 1082 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 1083 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 1084 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 1085 #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 1086 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 1087 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 1088 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 1089 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 1090 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 1091 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 1092 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 1093 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 1094 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G 1095 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL 1096 #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 1097 __le16 eventq_id; 1098 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 1099 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 1100 #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL 1101 #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 1102 __le16 srq_size; 1103 __le16 srq_fwo; 1104 #define CMDQ_CREATE_SRQ_SRQ_FWO_MASK 0xfffUL 1105 #define CMDQ_CREATE_SRQ_SRQ_FWO_SFT 0 1106 #define CMDQ_CREATE_SRQ_SRQ_SGE_MASK 0xf000UL 1107 #define CMDQ_CREATE_SRQ_SRQ_SGE_SFT 12 1108 __le32 dpi; 1109 __le32 pd_id; 1110 __le64 pbl; 1111 __le16 steering_tag; 1112 u8 pbl_pg_size; 1113 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_MASK 0x7UL 1114 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_SFT 0 1115 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_4K 0x0UL 1116 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_8K 0x1UL 1117 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_64K 0x2UL 1118 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_2M 0x3UL 1119 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_8M 0x4UL 1120 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_1G 0x5UL 1121 #define CMDQ_CREATE_SRQ_PBL_PG_SIZE_LAST CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_1G 1122 u8 reserved40[5]; 1123 __le64 reserved64; 1124 }; 1125 1126 /* creq_create_srq_resp (size:128b/16B) */ 1127 struct creq_create_srq_resp { 1128 u8 type; 1129 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 1130 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 1131 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1132 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 1133 u8 status; 1134 __le16 cookie; 1135 __le32 xid; 1136 u8 v; 1137 #define CREQ_CREATE_SRQ_RESP_V 0x1UL 1138 u8 event; 1139 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 1140 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 1141 u8 context_size; 1142 u8 reserved48[5]; 1143 }; 1144 1145 /* cmdq_destroy_srq (size:192b/24B) */ 1146 struct cmdq_destroy_srq { 1147 u8 opcode; 1148 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1149 #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 1150 u8 cmd_size; 1151 __le16 flags; 1152 __le16 cookie; 1153 u8 resp_size; 1154 u8 reserved8; 1155 __le64 resp_addr; 1156 __le32 srq_cid; 1157 __le32 unused_0; 1158 }; 1159 1160 /* creq_destroy_srq_resp (size:128b/16B) */ 1161 struct creq_destroy_srq_resp { 1162 u8 type; 1163 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 1164 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 1165 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1166 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 1167 u8 status; 1168 __le16 cookie; 1169 __le32 xid; 1170 u8 v; 1171 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 1172 u8 event; 1173 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 1174 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 1175 __le16 enable_for_arm[3]; 1176 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL 1177 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 1178 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 1179 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 1180 }; 1181 1182 /* cmdq_query_srq (size:192b/24B) */ 1183 struct cmdq_query_srq { 1184 u8 opcode; 1185 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1186 #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 1187 u8 cmd_size; 1188 __le16 flags; 1189 __le16 cookie; 1190 u8 resp_size; 1191 u8 reserved8; 1192 __le64 resp_addr; 1193 __le32 srq_cid; 1194 __le32 unused_0; 1195 }; 1196 1197 /* creq_query_srq_resp (size:128b/16B) */ 1198 struct creq_query_srq_resp { 1199 u8 type; 1200 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 1201 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 1202 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1203 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 1204 u8 status; 1205 __le16 cookie; 1206 __le32 size; 1207 u8 v; 1208 #define CREQ_QUERY_SRQ_RESP_V 0x1UL 1209 u8 event; 1210 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 1211 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 1212 u8 reserved48[6]; 1213 }; 1214 1215 /* creq_query_srq_resp_sb (size:256b/32B) */ 1216 struct creq_query_srq_resp_sb { 1217 u8 opcode; 1218 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 1219 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 1220 u8 status; 1221 __le16 cookie; 1222 __le16 flags; 1223 u8 resp_size; 1224 u8 reserved8; 1225 __le32 xid; 1226 __le16 srq_limit; 1227 __le16 reserved16; 1228 __le32 data[4]; 1229 }; 1230 1231 /* cmdq_create_cq (size:512b/64B) */ 1232 struct cmdq_create_cq { 1233 u8 opcode; 1234 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1235 #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 1236 u8 cmd_size; 1237 __le16 flags; 1238 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL 1239 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL 1240 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL 1241 #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID 0x8UL 1242 #define CMDQ_CREATE_CQ_FLAGS_PBL_PG_SIZE_VALID 0x10UL 1243 __le16 cookie; 1244 u8 resp_size; 1245 u8 reserved8; 1246 __le64 resp_addr; 1247 __le64 cq_handle; 1248 __le32 pg_size_lvl; 1249 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1250 #define CMDQ_CREATE_CQ_LVL_SFT 0 1251 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1252 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1253 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1254 #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 1255 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1256 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1257 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1258 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1259 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1260 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1261 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1262 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1263 #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G 1264 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL 1265 #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 1266 __le32 cq_fco_cnq_id; 1267 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1268 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1269 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1270 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1271 __le32 dpi; 1272 __le32 cq_size; 1273 __le64 pbl; 1274 __le16 steering_tag; 1275 u8 pbl_pg_size; 1276 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_MASK 0x7UL 1277 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_SFT 0 1278 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_4K 0x0UL 1279 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_8K 0x1UL 1280 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_64K 0x2UL 1281 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_2M 0x3UL 1282 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_8M 0x4UL 1283 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_1G 0x5UL 1284 #define CMDQ_CREATE_CQ_PBL_PG_SIZE_LAST CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_1G 1285 u8 reserved8_1; 1286 __le32 coalescing; 1287 #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK 0x1ffUL 1288 #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0 1289 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK 0x3e00UL 1290 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9 1291 #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK 0x7c000UL 1292 #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14 1293 #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE 0x80000UL 1294 #define CMDQ_CREATE_CQ_UNUSED12_MASK 0xfff00000UL 1295 #define CMDQ_CREATE_CQ_UNUSED12_SFT 20 1296 __le64 reserved64; 1297 }; 1298 1299 /* creq_create_cq_resp (size:128b/16B) */ 1300 struct creq_create_cq_resp { 1301 u8 type; 1302 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 1303 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 1304 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1305 #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 1306 u8 status; 1307 __le16 cookie; 1308 __le32 xid; 1309 u8 v; 1310 #define CREQ_CREATE_CQ_RESP_V 0x1UL 1311 u8 event; 1312 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 1313 #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 1314 u8 context_size; 1315 u8 reserved48[5]; 1316 }; 1317 1318 /* cmdq_destroy_cq (size:192b/24B) */ 1319 struct cmdq_destroy_cq { 1320 u8 opcode; 1321 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1322 #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 1323 u8 cmd_size; 1324 __le16 flags; 1325 __le16 cookie; 1326 u8 resp_size; 1327 u8 reserved8; 1328 __le64 resp_addr; 1329 __le32 cq_cid; 1330 __le32 unused_0; 1331 }; 1332 1333 /* creq_destroy_cq_resp (size:128b/16B) */ 1334 struct creq_destroy_cq_resp { 1335 u8 type; 1336 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 1337 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 1338 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 1339 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 1340 u8 status; 1341 __le16 cookie; 1342 __le32 xid; 1343 u8 v; 1344 #define CREQ_DESTROY_CQ_RESP_V 0x1UL 1345 u8 event; 1346 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 1347 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 1348 __le16 cq_arm_lvl; 1349 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 1350 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 1351 __le16 total_cnq_events; 1352 __le16 reserved16; 1353 }; 1354 1355 /* cmdq_resize_cq (size:320b/40B) */ 1356 struct cmdq_resize_cq { 1357 u8 opcode; 1358 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1359 #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 1360 u8 cmd_size; 1361 __le16 flags; 1362 #define CMDQ_RESIZE_CQ_FLAGS_PBL_PG_SIZE_VALID 0x1UL 1363 __le16 cookie; 1364 u8 resp_size; 1365 u8 reserved8; 1366 __le64 resp_addr; 1367 __le32 cq_cid; 1368 __le32 new_cq_size_pg_size_lvl; 1369 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1370 #define CMDQ_RESIZE_CQ_LVL_SFT 0 1371 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1372 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1373 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1374 #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 1375 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1376 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1377 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1378 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1379 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1380 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1381 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1382 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1383 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G 1384 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL 1385 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1386 __le64 new_pbl; 1387 __le32 new_cq_fco; 1388 #define CMDQ_RESIZE_CQ_CQ_FCO_MASK 0xfffffUL 1389 #define CMDQ_RESIZE_CQ_CQ_FCO_SFT 0 1390 #define CMDQ_RESIZE_CQ_RSVD_MASK 0xfff00000UL 1391 #define CMDQ_RESIZE_CQ_RSVD_SFT 20 1392 u8 pbl_pg_size; 1393 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_MASK 0x7UL 1394 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_SFT 0 1395 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_4K 0x0UL 1396 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_8K 0x1UL 1397 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_64K 0x2UL 1398 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_2M 0x3UL 1399 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_8M 0x4UL 1400 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_1G 0x5UL 1401 #define CMDQ_RESIZE_CQ_PBL_PG_SIZE_LAST CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_1G 1402 u8 unused_0[3]; 1403 }; 1404 1405 /* creq_resize_cq_resp (size:128b/16B) */ 1406 struct creq_resize_cq_resp { 1407 u8 type; 1408 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 1409 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 1410 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1411 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 1412 u8 status; 1413 __le16 cookie; 1414 __le32 xid; 1415 u8 v; 1416 #define CREQ_RESIZE_CQ_RESP_V 0x1UL 1417 u8 event; 1418 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 1419 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 1420 u8 reserved48[6]; 1421 }; 1422 1423 /* cmdq_allocate_mrw (size:256b/32B) */ 1424 struct cmdq_allocate_mrw { 1425 u8 opcode; 1426 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1427 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 1428 u8 cmd_size; 1429 __le16 flags; 1430 __le16 cookie; 1431 u8 resp_size; 1432 u8 reserved8; 1433 __le64 resp_addr; 1434 __le64 mrw_handle; 1435 u8 mrw_flags; 1436 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1437 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1438 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1439 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1440 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1441 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1442 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1443 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 1444 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID 0x10UL 1445 #define CMDQ_ALLOCATE_MRW_UNUSED3_MASK 0xe0UL 1446 #define CMDQ_ALLOCATE_MRW_UNUSED3_SFT 5 1447 u8 access; 1448 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1449 __le16 steering_tag; 1450 __le32 pd_id; 1451 }; 1452 1453 /* creq_allocate_mrw_resp (size:128b/16B) */ 1454 struct creq_allocate_mrw_resp { 1455 u8 type; 1456 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 1457 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 1458 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 1459 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 1460 u8 status; 1461 __le16 cookie; 1462 __le32 xid; 1463 u8 v; 1464 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 1465 u8 event; 1466 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 1467 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 1468 u8 context_size; 1469 u8 reserved48[5]; 1470 }; 1471 1472 /* cmdq_deallocate_key (size:192b/24B) */ 1473 struct cmdq_deallocate_key { 1474 u8 opcode; 1475 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1476 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 1477 u8 cmd_size; 1478 __le16 flags; 1479 __le16 cookie; 1480 u8 resp_size; 1481 u8 reserved8; 1482 __le64 resp_addr; 1483 u8 mrw_flags; 1484 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1485 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1486 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1487 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1488 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1489 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1490 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1491 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 1492 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL 1493 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 1494 u8 unused24[3]; 1495 __le32 key; 1496 }; 1497 1498 /* creq_deallocate_key_resp (size:128b/16B) */ 1499 struct creq_deallocate_key_resp { 1500 u8 type; 1501 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 1502 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 1503 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 1504 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 1505 u8 status; 1506 __le16 cookie; 1507 __le32 xid; 1508 u8 v; 1509 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 1510 u8 event; 1511 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 1512 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 1513 __le16 reserved16; 1514 __le32 bound_window_info; 1515 }; 1516 1517 /* cmdq_register_mr (size:512b/64B) */ 1518 struct cmdq_register_mr { 1519 u8 opcode; 1520 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1521 #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 1522 u8 cmd_size; 1523 __le16 flags; 1524 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL 1525 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL 1526 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO 0x4UL 1527 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_EROCE 0x8UL 1528 __le16 cookie; 1529 u8 resp_size; 1530 u8 reserved8; 1531 __le64 resp_addr; 1532 u8 log2_pg_size_lvl; 1533 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1534 #define CMDQ_REGISTER_MR_LVL_SFT 0 1535 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1536 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1537 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1538 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1539 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1540 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1541 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1542 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1543 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1544 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1545 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1546 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1547 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1548 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1549 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1550 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1551 u8 access; 1552 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1553 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1554 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1555 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1556 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1557 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1558 __le16 log2_pbl_pg_size; 1559 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1560 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1561 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1562 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1563 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1564 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1565 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1566 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1567 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1568 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1569 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1570 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1571 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1572 __le32 key; 1573 __le64 pbl; 1574 __le64 va; 1575 __le64 mr_size; 1576 __le16 steering_tag; 1577 u8 reserved48[6]; 1578 __le64 reserved64; 1579 }; 1580 1581 /* creq_register_mr_resp (size:128b/16B) */ 1582 struct creq_register_mr_resp { 1583 u8 type; 1584 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 1585 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 1586 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1587 #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 1588 u8 status; 1589 __le16 cookie; 1590 __le32 xid; 1591 u8 v; 1592 #define CREQ_REGISTER_MR_RESP_V 0x1UL 1593 u8 event; 1594 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 1595 #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 1596 u8 context_size; 1597 u8 reserved48[5]; 1598 }; 1599 1600 /* cmdq_deregister_mr (size:192b/24B) */ 1601 struct cmdq_deregister_mr { 1602 u8 opcode; 1603 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1604 #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 1605 u8 cmd_size; 1606 __le16 flags; 1607 #define CMDQ_DEREGISTER_MR_FLAGS_ENABLE_EROCE 0x1UL 1608 __le16 cookie; 1609 u8 resp_size; 1610 u8 reserved8; 1611 __le64 resp_addr; 1612 __le32 lkey; 1613 __le32 unused_0; 1614 }; 1615 1616 /* creq_deregister_mr_resp (size:128b/16B) */ 1617 struct creq_deregister_mr_resp { 1618 u8 type; 1619 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 1620 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 1621 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1622 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 1623 u8 status; 1624 __le16 cookie; 1625 __le32 xid; 1626 u8 v; 1627 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 1628 u8 event; 1629 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 1630 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 1631 __le16 reserved16; 1632 __le32 bound_windows; 1633 }; 1634 1635 /* cmdq_add_gid (size:384b/48B) */ 1636 struct cmdq_add_gid { 1637 u8 opcode; 1638 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1639 #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID 1640 u8 cmd_size; 1641 __le16 flags; 1642 __le16 cookie; 1643 u8 resp_size; 1644 u8 reserved8; 1645 __le64 resp_addr; 1646 __le32 gid[4]; 1647 __le16 src_mac[3]; 1648 __le16 vlan; 1649 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1650 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1651 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1652 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1653 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1654 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1655 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1656 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1657 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1658 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1659 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1660 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1661 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1662 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1663 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1664 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1665 __le16 ipid; 1666 __le16 stats_ctx; 1667 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL 1668 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 1669 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1670 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1671 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1672 __le16 host_gid_index; 1673 __le16 unused_0; 1674 }; 1675 1676 /* creq_add_gid_resp (size:128b/16B) */ 1677 struct creq_add_gid_resp { 1678 u8 type; 1679 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 1680 #define CREQ_ADD_GID_RESP_TYPE_SFT 0 1681 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 1682 #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT 1683 u8 status; 1684 __le16 cookie; 1685 __le32 xid; 1686 u8 v; 1687 #define CREQ_ADD_GID_RESP_V 0x1UL 1688 u8 event; 1689 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 1690 #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID 1691 u8 reserved48[6]; 1692 }; 1693 1694 /* cmdq_delete_gid (size:192b/24B) */ 1695 struct cmdq_delete_gid { 1696 u8 opcode; 1697 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1698 #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID 1699 u8 cmd_size; 1700 __le16 flags; 1701 __le16 cookie; 1702 u8 resp_size; 1703 u8 reserved8; 1704 __le64 resp_addr; 1705 __le16 gid_index; 1706 __le16 host_gid_index; 1707 u8 unused_0[4]; 1708 }; 1709 1710 /* creq_delete_gid_resp (size:128b/16B) */ 1711 struct creq_delete_gid_resp { 1712 u8 type; 1713 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 1714 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 1715 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 1716 #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 1717 u8 status; 1718 __le16 cookie; 1719 __le32 xid; 1720 u8 v; 1721 #define CREQ_DELETE_GID_RESP_V 0x1UL 1722 u8 event; 1723 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 1724 #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 1725 u8 reserved48[6]; 1726 }; 1727 1728 /* cmdq_modify_gid (size:384b/48B) */ 1729 struct cmdq_modify_gid { 1730 u8 opcode; 1731 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1732 #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 1733 u8 cmd_size; 1734 __le16 flags; 1735 __le16 cookie; 1736 u8 resp_size; 1737 u8 reserved8; 1738 __le64 resp_addr; 1739 __le32 gid[4]; 1740 __le16 src_mac[3]; 1741 __le16 vlan; 1742 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1743 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1744 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1745 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1746 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1747 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1748 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1749 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1750 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1751 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1752 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1753 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1754 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1755 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1756 __le16 ipid; 1757 __le16 gid_index; 1758 __le16 stats_ctx; 1759 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1760 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1761 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1762 __le16 host_gid_index; 1763 }; 1764 1765 /* creq_modify_gid_resp (size:128b/16B) */ 1766 struct creq_modify_gid_resp { 1767 u8 type; 1768 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 1769 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 1770 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 1771 #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 1772 u8 status; 1773 __le16 cookie; 1774 __le32 xid; 1775 u8 v; 1776 #define CREQ_MODIFY_GID_RESP_V 0x1UL 1777 u8 event; 1778 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 1779 #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 1780 u8 reserved48[6]; 1781 }; 1782 1783 /* cmdq_query_gid (size:192b/24B) */ 1784 struct cmdq_query_gid { 1785 u8 opcode; 1786 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1787 #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID 1788 u8 cmd_size; 1789 __le16 flags; 1790 __le16 cookie; 1791 u8 resp_size; 1792 u8 reserved8; 1793 __le64 resp_addr; 1794 __le16 gid_index; 1795 u8 unused16[6]; 1796 }; 1797 1798 /* creq_query_gid_resp (size:128b/16B) */ 1799 struct creq_query_gid_resp { 1800 u8 type; 1801 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 1802 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 1803 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 1804 #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 1805 u8 status; 1806 __le16 cookie; 1807 __le32 size; 1808 u8 v; 1809 #define CREQ_QUERY_GID_RESP_V 0x1UL 1810 u8 event; 1811 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 1812 #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 1813 u8 reserved48[6]; 1814 }; 1815 1816 /* creq_query_gid_resp_sb (size:320b/40B) */ 1817 struct creq_query_gid_resp_sb { 1818 u8 opcode; 1819 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 1820 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 1821 u8 status; 1822 __le16 cookie; 1823 __le16 flags; 1824 u8 resp_size; 1825 u8 reserved8; 1826 __le32 gid[4]; 1827 __le16 src_mac[3]; 1828 __le16 vlan; 1829 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1830 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1831 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 1832 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 1833 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 1834 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 1835 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1836 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 1837 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 1838 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 1839 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 1840 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1841 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1842 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1843 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 1844 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 1845 __le16 ipid; 1846 __le16 gid_index; 1847 __le32 unused_0; 1848 }; 1849 1850 /* cmdq_create_qp1 (size:640b/80B) */ 1851 struct cmdq_create_qp1 { 1852 u8 opcode; 1853 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1854 #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 1855 u8 cmd_size; 1856 __le16 flags; 1857 __le16 cookie; 1858 u8 resp_size; 1859 u8 reserved8; 1860 __le64 resp_addr; 1861 __le64 qp_handle; 1862 __le32 qp_flags; 1863 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1864 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1865 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1866 #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 1867 u8 type; 1868 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1869 #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI 1870 u8 sq_pg_size_sq_lvl; 1871 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1872 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1873 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1874 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1875 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1876 #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 1877 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1878 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1879 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1880 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1881 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1882 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1883 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1884 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1885 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G 1886 u8 rq_pg_size_rq_lvl; 1887 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1888 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1889 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1890 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1891 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1892 #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 1893 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1894 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1895 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1896 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1897 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1898 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1899 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1900 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1901 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G 1902 u8 unused_0; 1903 __le32 dpi; 1904 __le32 sq_size; 1905 __le32 rq_size; 1906 __le16 sq_fwo_sq_sge; 1907 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1908 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1909 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1910 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1911 __le16 rq_fwo_rq_sge; 1912 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1913 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1914 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1915 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1916 __le32 scq_cid; 1917 __le32 rcq_cid; 1918 __le32 srq_cid; 1919 __le32 pd_id; 1920 __le64 sq_pbl; 1921 __le64 rq_pbl; 1922 }; 1923 1924 /* creq_create_qp1_resp (size:128b/16B) */ 1925 struct creq_create_qp1_resp { 1926 u8 type; 1927 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 1928 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 1929 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 1930 #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 1931 u8 status; 1932 __le16 cookie; 1933 __le32 xid; 1934 u8 v; 1935 #define CREQ_CREATE_QP1_RESP_V 0x1UL 1936 u8 event; 1937 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 1938 #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 1939 u8 reserved48[6]; 1940 }; 1941 1942 /* cmdq_destroy_qp1 (size:192b/24B) */ 1943 struct cmdq_destroy_qp1 { 1944 u8 opcode; 1945 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1946 #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 1947 u8 cmd_size; 1948 __le16 flags; 1949 __le16 cookie; 1950 u8 resp_size; 1951 u8 reserved8; 1952 __le64 resp_addr; 1953 __le32 qp1_cid; 1954 __le32 unused_0; 1955 }; 1956 1957 /* creq_destroy_qp1_resp (size:128b/16B) */ 1958 struct creq_destroy_qp1_resp { 1959 u8 type; 1960 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 1961 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 1962 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 1963 #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 1964 u8 status; 1965 __le16 cookie; 1966 __le32 xid; 1967 u8 v; 1968 #define CREQ_DESTROY_QP1_RESP_V 0x1UL 1969 u8 event; 1970 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 1971 #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 1972 u8 reserved48[6]; 1973 }; 1974 1975 /* cmdq_create_ah (size:512b/64B) */ 1976 struct cmdq_create_ah { 1977 u8 opcode; 1978 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1979 #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH 1980 u8 cmd_size; 1981 __le16 flags; 1982 __le16 cookie; 1983 u8 resp_size; 1984 u8 reserved8; 1985 __le64 resp_addr; 1986 __le64 ah_handle; 1987 __le32 dgid[4]; 1988 u8 type; 1989 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1990 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1991 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1992 #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 1993 u8 hop_limit; 1994 __le16 sgid_index; 1995 __le32 dest_vlan_id_flow_label; 1996 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1997 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1998 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1999 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 2000 __le32 pd_id; 2001 __le32 unused_0; 2002 __le16 dest_mac[3]; 2003 u8 traffic_class; 2004 u8 enable_cc; 2005 #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL 2006 }; 2007 2008 /* creq_create_ah_resp (size:128b/16B) */ 2009 struct creq_create_ah_resp { 2010 u8 type; 2011 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 2012 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 2013 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 2014 #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 2015 u8 status; 2016 __le16 cookie; 2017 __le32 xid; 2018 u8 v; 2019 #define CREQ_CREATE_AH_RESP_V 0x1UL 2020 u8 event; 2021 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 2022 #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 2023 u8 reserved48[6]; 2024 }; 2025 2026 /* cmdq_destroy_ah (size:192b/24B) */ 2027 struct cmdq_destroy_ah { 2028 u8 opcode; 2029 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 2030 #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 2031 u8 cmd_size; 2032 __le16 flags; 2033 __le16 cookie; 2034 u8 resp_size; 2035 u8 reserved8; 2036 __le64 resp_addr; 2037 __le32 ah_cid; 2038 __le32 unused_0; 2039 }; 2040 2041 /* creq_destroy_ah_resp (size:128b/16B) */ 2042 struct creq_destroy_ah_resp { 2043 u8 type; 2044 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 2045 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 2046 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 2047 #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 2048 u8 status; 2049 __le16 cookie; 2050 __le32 xid; 2051 u8 v; 2052 #define CREQ_DESTROY_AH_RESP_V 0x1UL 2053 u8 event; 2054 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 2055 #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 2056 u8 reserved48[6]; 2057 }; 2058 2059 /* cmdq_query_roce_stats (size:192b/24B) */ 2060 struct cmdq_query_roce_stats { 2061 u8 opcode; 2062 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 2063 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 2064 u8 cmd_size; 2065 __le16 flags; 2066 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL 2067 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL 2068 __le16 cookie; 2069 u8 resp_size; 2070 u8 collection_id; 2071 __le64 resp_addr; 2072 __le32 function_id; 2073 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL 2074 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 2075 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL 2076 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 2077 #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL 2078 __le32 reserved32; 2079 }; 2080 2081 /* creq_query_roce_stats_resp (size:128b/16B) */ 2082 struct creq_query_roce_stats_resp { 2083 u8 type; 2084 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 2085 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 2086 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 2087 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 2088 u8 status; 2089 __le16 cookie; 2090 __le32 size; 2091 u8 v; 2092 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 2093 u8 event; 2094 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 2095 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 2096 u8 reserved48[6]; 2097 }; 2098 2099 /* creq_query_roce_stats_resp_sb (size:3072b/384B) */ 2100 struct creq_query_roce_stats_resp_sb { 2101 u8 opcode; 2102 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 2103 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 2104 u8 status; 2105 __le16 cookie; 2106 __le16 flags; 2107 u8 resp_size; 2108 u8 rsvd; 2109 __le32 num_counters; 2110 __le32 rsvd1; 2111 __le64 to_retransmits; 2112 __le64 seq_err_naks_rcvd; 2113 __le64 max_retry_exceeded; 2114 __le64 rnr_naks_rcvd; 2115 __le64 missing_resp; 2116 __le64 unrecoverable_err; 2117 __le64 bad_resp_err; 2118 __le64 local_qp_op_err; 2119 __le64 local_protection_err; 2120 __le64 mem_mgmt_op_err; 2121 __le64 remote_invalid_req_err; 2122 __le64 remote_access_err; 2123 __le64 remote_op_err; 2124 __le64 dup_req; 2125 __le64 res_exceed_max; 2126 __le64 res_length_mismatch; 2127 __le64 res_exceeds_wqe; 2128 __le64 res_opcode_err; 2129 __le64 res_rx_invalid_rkey; 2130 __le64 res_rx_domain_err; 2131 __le64 res_rx_no_perm; 2132 __le64 res_rx_range_err; 2133 __le64 res_tx_invalid_rkey; 2134 __le64 res_tx_domain_err; 2135 __le64 res_tx_no_perm; 2136 __le64 res_tx_range_err; 2137 __le64 res_irrq_oflow; 2138 __le64 res_unsup_opcode; 2139 __le64 res_unaligned_atomic; 2140 __le64 res_rem_inv_err; 2141 __le64 res_mem_error; 2142 __le64 res_srq_err; 2143 __le64 res_cmp_err; 2144 __le64 res_invalid_dup_rkey; 2145 __le64 res_wqe_format_err; 2146 __le64 res_cq_load_err; 2147 __le64 res_srq_load_err; 2148 __le64 res_tx_pci_err; 2149 __le64 res_rx_pci_err; 2150 __le64 res_oos_drop_count; 2151 __le64 active_qp_count_p0; 2152 __le64 active_qp_count_p1; 2153 __le64 active_qp_count_p2; 2154 __le64 active_qp_count_p3; 2155 __le64 xp_sq_overflow_err; 2156 __le64 xp_rq_overflow_error; 2157 }; 2158 2159 /* cmdq_query_roce_stats_ext (size:192b/24B) */ 2160 struct cmdq_query_roce_stats_ext { 2161 u8 opcode; 2162 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL 2163 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 2164 u8 cmd_size; 2165 __le16 flags; 2166 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL 2167 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL 2168 __le16 cookie; 2169 u8 resp_size; 2170 u8 collection_id; 2171 __le64 resp_addr; 2172 __le32 function_id; 2173 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL 2174 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 2175 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL 2176 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 2177 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL 2178 __le32 reserved32; 2179 }; 2180 2181 /* creq_query_roce_stats_ext_resp (size:128b/16B) */ 2182 struct creq_query_roce_stats_ext_resp { 2183 u8 type; 2184 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL 2185 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 2186 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL 2187 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 2188 u8 status; 2189 __le16 cookie; 2190 __le32 size; 2191 u8 v; 2192 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL 2193 u8 event; 2194 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL 2195 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 2196 u8 reserved48[6]; 2197 }; 2198 2199 /* creq_query_roce_stats_ext_resp_sb (size:2368b/296B) */ 2200 struct creq_query_roce_stats_ext_resp_sb { 2201 u8 opcode; 2202 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 2203 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 2204 u8 status; 2205 __le16 cookie; 2206 __le16 flags; 2207 u8 resp_size; 2208 u8 rsvd; 2209 __le64 rx_ack_pkts; 2210 __le64 tx_atomic_req_pkts; 2211 __le64 tx_read_req_pkts; 2212 __le64 tx_read_res_pkts; 2213 __le64 tx_write_req_pkts; 2214 __le64 tx_send_req_pkts; 2215 __le64 tx_roce_pkts; 2216 __le64 tx_roce_bytes; 2217 __le64 rx_atomic_req_pkts; 2218 __le64 rx_read_req_pkts; 2219 __le64 rx_read_res_pkts; 2220 __le64 rx_write_req_pkts; 2221 __le64 rx_send_req_pkts; 2222 __le64 rx_roce_pkts; 2223 __le64 rx_roce_bytes; 2224 __le64 rx_roce_good_pkts; 2225 __le64 rx_roce_good_bytes; 2226 __le64 rx_out_of_buffer_pkts; 2227 __le64 rx_out_of_sequence_pkts; 2228 __le64 tx_cnp_pkts; 2229 __le64 rx_cnp_pkts; 2230 __le64 rx_ecn_marked_pkts; 2231 __le64 tx_cnp_bytes; 2232 __le64 rx_cnp_bytes; 2233 __le64 seq_err_naks_rcvd; 2234 __le64 rnr_naks_rcvd; 2235 __le64 missing_resp; 2236 __le64 to_retransmit; 2237 __le64 dup_req; 2238 __le64 rx_dcn_payload_cut; 2239 __le64 te_bypassed; 2240 __le64 tx_dcn_cnp; 2241 __le64 rx_dcn_cnp; 2242 __le64 rx_payload_cut; 2243 __le64 rx_payload_cut_ignored; 2244 __le64 rx_dcn_cnp_ignored; 2245 }; 2246 2247 /* cmdq_query_func (size:128b/16B) */ 2248 struct cmdq_query_func { 2249 u8 opcode; 2250 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 2251 #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 2252 u8 cmd_size; 2253 __le16 flags; 2254 __le16 cookie; 2255 u8 resp_size; 2256 u8 reserved8; 2257 __le64 resp_addr; 2258 }; 2259 2260 /* creq_query_func_resp (size:128b/16B) */ 2261 struct creq_query_func_resp { 2262 u8 type; 2263 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2264 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2265 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2266 #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 2267 u8 status; 2268 __le16 cookie; 2269 __le32 size; 2270 u8 v; 2271 #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2272 u8 event; 2273 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2274 #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 2275 u8 reserved48[6]; 2276 }; 2277 2278 /* creq_query_func_resp_sb (size:1728b/216B) */ 2279 struct creq_query_func_resp_sb { 2280 u8 opcode; 2281 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2282 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 2283 u8 status; 2284 __le16 cookie; 2285 __le16 flags; 2286 u8 resp_size; 2287 u8 reserved8; 2288 __le64 max_mr_size; 2289 __le32 max_qp; 2290 __le16 max_qp_wr; 2291 __le16 dev_cap_flags; 2292 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL 2293 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL 2294 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 2295 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1) 2296 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1) 2297 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1) 2298 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 (0x3UL << 1) 2299 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2_EXT (0x4UL << 1) 2300 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2_EXT 2301 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL 2302 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL 2303 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL 2304 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL 2305 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL 2306 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL 2307 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL 2308 #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED 0x800UL 2309 #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID 0x1000UL 2310 #define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED 0x2000UL 2311 #define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED 0x4000UL 2312 #define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY 0x8000UL 2313 __le32 max_cq; 2314 __le32 max_cqe; 2315 __le32 max_pd; 2316 u8 max_sge; 2317 u8 max_srq_sge; 2318 u8 max_qp_rd_atom; 2319 u8 max_qp_init_rd_atom; 2320 __le32 max_mr; 2321 __le32 max_mw; 2322 __le32 max_raw_eth_qp; 2323 __le32 max_ah; 2324 __le32 max_fmr; 2325 __le32 max_srq_wr; 2326 __le32 max_pkeys; 2327 __le32 max_inline_data; 2328 u8 max_map_per_fmr; 2329 u8 l2_db_space_size; 2330 __le16 max_srq; 2331 __le32 max_gid; 2332 __le32 tqm_alloc_reqs[12]; 2333 __le32 max_dpi; 2334 u8 max_sge_var_wqe; 2335 u8 dev_cap_ext_flags; 2336 #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL 2337 #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL 2338 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL 2339 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL 2340 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL 2341 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL 2342 #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL 2343 #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL 2344 __le16 max_inline_data_var_wqe; 2345 __le32 start_qid; 2346 u8 max_msn_table_size; 2347 u8 dev_cap_ext_flags_1; 2348 #define CREQ_QUERY_FUNC_RESP_SB_PBL_PAGE_SIZE_SUPPORTED 0x1UL 2349 #define CREQ_QUERY_FUNC_RESP_SB_INFINITE_RETRY_TO_RETX_SUPPORTED 0x2UL 2350 __le16 dev_cap_ext_flags_2; 2351 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL 2352 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL 2353 #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL 2354 #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL 2355 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL 2356 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4 2357 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4) 2358 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4) 2359 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4) 2360 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE 2361 #define CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED 0x40UL 2362 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_SUPPORTED 0x80UL 2363 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_CONTEXT_SB_SUPPORTED 0x100UL 2364 #define CREQ_QUERY_FUNC_RESP_SB_DEFAULT_ROCE_CC_PARAMS_SUPPORTED 0x200UL 2365 #define CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED 0x400UL 2366 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_UDCC_SESSION_SB_SUPPORTED 0x800UL 2367 #define CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED 0x1000UL 2368 #define CREQ_QUERY_FUNC_RESP_SB_CQ_OVERFLOW_DETECTION_ENABLED 0x2000UL 2369 #define CREQ_QUERY_FUNC_RESP_SB_ICRC_CHECK_DISABLE_SUPPORTED 0x4000UL 2370 #define CREQ_QUERY_FUNC_RESP_SB_FORCE_MIRROR_ENABLE_SUPPORTED 0x8000UL 2371 __le16 max_xp_qp_size; 2372 __le16 create_qp_batch_size; 2373 __le16 destroy_qp_batch_size; 2374 __le16 max_srq_ext; 2375 __le16 roce_cc_tlv_en_flags; 2376 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_CC_GEN2_TLV_EN 0x1UL 2377 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_CC_GEN1_EXT_TLV_EN 0x2UL 2378 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_CC_GEN2_EXT_TLV_EN 0x4UL 2379 __le16 pno_flags; 2380 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_ENABLED 0x1UL 2381 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_ENABLED_ON_PF 0x2UL 2382 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_EXT_ENABLED 0x4UL 2383 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_EXT_ENABLED_ON_PF 0x8UL 2384 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PSP_ENABLED 0x10UL 2385 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PSP_ENABLED_ON_PF 0x20UL 2386 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_DYNAMIC_TUNNELS_ENABLED 0x40UL 2387 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PER_TUNNEL_EV_MONITORING_SUPPORTED 0x80UL 2388 u8 pno_tnl_dest_grp_auto; 2389 u8 pno_max_tnl_per_endpoint; 2390 u8 pno_cc_algo; 2391 u8 pno_pf_num; 2392 __le32 pno_max_endpoints; 2393 u8 eroce_spec_dscp[2]; 2394 u8 eroce_pull_dscp[2]; 2395 u8 eroce_retx_dscp[2]; 2396 u8 eroce_rts_dscp[2]; 2397 u8 eroce_rerouted_dscp[2]; 2398 u8 eroce_trim_dscp; 2399 u8 eroce_trim_last_hop_dscp; 2400 u8 eroce_control_dscp; 2401 u8 reserved24[3]; 2402 __le16 pno_num_debug_tunnels; 2403 u8 pno_num_cos; 2404 u8 reserved40[5]; 2405 __le32 pno_flags_ext; 2406 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_UPDATE_RTS 0x1UL 2407 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EVENT 0x2UL 2408 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EXP_ARRAY 0x4UL 2409 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_GEN_ARRAY 0x8UL 2410 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EXP_ARRAY_RANGE 0x10UL 2411 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_PROBE 0x20UL 2412 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EVENT_PRECISE_CNT 0x40UL 2413 #define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_SPRAYING_DISABLE 0x80UL 2414 __le16 max_mpr; 2415 u8 max_paths_per_path_ctx; 2416 u8 max_plane; 2417 u8 max_paths_per_plane; 2418 u8 max_strpath_tiers; 2419 u8 pno_telemetry_type; 2420 u8 reserved9_8b; 2421 __le32 max_path_ctx_strpath; 2422 __le32 max_path_ctx_srv6; 2423 __le32 rate_limit_max; 2424 __le32 rate_limit_min; 2425 }; 2426 2427 /* cmdq_set_func_resources (size:448b/56B) */ 2428 struct cmdq_set_func_resources { 2429 u8 opcode; 2430 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 2431 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 2432 u8 cmd_size; 2433 __le16 flags; 2434 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 2435 __le16 cookie; 2436 u8 resp_size; 2437 u8 reserved8; 2438 __le64 resp_addr; 2439 __le32 number_of_qp; 2440 __le32 number_of_mrw; 2441 __le32 number_of_srq; 2442 __le32 number_of_cq; 2443 __le32 max_qp_per_vf; 2444 __le32 max_mrw_per_vf; 2445 __le32 max_srq_per_vf; 2446 __le32 max_cq_per_vf; 2447 __le32 max_gid_per_vf; 2448 __le32 stat_ctx_id; 2449 }; 2450 2451 /* creq_set_func_resources_resp (size:128b/16B) */ 2452 struct creq_set_func_resources_resp { 2453 u8 type; 2454 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2455 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2456 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2457 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 2458 u8 status; 2459 __le16 cookie; 2460 __le32 reserved32; 2461 u8 v; 2462 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2463 u8 event; 2464 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2465 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \ 2466 CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 2467 u8 reserved48[6]; 2468 }; 2469 2470 /* cmdq_read_context (size:192b/24B) */ 2471 struct cmdq_read_context { 2472 u8 opcode; 2473 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL 2474 #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 2475 u8 cmd_size; 2476 __le16 flags; 2477 __le16 cookie; 2478 u8 resp_size; 2479 u8 reserved8; 2480 __le64 resp_addr; 2481 __le32 xid; 2482 u8 type; 2483 #define CMDQ_READ_CONTEXT_TYPE_QPC 0x0UL 2484 #define CMDQ_READ_CONTEXT_TYPE_CQ 0x1UL 2485 #define CMDQ_READ_CONTEXT_TYPE_MRW 0x2UL 2486 #define CMDQ_READ_CONTEXT_TYPE_SRQ 0x3UL 2487 #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ 2488 u8 unused_0[3]; 2489 }; 2490 2491 /* creq_read_context (size:128b/16B) */ 2492 struct creq_read_context { 2493 u8 type; 2494 #define CREQ_READ_CONTEXT_TYPE_MASK 0x3fUL 2495 #define CREQ_READ_CONTEXT_TYPE_SFT 0 2496 #define CREQ_READ_CONTEXT_TYPE_QP_EVENT 0x38UL 2497 #define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT 2498 u8 status; 2499 __le16 cookie; 2500 __le32 reserved32; 2501 u8 v; 2502 #define CREQ_READ_CONTEXT_V 0x1UL 2503 u8 event; 2504 #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 0x85UL 2505 #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 2506 __le16 reserved16; 2507 __le32 reserved_32; 2508 }; 2509 2510 /* cmdq_map_tc_to_cos (size:192b/24B) */ 2511 struct cmdq_map_tc_to_cos { 2512 u8 opcode; 2513 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 2514 #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 2515 u8 cmd_size; 2516 __le16 flags; 2517 __le16 cookie; 2518 u8 resp_size; 2519 u8 reserved8; 2520 __le64 resp_addr; 2521 __le16 cos0; 2522 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 2523 #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 2524 __le16 cos1; 2525 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 2526 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 2527 #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 2528 __le32 unused_0; 2529 }; 2530 2531 /* creq_map_tc_to_cos_resp (size:128b/16B) */ 2532 struct creq_map_tc_to_cos_resp { 2533 u8 type; 2534 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2535 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2536 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2537 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 2538 u8 status; 2539 __le16 cookie; 2540 __le32 reserved32; 2541 u8 v; 2542 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2543 u8 event; 2544 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2545 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 2546 u8 reserved48[6]; 2547 }; 2548 2549 /* cmdq_query_roce_cc (size:128b/16B) */ 2550 struct cmdq_query_roce_cc { 2551 u8 opcode; 2552 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL 2553 #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 2554 u8 cmd_size; 2555 __le16 flags; 2556 __le16 cookie; 2557 u8 resp_size; 2558 u8 reserved8; 2559 __le64 resp_addr; 2560 }; 2561 2562 /* creq_query_roce_cc_resp (size:128b/16B) */ 2563 struct creq_query_roce_cc_resp { 2564 u8 type; 2565 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2566 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 2567 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2568 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 2569 u8 status; 2570 __le16 cookie; 2571 __le32 size; 2572 u8 v; 2573 #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL 2574 u8 event; 2575 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL 2576 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 2577 u8 reserved48[6]; 2578 }; 2579 2580 /* creq_query_roce_cc_resp_sb (size:256b/32B) */ 2581 struct creq_query_roce_cc_resp_sb { 2582 u8 opcode; 2583 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL 2584 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 2585 u8 status; 2586 __le16 cookie; 2587 __le16 flags; 2588 u8 resp_size; 2589 u8 reserved8; 2590 u8 enable_cc; 2591 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL 2592 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL 2593 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 2594 u8 tos_dscp_tos_ecn; 2595 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL 2596 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 2597 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 2598 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 2599 u8 g; 2600 u8 num_phases_per_state; 2601 __le16 init_cr; 2602 __le16 init_tr; 2603 u8 alt_vlan_pcp; 2604 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL 2605 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 2606 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL 2607 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 2608 u8 alt_tos_dscp; 2609 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL 2610 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 2611 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL 2612 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 2613 u8 cc_mode; 2614 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL 2615 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL 2616 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 2617 u8 tx_queue; 2618 __le16 rtt; 2619 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL 2620 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 2621 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL 2622 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 2623 __le16 tcp_cp; 2624 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL 2625 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 2626 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL 2627 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 2628 __le16 inactivity_th; 2629 u8 pkts_per_phase; 2630 u8 time_per_phase; 2631 __le32 reserved32; 2632 }; 2633 2634 /* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ 2635 struct creq_query_roce_cc_resp_sb_tlv { 2636 __le16 cmd_discr; 2637 u8 reserved_8b; 2638 u8 tlv_flags; 2639 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2640 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2641 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2642 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2643 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2644 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2645 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2646 __le16 tlv_type; 2647 __le16 length; 2648 u8 total_size; 2649 u8 reserved56[7]; 2650 u8 opcode; 2651 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL 2652 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 2653 u8 status; 2654 __le16 cookie; 2655 __le16 flags; 2656 u8 resp_size; 2657 u8 reserved8; 2658 u8 enable_cc; 2659 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL 2660 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL 2661 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 2662 u8 tos_dscp_tos_ecn; 2663 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL 2664 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 2665 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL 2666 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 2667 u8 g; 2668 u8 num_phases_per_state; 2669 __le16 init_cr; 2670 __le16 init_tr; 2671 u8 alt_vlan_pcp; 2672 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL 2673 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 2674 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL 2675 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 2676 u8 alt_tos_dscp; 2677 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2678 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 2679 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL 2680 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 2681 u8 cc_mode; 2682 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL 2683 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL 2684 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 2685 u8 tx_queue; 2686 __le16 rtt; 2687 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL 2688 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 2689 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL 2690 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 2691 __le16 tcp_cp; 2692 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL 2693 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 2694 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL 2695 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 2696 __le16 inactivity_th; 2697 u8 pkts_per_phase; 2698 u8 time_per_phase; 2699 __le32 reserved32; 2700 }; 2701 2702 /* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ 2703 struct creq_query_roce_cc_gen1_resp_sb_tlv { 2704 __le16 cmd_discr; 2705 u8 reserved_8b; 2706 u8 tlv_flags; 2707 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2708 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2709 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2710 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2711 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2712 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2713 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2714 __le16 tlv_type; 2715 __le16 length; 2716 __le64 reserved64; 2717 __le16 inactivity_th_hi; 2718 __le16 min_time_between_cnps; 2719 __le16 init_cp; 2720 u8 tr_update_mode; 2721 u8 tr_update_cycles; 2722 u8 fr_num_rtts; 2723 u8 ai_rate_increase; 2724 __le16 reduction_relax_rtts_th; 2725 __le16 additional_relax_cr_th; 2726 __le16 cr_min_th; 2727 u8 bw_avg_weight; 2728 u8 actual_cr_factor; 2729 __le16 max_cp_cr_th; 2730 u8 cp_bias_en; 2731 u8 cp_bias; 2732 u8 cnp_ecn; 2733 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL 2734 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL 2735 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL 2736 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 2737 u8 rtt_jitter_en; 2738 __le16 link_bytes_per_usec; 2739 __le16 reset_cc_cr_th; 2740 u8 cr_width; 2741 u8 quota_period_min; 2742 u8 quota_period_max; 2743 u8 quota_period_abs_max; 2744 __le16 tr_lower_bound; 2745 u8 cr_prob_factor; 2746 u8 tr_prob_factor; 2747 __le16 fairness_cr_th; 2748 u8 red_div; 2749 u8 cnp_ratio_th; 2750 __le16 exp_ai_rtts; 2751 u8 exp_ai_cr_cp_ratio; 2752 u8 use_rate_table; 2753 __le16 cp_exp_update_th; 2754 __le16 high_exp_ai_rtts_th1; 2755 __le16 high_exp_ai_rtts_th2; 2756 __le16 actual_cr_cong_free_rtts_th; 2757 __le16 severe_cong_cr_th1; 2758 __le16 severe_cong_cr_th2; 2759 __le32 link64B_per_rtt; 2760 u8 cc_ack_bytes; 2761 u8 reduce_init_en; 2762 __le16 reduce_init_cong_free_rtts_th; 2763 u8 random_no_red_en; 2764 u8 actual_cr_shift_correction_en; 2765 u8 quota_period_adjust_en; 2766 u8 reserved[5]; 2767 }; 2768 2769 /* creq_query_roce_cc_gen2_resp_sb_tlv (size:512b/64B) */ 2770 struct creq_query_roce_cc_gen2_resp_sb_tlv { 2771 __le16 cmd_discr; 2772 u8 reserved_8b; 2773 u8 tlv_flags; 2774 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2775 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2776 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2777 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2778 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2779 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2780 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2781 __le16 tlv_type; 2782 __le16 length; 2783 __le64 reserved64; 2784 __le16 dcn_qlevel_tbl_thr[8]; 2785 __le32 dcn_qlevel_tbl_act[8]; 2786 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK 0x3fffUL 2787 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0 2788 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP 0x4000UL 2789 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM 0x8000UL 2790 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK 0x3fff0000UL 2791 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16 2792 }; 2793 2794 /* creq_query_roce_cc_gen1_ext_resp_sb_tlv (size:896b/112B) */ 2795 struct creq_query_roce_cc_gen1_ext_resp_sb_tlv { 2796 __le16 cmd_discr; 2797 u8 reserved_8b; 2798 u8 tlv_flags; 2799 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2800 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2801 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2802 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2803 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2804 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2805 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2806 __le16 tlv_type; 2807 __le16 length; 2808 __le64 reserved64; 2809 __le16 rnd_no_red_mult; 2810 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RND_NO_RED_MULT_MASK 0x3ffUL 2811 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RND_NO_RED_MULT_SFT 0 2812 __le16 no_red_offset; 2813 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_NO_RED_OFFSET_MASK 0x7ffUL 2814 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_NO_RED_OFFSET_SFT 0 2815 __le16 reduce2_init_cong_free_rtts_th; 2816 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_MASK 0x3ffUL 2817 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_SFT 0 2818 u8 reduce2_init_en; 2819 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_REDUCE2_INIT_EN 0x1UL 2820 u8 period_adjust_count; 2821 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_PERIOD_ADJUST_COUNT_MASK 0xffUL 2822 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_PERIOD_ADJUST_COUNT_SFT 0 2823 __le16 current_rate_threshold_1; 2824 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_1_MASK 0x3fffUL 2825 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_1_SFT 0 2826 __le16 current_rate_threshold_2; 2827 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_2_MASK 0x3fffUL 2828 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_2_SFT 0 2829 __le32 reserved32; 2830 __le64 reserved64_1; 2831 u8 rate_table_quota_period[24]; 2832 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_QUOTA_PERIOD_MASK 0xffUL 2833 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_QUOTA_PERIOD_SFT 0 2834 __le16 rate_table_byte_quota[24]; 2835 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_BYTE_QUOTA_MASK 0xffffUL 2836 #define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_BYTE_QUOTA_SFT 0 2837 }; 2838 2839 /* creq_query_roce_cc_gen2_ext_resp_sb_tlv (size:256b/32B) */ 2840 struct creq_query_roce_cc_gen2_ext_resp_sb_tlv { 2841 __le16 cmd_discr; 2842 u8 reserved_8b; 2843 u8 tlv_flags; 2844 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2845 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2846 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2847 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2848 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2849 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2850 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2851 __le16 tlv_type; 2852 __le16 length; 2853 __le64 reserved64; 2854 __le16 cr2bw_64b_ratio; 2855 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_CR2BW_64B_RATIO_MASK 0x3ffUL 2856 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_CR2BW_64B_RATIO_SFT 0 2857 u8 sr2_cc_first_cnp_en; 2858 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_SR2_CC_FIRST_CNP_EN 0x1UL 2859 u8 sr2_cc_actual_cr_en; 2860 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_SR2_CC_ACTUAL_CR_EN 0x1UL 2861 __le16 retx_cp; 2862 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CP_MASK 0x3ffUL 2863 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CP_SFT 0 2864 __le16 retx_cr; 2865 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CR_MASK 0x3fffUL 2866 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CR_SFT 0 2867 __le16 retx_tr; 2868 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_TR_MASK 0x3fffUL 2869 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_TR_SFT 0 2870 u8 hw_retx_cc_reset_en; 2871 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_ACK_TIMEOUT_EN 0x1UL 2872 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RX_NAK_EN 0x2UL 2873 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RX_RNR_NAK_EN 0x4UL 2874 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_MISSING_RESPONSE_EN 0x8UL 2875 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_DUPLICATE_READ_EN 0x10UL 2876 u8 reserved8; 2877 __le16 hw_retx_reset_cc_cr_th; 2878 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_HW_RETX_RESET_CC_CR_TH_MASK 0x3fffUL 2879 #define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_HW_RETX_RESET_CC_CR_TH_SFT 0 2880 __le16 reserved16; 2881 }; 2882 2883 /* cmdq_modify_roce_cc (size:448b/56B) */ 2884 struct cmdq_modify_roce_cc { 2885 u8 opcode; 2886 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL 2887 #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 2888 u8 cmd_size; 2889 __le16 flags; 2890 __le16 cookie; 2891 u8 resp_size; 2892 u8 reserved8; 2893 __le64 resp_addr; 2894 __le32 modify_mask; 2895 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL 2896 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL 2897 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2898 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL 2899 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL 2900 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL 2901 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL 2902 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2903 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2904 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL 2905 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL 2906 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL 2907 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL 2908 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2909 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2910 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2911 u8 enable_cc; 2912 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL 2913 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL 2914 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 2915 u8 g; 2916 u8 num_phases_per_state; 2917 u8 pkts_per_phase; 2918 __le16 init_cr; 2919 __le16 init_tr; 2920 u8 tos_dscp_tos_ecn; 2921 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL 2922 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 2923 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL 2924 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 2925 u8 alt_vlan_pcp; 2926 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL 2927 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 2928 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL 2929 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 2930 __le16 alt_tos_dscp; 2931 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL 2932 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 2933 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL 2934 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 2935 __le16 rtt; 2936 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL 2937 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 2938 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL 2939 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 2940 __le16 tcp_cp; 2941 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL 2942 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 2943 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL 2944 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 2945 u8 cc_mode; 2946 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL 2947 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2948 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 2949 u8 tx_queue; 2950 __le16 inactivity_th; 2951 u8 time_per_phase; 2952 u8 reserved8_1; 2953 __le16 reserved16; 2954 __le32 reserved32; 2955 __le64 reserved64; 2956 }; 2957 2958 /* cmdq_modify_roce_cc_tlv (size:640b/80B) */ 2959 struct cmdq_modify_roce_cc_tlv { 2960 __le16 cmd_discr; 2961 u8 reserved_8b; 2962 u8 tlv_flags; 2963 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL 2964 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2965 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2966 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL 2967 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2968 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2969 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES 2970 __le16 tlv_type; 2971 __le16 length; 2972 u8 total_size; 2973 u8 reserved56[7]; 2974 u8 opcode; 2975 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL 2976 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 2977 u8 cmd_size; 2978 __le16 flags; 2979 __le16 cookie; 2980 u8 resp_size; 2981 u8 reserved8; 2982 __le64 resp_addr; 2983 __le32 modify_mask; 2984 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL 2985 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL 2986 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2987 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL 2988 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL 2989 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL 2990 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL 2991 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2992 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2993 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL 2994 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL 2995 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL 2996 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL 2997 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2998 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2999 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 3000 u8 enable_cc; 3001 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL 3002 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL 3003 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 3004 u8 g; 3005 u8 num_phases_per_state; 3006 u8 pkts_per_phase; 3007 __le16 init_cr; 3008 __le16 init_tr; 3009 u8 tos_dscp_tos_ecn; 3010 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL 3011 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 3012 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL 3013 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 3014 u8 alt_vlan_pcp; 3015 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL 3016 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 3017 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL 3018 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 3019 __le16 alt_tos_dscp; 3020 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL 3021 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 3022 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL 3023 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 3024 __le16 rtt; 3025 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL 3026 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 3027 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL 3028 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 3029 __le16 tcp_cp; 3030 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL 3031 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 3032 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL 3033 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 3034 u8 cc_mode; 3035 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL 3036 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 3037 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 3038 u8 tx_queue; 3039 __le16 inactivity_th; 3040 u8 time_per_phase; 3041 u8 reserved8_1; 3042 __le16 reserved16; 3043 __le32 reserved32; 3044 __le64 reserved64; 3045 __le64 reservedtlvpad; 3046 }; 3047 3048 /* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ 3049 struct cmdq_modify_roce_cc_gen1_tlv { 3050 __le16 cmd_discr; 3051 u8 reserved_8b; 3052 u8 tlv_flags; 3053 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL 3054 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL 3055 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 3056 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL 3057 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 3058 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 3059 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES 3060 __le16 tlv_type; 3061 __le16 length; 3062 __le64 reserved64; 3063 __le64 modify_mask; 3064 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL 3065 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL 3066 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL 3067 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL 3068 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL 3069 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL 3070 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL 3071 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL 3072 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL 3073 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL 3074 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL 3075 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL 3076 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL 3077 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL 3078 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL 3079 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL 3080 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL 3081 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL 3082 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL 3083 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL 3084 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL 3085 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL 3086 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL 3087 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL 3088 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL 3089 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL 3090 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL 3091 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL 3092 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL 3093 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL 3094 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL 3095 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL 3096 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL 3097 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL 3098 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL 3099 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL 3100 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL 3101 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL 3102 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL 3103 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL 3104 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH 0x10000000000ULL 3105 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL 3106 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN 0x40000000000ULL 3107 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL 3108 __le16 inactivity_th_hi; 3109 __le16 min_time_between_cnps; 3110 __le16 init_cp; 3111 u8 tr_update_mode; 3112 u8 tr_update_cycles; 3113 u8 fr_num_rtts; 3114 u8 ai_rate_increase; 3115 __le16 reduction_relax_rtts_th; 3116 __le16 additional_relax_cr_th; 3117 __le16 cr_min_th; 3118 u8 bw_avg_weight; 3119 u8 actual_cr_factor; 3120 __le16 max_cp_cr_th; 3121 u8 cp_bias_en; 3122 u8 cp_bias; 3123 u8 cnp_ecn; 3124 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL 3125 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL 3126 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL 3127 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 3128 u8 rtt_jitter_en; 3129 __le16 link_bytes_per_usec; 3130 __le16 reset_cc_cr_th; 3131 u8 cr_width; 3132 u8 quota_period_min; 3133 u8 quota_period_max; 3134 u8 quota_period_abs_max; 3135 __le16 tr_lower_bound; 3136 u8 cr_prob_factor; 3137 u8 tr_prob_factor; 3138 __le16 fairness_cr_th; 3139 u8 red_div; 3140 u8 cnp_ratio_th; 3141 __le16 exp_ai_rtts; 3142 u8 exp_ai_cr_cp_ratio; 3143 u8 use_rate_table; 3144 __le16 cp_exp_update_th; 3145 __le16 high_exp_ai_rtts_th1; 3146 __le16 high_exp_ai_rtts_th2; 3147 __le16 actual_cr_cong_free_rtts_th; 3148 __le16 severe_cong_cr_th1; 3149 __le16 severe_cong_cr_th2; 3150 __le32 link64B_per_rtt; 3151 u8 cc_ack_bytes; 3152 u8 reduce_init_en; 3153 __le16 reduce_init_cong_free_rtts_th; 3154 u8 random_no_red_en; 3155 u8 actual_cr_shift_correction_en; 3156 u8 quota_period_adjust_en; 3157 u8 reserved[5]; 3158 }; 3159 3160 /* cmdq_modify_roce_cc_gen2_tlv (size:256b/32B) */ 3161 struct cmdq_modify_roce_cc_gen2_tlv { 3162 __le16 cmd_discr; 3163 u8 reserved_8b; 3164 u8 tlv_flags; 3165 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE 0x1UL 3166 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST 0x0UL 3167 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 3168 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED 0x2UL 3169 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 3170 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 3171 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES 3172 __le16 tlv_type; 3173 __le16 length; 3174 __le64 reserved64; 3175 __le64 modify_mask; 3176 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX 0x1UL 3177 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR 0x2UL 3178 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR 0x4UL 3179 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP 0x8UL 3180 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM 0x10UL 3181 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR 0x20UL 3182 u8 dcn_qlevel_tbl_idx; 3183 u8 reserved8; 3184 __le16 dcn_qlevel_tbl_thr; 3185 __le32 dcn_qlevel_tbl_act; 3186 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK 0x3fffUL 3187 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0 3188 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP 0x4000UL 3189 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM 0x8000UL 3190 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK 0x3fff0000UL 3191 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16 3192 }; 3193 3194 /* cmdq_modify_roce_cc_gen1_ext_tlv (size:384b/48B) */ 3195 struct cmdq_modify_roce_cc_gen1_ext_tlv { 3196 __le16 cmd_discr; 3197 u8 reserved_8b; 3198 u8 tlv_flags; 3199 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_MORE 0x1UL 3200 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_MORE_LAST 0x0UL 3201 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 3202 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED 0x2UL 3203 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 3204 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 3205 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_YES 3206 __le16 tlv_type; 3207 __le16 length; 3208 __le64 reserved64; 3209 __le64 modify_mask; 3210 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RND_NO_RED_MULT 0x1UL 3211 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_NO_RED_OFFSET 0x2UL 3212 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_REDUCE2_INIT_CONG_FREE_RTTS_TH 0x4UL 3213 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_REDUCE2_INIT_EN 0x8UL 3214 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_PERIOD_ADJUST_COUNT 0x10UL 3215 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_CURRENT_RATE_THRESHOLD_1 0x20UL 3216 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_CURRENT_RATE_THRESHOLD_2 0x40UL 3217 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RATE_TABLE_IDX 0x80UL 3218 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RATE_TABLE_QUOTA_PERIOD 0x100UL 3219 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RATE_TABLE_BYTE_QUOTA 0x200UL 3220 __le16 rnd_no_red_mult; 3221 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RND_NO_RED_MULT_MASK 0x3ffUL 3222 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RND_NO_RED_MULT_SFT 0 3223 __le16 no_red_offset; 3224 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_NO_RED_OFFSET_MASK 0x7ffUL 3225 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_NO_RED_OFFSET_SFT 0 3226 __le16 reduce2_init_cong_free_rtts_th; 3227 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_MASK 0x3ffUL 3228 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_SFT 0 3229 u8 reduce2_init_en; 3230 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_REDUCE2_INIT_EN 0x1UL 3231 u8 period_adjust_count; 3232 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_PERIOD_ADJUST_COUNT_MASK 0xffUL 3233 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_PERIOD_ADJUST_COUNT_SFT 0 3234 __le16 current_rate_threshold_1; 3235 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_1_MASK 0x3fffUL 3236 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_1_SFT 0 3237 __le16 current_rate_threshold_2; 3238 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_2_MASK 0x3fffUL 3239 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_2_SFT 0 3240 u8 rate_table_idx; 3241 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_IDX_MASK 0xffUL 3242 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_IDX_SFT 0 3243 u8 rate_table_quota_period; 3244 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_QUOTA_PERIOD_MASK 0xffUL 3245 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_QUOTA_PERIOD_SFT 0 3246 __le16 rate_table_byte_quota; 3247 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_BYTE_QUOTA_MASK 0xffffUL 3248 #define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_BYTE_QUOTA_SFT 0 3249 __le64 reserved64_1; 3250 }; 3251 3252 /* cmdq_modify_roce_cc_gen2_ext_tlv (size:384b/48B) */ 3253 struct cmdq_modify_roce_cc_gen2_ext_tlv { 3254 __le16 cmd_discr; 3255 u8 reserved_8b; 3256 u8 tlv_flags; 3257 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_MORE 0x1UL 3258 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_MORE_LAST 0x0UL 3259 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 3260 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED 0x2UL 3261 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 3262 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 3263 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_YES 3264 __le16 tlv_type; 3265 __le16 length; 3266 __le64 reserved64; 3267 __le64 modify_mask; 3268 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_CR2BW_64B_RATIO 0x1UL 3269 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_SR2_CC_FIRST_CNP_EN 0x2UL 3270 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_SR2_CC_ACTUAL_CR_EN 0x4UL 3271 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_RETX_CP 0x8UL 3272 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_RETX_CR 0x10UL 3273 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_RETX_TR 0x20UL 3274 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_HW_RETX_CC_RESET_EN 0x40UL 3275 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_HW_RETX_RESET_CC_CR_TH 0x80UL 3276 __le64 reserved64_1; 3277 __le16 cr2bw_64b_ratio; 3278 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_CR2BW_64B_RATIO_MASK 0x3ffUL 3279 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_CR2BW_64B_RATIO_SFT 0 3280 u8 sr2_cc_first_cnp_en; 3281 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_SR2_CC_FIRST_CNP_EN 0x1UL 3282 u8 sr2_cc_actual_cr_en; 3283 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_SR2_CC_ACTUAL_CR_EN 0x1UL 3284 __le16 retx_cp; 3285 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CP_MASK 0x3ffUL 3286 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CP_SFT 0 3287 __le16 retx_cr; 3288 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CR_MASK 0x3fffUL 3289 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CR_SFT 0 3290 __le16 retx_tr; 3291 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_TR_MASK 0x3fffUL 3292 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_TR_SFT 0 3293 u8 hw_retx_cc_reset_en; 3294 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_ACK_TIMEOUT_EN 0x1UL 3295 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RX_NAK_EN 0x2UL 3296 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RX_RNR_NAK_EN 0x4UL 3297 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MISSING_RESPONSE_EN 0x8UL 3298 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_DUPLICATE_READ_EN 0x10UL 3299 u8 reserved8; 3300 __le16 hw_retx_reset_cc_cr_th; 3301 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_HW_RETX_RESET_CC_CR_TH_MASK 0x3fffUL 3302 #define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_HW_RETX_RESET_CC_CR_TH_SFT 0 3303 __le16 reserved16; 3304 }; 3305 3306 /* creq_modify_roce_cc_resp (size:128b/16B) */ 3307 struct creq_modify_roce_cc_resp { 3308 u8 type; 3309 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 3310 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 3311 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 3312 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 3313 u8 status; 3314 __le16 cookie; 3315 __le32 reserved32; 3316 u8 v; 3317 #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL 3318 u8 event; 3319 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL 3320 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 3321 u8 reserved48[6]; 3322 }; 3323 3324 /* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ 3325 struct cmdq_set_link_aggr_mode_cc { 3326 u8 opcode; 3327 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 3328 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 3329 u8 cmd_size; 3330 __le16 flags; 3331 __le16 cookie; 3332 u8 resp_size; 3333 u8 reserved8; 3334 __le64 resp_addr; 3335 __le32 modify_mask; 3336 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL 3337 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL 3338 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL 3339 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL 3340 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL 3341 u8 aggr_enable; 3342 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL 3343 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL 3344 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 3345 u8 active_port_map; 3346 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL 3347 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 3348 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL 3349 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 3350 u8 member_port_map; 3351 u8 link_aggr_mode; 3352 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL 3353 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL 3354 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL 3355 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL 3356 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 3357 __le16 stat_ctx_id[4]; 3358 __le64 rsvd1; 3359 }; 3360 3361 /* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ 3362 struct creq_set_link_aggr_mode_resources_resp { 3363 u8 type; 3364 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL 3365 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 3366 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL 3367 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 3368 u8 status; 3369 __le16 cookie; 3370 __le32 reserved32; 3371 u8 v; 3372 #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL 3373 u8 event; 3374 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL 3375 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 3376 u8 reserved48[6]; 3377 }; 3378 3379 /* cmdq_allocate_roce_stats_ext_ctx (size:256b/32B) */ 3380 struct cmdq_allocate_roce_stats_ext_ctx { 3381 u8 opcode; 3382 #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX 0x96UL 3383 #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX 3384 u8 cmd_size; 3385 __le16 flags; 3386 #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_FLAGS_PER_FUNC 0x1UL 3387 __le16 cookie; 3388 u8 resp_size; 3389 u8 reserved8; 3390 __le64 resp_addr; 3391 __le64 stats_dma_addr; 3392 __le32 update_period_ms; 3393 __le16 steering_tag; 3394 __le16 reserved16; 3395 }; 3396 3397 /* creq_allocate_roce_stats_ext_ctx_resp (size:128b/16B) */ 3398 struct creq_allocate_roce_stats_ext_ctx_resp { 3399 u8 type; 3400 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK 0x3fUL 3401 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0 3402 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT 0x38UL 3403 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT 3404 u8 status; 3405 __le16 cookie; 3406 __le32 roce_stats_ext_xid; 3407 u8 v; 3408 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V 0x1UL 3409 u8 event; 3410 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX 0x96UL 3411 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX 3412 u8 reserved48[6]; 3413 }; 3414 3415 /* cmdq_deallocate_roce_stats_ext_ctx (size:256b/32B) */ 3416 struct cmdq_deallocate_roce_stats_ext_ctx { 3417 u8 opcode; 3418 #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX 0x97UL 3419 #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX 3420 u8 cmd_size; 3421 __le16 flags; 3422 __le16 cookie; 3423 u8 resp_size; 3424 u8 reserved8; 3425 __le64 resp_addr; 3426 __le32 roce_stats_ext_xid; 3427 __le32 reserved32; 3428 __le64 reserved64; 3429 }; 3430 3431 /* creq_deallocate_roce_stats_ext_ctx_resp (size:128b/16B) */ 3432 struct creq_deallocate_roce_stats_ext_ctx_resp { 3433 u8 type; 3434 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK 0x3fUL 3435 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0 3436 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT 0x38UL 3437 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT 3438 u8 status; 3439 __le16 cookie; 3440 __le32 roce_stats_ext_xid; 3441 u8 v; 3442 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V 0x1UL 3443 u8 event; 3444 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX 0x97UL 3445 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX 3446 u8 reserved48[6]; 3447 }; 3448 3449 /* cmdq_query_roce_stats_ext_v2 (size:256b/32B) */ 3450 struct cmdq_query_roce_stats_ext_v2 { 3451 u8 opcode; 3452 #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 0x98UL 3453 #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 3454 u8 cmd_size; 3455 __le16 flags; 3456 __le16 cookie; 3457 u8 resp_size; 3458 u8 reserved8; 3459 __le64 resp_addr; 3460 __le32 roce_stats_ext_xid; 3461 __le32 reserved32; 3462 __le64 reserved64; 3463 }; 3464 3465 /* creq_query_roce_stats_ext_v2_resp (size:128b/16B) */ 3466 struct creq_query_roce_stats_ext_v2_resp { 3467 u8 type; 3468 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK 0x3fUL 3469 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_SFT 0 3470 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT 0x38UL 3471 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT 3472 u8 status; 3473 __le16 cookie; 3474 __le32 size; 3475 u8 v; 3476 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V 0x1UL 3477 u8 event; 3478 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 0x98UL 3479 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 3480 u8 reserved48[6]; 3481 }; 3482 3483 /* creq_query_roce_stats_ext_v2_resp_sb (size:2304b/288B) */ 3484 struct creq_query_roce_stats_ext_v2_resp_sb { 3485 u8 opcode; 3486 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 0x98UL 3487 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 3488 u8 status; 3489 __le16 cookie; 3490 __le16 flags; 3491 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_TS_VALID 0x1UL 3492 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_RSVD_MASK 0xfffeUL 3493 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_RSVD_SFT 1 3494 u8 resp_size; 3495 u8 offset; 3496 __le64 timestamp; 3497 __le32 rsvd[8]; 3498 __le64 tx_atomic_req_pkts; 3499 __le64 tx_read_req_pkts; 3500 __le64 tx_read_res_pkts; 3501 __le64 tx_write_req_pkts; 3502 __le64 tx_rc_send_req_pkts; 3503 __le64 tx_ud_send_req_pkts; 3504 __le64 tx_cnp_pkts; 3505 __le64 tx_roce_pkts; 3506 __le64 tx_roce_bytes; 3507 __le64 rx_out_of_buffer_pkts; 3508 __le64 rx_out_of_sequence_pkts; 3509 __le64 dup_req; 3510 __le64 missing_resp; 3511 __le64 seq_err_naks_rcvd; 3512 __le64 rnr_naks_rcvd; 3513 __le64 to_retransmits; 3514 __le64 rx_atomic_req_pkts; 3515 __le64 rx_read_req_pkts; 3516 __le64 rx_read_res_pkts; 3517 __le64 rx_write_req_pkts; 3518 __le64 rx_rc_send_pkts; 3519 __le64 rx_ud_send_pkts; 3520 __le64 rx_dcn_payload_cut; 3521 __le64 rx_ecn_marked_pkts; 3522 __le64 rx_cnp_pkts; 3523 __le64 rx_roce_pkts; 3524 __le64 rx_roce_bytes; 3525 __le64 rx_roce_good_pkts; 3526 __le64 rx_roce_good_bytes; 3527 __le64 rx_ack_pkts; 3528 }; 3529 3530 /* cmdq_roce_mirror_cfg (size:192b/24B) */ 3531 struct cmdq_roce_mirror_cfg { 3532 u8 opcode; 3533 #define CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG 0xa6UL 3534 #define CMDQ_ROCE_MIRROR_CFG_OPCODE_LAST CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG 3535 u8 cmd_size; 3536 __le16 flags; 3537 __le16 cookie; 3538 u8 resp_size; 3539 u8 reserved8; 3540 __le64 resp_addr; 3541 u8 mirror_flags; 3542 #define CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE 0x1UL 3543 u8 rsvd[7]; 3544 }; 3545 3546 /* creq_roce_mirror_cfg_resp (size:128b/16B) */ 3547 struct creq_roce_mirror_cfg_resp { 3548 u8 type; 3549 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_MASK 0x3fUL 3550 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_SFT 0 3551 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT 0x38UL 3552 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_LAST CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT 3553 u8 status; 3554 __le16 cookie; 3555 __le32 reserved32; 3556 u8 v; 3557 #define CREQ_ROCE_MIRROR_CFG_RESP_V 0x1UL 3558 u8 event; 3559 #define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG 0xa6UL 3560 #define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_LAST CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG 3561 u8 reserved48[6]; 3562 }; 3563 3564 /* cmdq_roce_cfg (size:192b/24B) */ 3565 struct cmdq_roce_cfg { 3566 u8 opcode; 3567 #define CMDQ_ROCE_CFG_OPCODE_ROCE_CFG 0xa7UL 3568 #define CMDQ_ROCE_CFG_OPCODE_LAST CMDQ_ROCE_CFG_OPCODE_ROCE_CFG 3569 u8 cmd_size; 3570 __le16 flags; 3571 __le16 cookie; 3572 u8 resp_size; 3573 u8 reserved8; 3574 __le64 resp_addr; 3575 __le32 feat_cfg; 3576 #define CMDQ_ROCE_CFG_FEAT_CFG_ICRC_CHECK_DISABLE 0x1UL 3577 #define CMDQ_ROCE_CFG_FEAT_CFG_FORCE_MIRROR_ENABLE 0x2UL 3578 #define CMDQ_ROCE_CFG_FEAT_CFG_RSVD_MASK 0xfffffffcUL 3579 #define CMDQ_ROCE_CFG_FEAT_CFG_RSVD_SFT 2 3580 __le32 feat_enables; 3581 #define CMDQ_ROCE_CFG_FEAT_ENABLES_ICRC_CHECK_DISABLE 0x1UL 3582 #define CMDQ_ROCE_CFG_FEAT_ENABLES_FORCE_MIRROR_ENABLE 0x2UL 3583 #define CMDQ_ROCE_CFG_FEAT_ENABLES_RSVD_MASK 0xfffffffcUL 3584 #define CMDQ_ROCE_CFG_FEAT_ENABLES_RSVD_SFT 2 3585 }; 3586 3587 /* creq_roce_cfg_resp (size:128b/16B) */ 3588 struct creq_roce_cfg_resp { 3589 u8 type; 3590 #define CREQ_ROCE_CFG_RESP_TYPE_MASK 0x3fUL 3591 #define CREQ_ROCE_CFG_RESP_TYPE_SFT 0 3592 #define CREQ_ROCE_CFG_RESP_TYPE_QP_EVENT 0x38UL 3593 #define CREQ_ROCE_CFG_RESP_TYPE_LAST CREQ_ROCE_CFG_RESP_TYPE_QP_EVENT 3594 u8 status; 3595 __le16 cookie; 3596 __le32 reserved04; 3597 u8 v; 3598 #define CREQ_ROCE_CFG_RESP_V 0x1UL 3599 u8 event; 3600 #define CREQ_ROCE_CFG_RESP_EVENT_ROCE_CFG 0xa7UL 3601 #define CREQ_ROCE_CFG_RESP_EVENT_LAST CREQ_ROCE_CFG_RESP_EVENT_ROCE_CFG 3602 __le16 reserved0A; 3603 __le32 feat_cfg_cur; 3604 #define CREQ_ROCE_CFG_RESP_ICRC_CHECK_DISABLED 0x1UL 3605 #define CREQ_ROCE_CFG_RESP_FORCE_MIRROR_ENABLE 0x2UL 3606 #define CREQ_ROCE_CFG_RESP_RSVD_MASK 0xfffffffcUL 3607 #define CREQ_ROCE_CFG_RESP_RSVD_SFT 2 3608 }; 3609 3610 /* creq_func_event (size:128b/16B) */ 3611 struct creq_func_event { 3612 u8 type; 3613 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 3614 #define CREQ_FUNC_EVENT_TYPE_SFT 0 3615 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 3616 #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 3617 u8 reserved56[7]; 3618 u8 v; 3619 #define CREQ_FUNC_EVENT_V 0x1UL 3620 u8 event; 3621 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 3622 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 3623 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 3624 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 3625 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 3626 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 3627 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 3628 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 3629 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 3630 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 3631 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 3632 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 3633 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 3634 #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 3635 u8 reserved48[6]; 3636 }; 3637 3638 /* creq_qp_event (size:128b/16B) */ 3639 struct creq_qp_event { 3640 u8 type; 3641 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 3642 #define CREQ_QP_EVENT_TYPE_SFT 0 3643 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 3644 #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT 3645 u8 status; 3646 #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL 3647 #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL 3648 #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL 3649 #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL 3650 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL 3651 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL 3652 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL 3653 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL 3654 #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 3655 __le16 cookie; 3656 __le32 reserved32; 3657 u8 v; 3658 #define CREQ_QP_EVENT_V 0x1UL 3659 u8 event; 3660 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 3661 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 3662 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 3663 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 3664 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 3665 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 3666 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 3667 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 3668 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 3669 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 3670 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 3671 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 3672 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 3673 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 3674 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 3675 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 3676 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 3677 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 3678 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 3679 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 3680 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 3681 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 3682 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 3683 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 3684 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 3685 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 3686 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 3687 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL 3688 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 3689 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 3690 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 3691 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 3692 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL 3693 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL 3694 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL 3695 #define CREQ_QP_EVENT_EVENT_PNO_STATS_CONFIG 0x99UL 3696 #define CREQ_QP_EVENT_EVENT_PNO_DEBUG_TUNNEL_CONFIG 0x9aUL 3697 #define CREQ_QP_EVENT_EVENT_SET_PNO_FABRIC_NEXTHOP_MAC 0x9bUL 3698 #define CREQ_QP_EVENT_EVENT_PNO_PATH_STRPATH_CONFIG 0x9cUL 3699 #define CREQ_QP_EVENT_EVENT_PNO_PATH_QUERY 0x9dUL 3700 #define CREQ_QP_EVENT_EVENT_PNO_PATH_ACCESS_CONTROL 0x9eUL 3701 #define CREQ_QP_EVENT_EVENT_QUERY_PNO_FABRIC_NEXTHOP_IP 0x9fUL 3702 #define CREQ_QP_EVENT_EVENT_PNO_PATH_PLANE_CONFIG 0xa0UL 3703 #define CREQ_QP_EVENT_EVENT_PNO_TUNNEL_CLOSE 0xa1UL 3704 #define CREQ_QP_EVENT_EVENT_ROCE_MIRROR_CFG 0xa6UL 3705 #define CREQ_QP_EVENT_EVENT_ROCE_CFG 0xa7UL 3706 #define CREQ_QP_EVENT_EVENT_PNO_EV_MONITORING_CONFIG 0xa8UL 3707 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3708 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 3709 #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 3710 u8 reserved48[6]; 3711 }; 3712 3713 /* creq_qp_error_notification (size:128b/16B) */ 3714 struct creq_qp_error_notification { 3715 u8 type; 3716 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 3717 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 3718 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 3719 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 3720 u8 status; 3721 u8 req_slow_path_state; 3722 u8 req_err_state_reason; 3723 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0x0UL 3724 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0x1UL 3725 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0x2UL 3726 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0x3UL 3727 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0x4UL 3728 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0x5UL 3729 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0x6UL 3730 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0x7UL 3731 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0x8UL 3732 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0x9UL 3733 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0xaUL 3734 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0xbUL 3735 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0xcUL 3736 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0xdUL 3737 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0xeUL 3738 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0xfUL 3739 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0x10UL 3740 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0x11UL 3741 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0x12UL 3742 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0x13UL 3743 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0x14UL 3744 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0x15UL 3745 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0x16UL 3746 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0x17UL 3747 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0x18UL 3748 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0x19UL 3749 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0x1aUL 3750 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0x1bUL 3751 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0x1cUL 3752 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW 0x1dUL 3753 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW 3754 __le32 xid; 3755 u8 v; 3756 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 3757 u8 event; 3758 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3759 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 3760 u8 res_slow_path_state; 3761 u8 res_err_state_reason; 3762 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL 3763 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL 3764 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL 3765 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL 3766 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL 3767 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL 3768 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL 3769 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL 3770 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL 3771 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL 3772 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL 3773 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL 3774 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL 3775 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL 3776 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL 3777 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL 3778 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL 3779 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL 3780 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL 3781 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL 3782 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL 3783 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL 3784 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL 3785 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL 3786 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL 3787 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL 3788 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL 3789 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL 3790 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL 3791 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW 0x1eUL 3792 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW 3793 __le16 sq_cons_idx; 3794 __le16 rq_cons_idx; 3795 }; 3796 3797 /* creq_cq_error_notification (size:128b/16B) */ 3798 struct creq_cq_error_notification { 3799 u8 type; 3800 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 3801 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 3802 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL 3803 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 3804 u8 status; 3805 u8 cq_err_reason; 3806 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL 3807 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL 3808 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL 3809 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL 3810 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL 3811 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL 3812 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 3813 u8 reserved8; 3814 __le32 xid; 3815 u8 v; 3816 #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL 3817 u8 event; 3818 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 3819 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 3820 u8 reserved48[6]; 3821 }; 3822 3823 /* sq_base (size:64b/8B) */ 3824 struct sq_base { 3825 u8 wqe_type; 3826 #define SQ_BASE_WQE_TYPE_SEND 0x0UL 3827 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3828 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 3829 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 3830 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3831 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 3832 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 3833 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 3834 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 3835 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 3836 #define SQ_BASE_WQE_TYPE_BIND 0xeUL 3837 #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL 3838 #define SQ_BASE_WQE_TYPE_SEND_V3 0x10UL 3839 #define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3 0x11UL 3840 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3 0x12UL 3841 #define SQ_BASE_WQE_TYPE_UDSEND_V3 0x13UL 3842 #define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3 0x14UL 3843 #define SQ_BASE_WQE_TYPE_WRITE_WQE_V3 0x15UL 3844 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3 0x16UL 3845 #define SQ_BASE_WQE_TYPE_READ_WQE_V3 0x17UL 3846 #define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3 0x18UL 3847 #define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3 0x19UL 3848 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3 0x1aUL 3849 #define SQ_BASE_WQE_TYPE_FR_PMR_V3 0x1bUL 3850 #define SQ_BASE_WQE_TYPE_BIND_V3 0x1cUL 3851 #define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3 0x1dUL 3852 #define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 0x1eUL 3853 #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 3854 u8 unused_0[7]; 3855 }; 3856 3857 /* sq_sge (size:128b/16B) */ 3858 struct sq_sge { 3859 __le64 va_or_pa; 3860 __le32 l_key; 3861 __le32 size; 3862 }; 3863 3864 /* sq_psn_search (size:64b/8B) */ 3865 struct sq_psn_search { 3866 __le32 opcode_start_psn; 3867 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 3868 #define SQ_PSN_SEARCH_START_PSN_SFT 0 3869 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 3870 #define SQ_PSN_SEARCH_OPCODE_SFT 24 3871 __le32 flags_next_psn; 3872 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 3873 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 3874 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 3875 #define SQ_PSN_SEARCH_FLAGS_SFT 24 3876 }; 3877 3878 /* sq_psn_search_ext (size:128b/16B) */ 3879 struct sq_psn_search_ext { 3880 __le32 opcode_start_psn; 3881 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 3882 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 3883 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 3884 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 3885 __le32 flags_next_psn; 3886 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 3887 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 3888 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 3889 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 3890 __le16 start_slot_idx; 3891 __le16 reserved16; 3892 __le32 reserved32; 3893 }; 3894 3895 /* sq_msn_search (size:64b/8B) */ 3896 struct sq_msn_search { 3897 __le64 start_idx_next_psn_start_psn; 3898 #define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL 3899 #define SQ_MSN_SEARCH_START_PSN_SFT 0 3900 #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL 3901 #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24 3902 #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL 3903 #define SQ_MSN_SEARCH_START_IDX_SFT 48 3904 }; 3905 3906 /* sq_send (size:1024b/128B) */ 3907 struct sq_send { 3908 u8 wqe_type; 3909 #define SQ_SEND_WQE_TYPE_SEND 0x0UL 3910 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3911 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 3912 #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID 3913 u8 flags; 3914 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3915 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3916 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 3917 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3918 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 3919 #define SQ_SEND_FLAGS_SE 0x8UL 3920 #define SQ_SEND_FLAGS_INLINE 0x10UL 3921 #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL 3922 #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL 3923 u8 wqe_size; 3924 u8 reserved8_1; 3925 __le32 inv_key_or_imm_data; 3926 __le32 length; 3927 __le32 q_key; 3928 __le32 dst_qp; 3929 #define SQ_SEND_DST_QP_MASK 0xffffffUL 3930 #define SQ_SEND_DST_QP_SFT 0 3931 __le32 avid; 3932 #define SQ_SEND_AVID_MASK 0xfffffUL 3933 #define SQ_SEND_AVID_SFT 0 3934 __le32 reserved32; 3935 __le32 timestamp; 3936 #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL 3937 #define SQ_SEND_TIMESTAMP_SFT 0 3938 __le32 data[24]; 3939 }; 3940 3941 /* sq_send_hdr (size:256b/32B) */ 3942 struct sq_send_hdr { 3943 u8 wqe_type; 3944 #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL 3945 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3946 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL 3947 #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 3948 u8 flags; 3949 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3950 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3951 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3952 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3953 #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL 3954 #define SQ_SEND_HDR_FLAGS_SE 0x8UL 3955 #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL 3956 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL 3957 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3958 u8 wqe_size; 3959 u8 reserved8_1; 3960 __le32 inv_key_or_imm_data; 3961 __le32 length; 3962 __le32 q_key; 3963 __le32 dst_qp; 3964 #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL 3965 #define SQ_SEND_HDR_DST_QP_SFT 0 3966 __le32 avid; 3967 #define SQ_SEND_HDR_AVID_MASK 0xfffffUL 3968 #define SQ_SEND_HDR_AVID_SFT 0 3969 __le32 reserved32; 3970 __le32 timestamp; 3971 #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL 3972 #define SQ_SEND_HDR_TIMESTAMP_SFT 0 3973 }; 3974 3975 /* sq_send_raweth_qp1 (size:1024b/128B) */ 3976 struct sq_send_raweth_qp1 { 3977 u8 wqe_type; 3978 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 3979 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 3980 u8 flags; 3981 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3982 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3983 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 3984 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3985 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 3986 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 3987 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 3988 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL 3989 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL 3990 u8 wqe_size; 3991 u8 reserved8; 3992 __le16 lflags; 3993 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3994 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 3995 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 3996 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 3997 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 3998 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 3999 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 4000 __le16 cfa_action; 4001 __le32 length; 4002 __le32 reserved32_1; 4003 __le32 cfa_meta; 4004 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 4005 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 4006 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 4007 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 4008 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 4009 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 4010 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 4011 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 4012 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 4013 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 4014 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 4015 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 4016 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 4017 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 4018 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 4019 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 4020 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 4021 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 4022 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 4023 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 4024 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 4025 __le32 reserved32_2; 4026 __le32 reserved32_3; 4027 __le32 timestamp; 4028 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL 4029 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 4030 __le32 data[24]; 4031 }; 4032 4033 /* sq_send_raweth_qp1_hdr (size:256b/32B) */ 4034 struct sq_send_raweth_qp1_hdr { 4035 u8 wqe_type; 4036 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL 4037 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 4038 u8 flags; 4039 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4040 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4041 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL 4042 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4043 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL 4044 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL 4045 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL 4046 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL 4047 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL 4048 u8 wqe_size; 4049 u8 reserved8; 4050 __le16 lflags; 4051 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL 4052 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL 4053 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL 4054 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL 4055 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL 4056 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL 4057 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL 4058 __le16 cfa_action; 4059 __le32 length; 4060 __le32 reserved32_1; 4061 __le32 cfa_meta; 4062 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL 4063 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 4064 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL 4065 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL 4066 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 4067 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL 4068 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 4069 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 4070 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 4071 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 4072 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 4073 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 4074 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 4075 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG 4076 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 4077 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 4078 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL 4079 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 4080 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28) 4081 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 4082 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG 4083 __le32 reserved32_2; 4084 __le32 reserved32_3; 4085 __le32 timestamp; 4086 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL 4087 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 4088 }; 4089 4090 /* sq_rdma (size:1024b/128B) */ 4091 struct sq_rdma { 4092 u8 wqe_type; 4093 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 4094 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 4095 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 4096 #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE 4097 u8 flags; 4098 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4099 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4100 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 4101 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4102 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 4103 #define SQ_RDMA_FLAGS_SE 0x8UL 4104 #define SQ_RDMA_FLAGS_INLINE 0x10UL 4105 #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL 4106 #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL 4107 u8 wqe_size; 4108 u8 reserved8; 4109 __le32 imm_data; 4110 __le32 length; 4111 __le32 reserved32_1; 4112 __le64 remote_va; 4113 __le32 remote_key; 4114 __le32 timestamp; 4115 #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL 4116 #define SQ_RDMA_TIMESTAMP_SFT 0 4117 __le32 data[24]; 4118 }; 4119 4120 /* sq_rdma_hdr (size:256b/32B) */ 4121 struct sq_rdma_hdr { 4122 u8 wqe_type; 4123 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL 4124 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 4125 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL 4126 #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE 4127 u8 flags; 4128 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4129 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4130 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL 4131 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4132 #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL 4133 #define SQ_RDMA_HDR_FLAGS_SE 0x8UL 4134 #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL 4135 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL 4136 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL 4137 u8 wqe_size; 4138 u8 reserved8; 4139 __le32 imm_data; 4140 __le32 length; 4141 __le32 reserved32_1; 4142 __le64 remote_va; 4143 __le32 remote_key; 4144 __le32 timestamp; 4145 #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL 4146 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 4147 }; 4148 4149 /* sq_atomic (size:1024b/128B) */ 4150 struct sq_atomic { 4151 u8 wqe_type; 4152 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 4153 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 4154 #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 4155 u8 flags; 4156 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4157 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4158 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 4159 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4160 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 4161 #define SQ_ATOMIC_FLAGS_SE 0x8UL 4162 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 4163 #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL 4164 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL 4165 __le16 reserved16; 4166 __le32 remote_key; 4167 __le64 remote_va; 4168 __le64 swap_data; 4169 __le64 cmp_data; 4170 __le32 data[24]; 4171 }; 4172 4173 /* sq_atomic_hdr (size:256b/32B) */ 4174 struct sq_atomic_hdr { 4175 u8 wqe_type; 4176 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL 4177 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL 4178 #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 4179 u8 flags; 4180 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4181 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4182 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL 4183 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4184 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL 4185 #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL 4186 #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL 4187 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL 4188 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL 4189 __le16 reserved16; 4190 __le32 remote_key; 4191 __le64 remote_va; 4192 __le64 swap_data; 4193 __le64 cmp_data; 4194 }; 4195 4196 /* sq_localinvalidate (size:1024b/128B) */ 4197 struct sq_localinvalidate { 4198 u8 wqe_type; 4199 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 4200 #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 4201 u8 flags; 4202 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4203 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4204 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 4205 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4206 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 4207 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 4208 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 4209 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL 4210 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL 4211 __le16 reserved16; 4212 __le32 inv_l_key; 4213 __le64 reserved64; 4214 u8 reserved128[16]; 4215 __le32 data[24]; 4216 }; 4217 4218 /* sq_localinvalidate_hdr (size:256b/32B) */ 4219 struct sq_localinvalidate_hdr { 4220 u8 wqe_type; 4221 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL 4222 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 4223 u8 flags; 4224 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4225 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4226 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL 4227 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4228 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL 4229 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL 4230 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL 4231 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL 4232 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL 4233 __le16 reserved16; 4234 __le32 inv_l_key; 4235 __le64 reserved64; 4236 u8 reserved128[16]; 4237 }; 4238 4239 /* sq_fr_pmr (size:1024b/128B) */ 4240 struct sq_fr_pmr { 4241 u8 wqe_type; 4242 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 4243 #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR 4244 u8 flags; 4245 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 4246 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4247 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 4248 #define SQ_FR_PMR_FLAGS_SE 0x8UL 4249 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 4250 #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL 4251 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL 4252 u8 access_cntl; 4253 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 4254 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 4255 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 4256 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 4257 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 4258 u8 zero_based_page_size_log; 4259 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 4260 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 4261 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 4262 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 4263 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 4264 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 4265 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 4266 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 4267 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 4268 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 4269 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 4270 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 4271 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 4272 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 4273 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 4274 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 4275 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 4276 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 4277 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 4278 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 4279 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 4280 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 4281 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 4282 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 4283 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 4284 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 4285 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 4286 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 4287 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 4288 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 4289 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 4290 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 4291 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 4292 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 4293 #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 4294 #define SQ_FR_PMR_ZERO_BASED 0x20UL 4295 __le32 l_key; 4296 u8 length[5]; 4297 u8 reserved8_1; 4298 u8 reserved8_2; 4299 u8 numlevels_pbl_page_size_log; 4300 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 4301 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 4302 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 4303 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 4304 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 4305 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 4306 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 4307 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 4308 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 4309 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 4310 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 4311 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 4312 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 4313 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 4314 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 4315 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 4316 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 4317 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 4318 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 4319 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 4320 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 4321 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 4322 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 4323 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 4324 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 4325 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 4326 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 4327 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 4328 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 4329 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 4330 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 4331 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 4332 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 4333 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 4334 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 4335 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 4336 #define SQ_FR_PMR_NUMLEVELS_SFT 6 4337 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 4338 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 4339 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 4340 #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 4341 __le64 pblptr; 4342 __le64 va; 4343 __le32 data[24]; 4344 }; 4345 4346 /* sq_fr_pmr_hdr (size:256b/32B) */ 4347 struct sq_fr_pmr_hdr { 4348 u8 wqe_type; 4349 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL 4350 #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 4351 u8 flags; 4352 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL 4353 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4354 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL 4355 #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL 4356 #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL 4357 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL 4358 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL 4359 u8 access_cntl; 4360 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 4361 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 4362 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 4363 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 4364 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 4365 u8 zero_based_page_size_log; 4366 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL 4367 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 4368 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 4369 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 4370 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 4371 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 4372 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 4373 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 4374 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 4375 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 4376 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 4377 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 4378 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 4379 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 4380 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 4381 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 4382 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 4383 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 4384 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 4385 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 4386 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 4387 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 4388 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 4389 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 4390 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 4391 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 4392 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 4393 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 4394 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 4395 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 4396 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 4397 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 4398 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 4399 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 4400 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 4401 #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL 4402 __le32 l_key; 4403 u8 length[5]; 4404 u8 reserved8_1; 4405 u8 reserved8_2; 4406 u8 numlevels_pbl_page_size_log; 4407 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 4408 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 4409 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 4410 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 4411 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 4412 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 4413 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 4414 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 4415 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 4416 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 4417 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 4418 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 4419 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 4420 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 4421 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 4422 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 4423 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 4424 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 4425 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 4426 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 4427 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 4428 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 4429 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 4430 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 4431 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 4432 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 4433 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 4434 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 4435 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 4436 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 4437 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 4438 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 4439 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 4440 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 4441 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 4442 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL 4443 #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 4444 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6) 4445 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6) 4446 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6) 4447 #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 4448 __le64 pblptr; 4449 __le64 va; 4450 }; 4451 4452 /* sq_bind (size:1024b/128B) */ 4453 struct sq_bind { 4454 u8 wqe_type; 4455 #define SQ_BIND_WQE_TYPE_BIND 0xeUL 4456 #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND 4457 u8 flags; 4458 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4459 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4460 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 4461 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4462 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 4463 #define SQ_BIND_FLAGS_SE 0x8UL 4464 #define SQ_BIND_FLAGS_INLINE 0x10UL 4465 #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL 4466 #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL 4467 u8 access_cntl; 4468 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK 0xffUL 4469 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 4470 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 4471 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 4472 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 4473 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 4474 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 4475 u8 reserved8_1; 4476 u8 mw_type_zero_based; 4477 #define SQ_BIND_ZERO_BASED 0x1UL 4478 #define SQ_BIND_MW_TYPE 0x2UL 4479 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 4480 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 4481 #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 4482 u8 reserved8_2; 4483 __le16 reserved16; 4484 __le32 parent_l_key; 4485 __le32 l_key; 4486 __le64 va; 4487 u8 length[5]; 4488 u8 reserved24[3]; 4489 __le32 data[24]; 4490 }; 4491 4492 /* sq_bind_hdr (size:256b/32B) */ 4493 struct sq_bind_hdr { 4494 u8 wqe_type; 4495 #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL 4496 #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND 4497 u8 flags; 4498 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 4499 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 4500 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL 4501 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4502 #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL 4503 #define SQ_BIND_HDR_FLAGS_SE 0x8UL 4504 #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL 4505 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL 4506 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL 4507 u8 access_cntl; 4508 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK 0xffUL 4509 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 4510 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 4511 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 4512 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 4513 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 4514 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 4515 u8 reserved8_1; 4516 u8 mw_type_zero_based; 4517 #define SQ_BIND_HDR_ZERO_BASED 0x1UL 4518 #define SQ_BIND_HDR_MW_TYPE 0x2UL 4519 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1) 4520 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1) 4521 #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 4522 u8 reserved8_2; 4523 __le16 reserved16; 4524 __le32 parent_l_key; 4525 __le32 l_key; 4526 __le64 va; 4527 u8 length[5]; 4528 u8 reserved24[3]; 4529 }; 4530 4531 /* sq_msn_search_v3 (size:128b/16B) */ 4532 struct sq_msn_search_v3 { 4533 __le64 idx_psn; 4534 #define SQ_MSN_SEARCH_V3_START_PSN_MASK 0xffffffUL 4535 #define SQ_MSN_SEARCH_V3_START_PSN_SFT 0 4536 #define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK 0xffffff000000ULL 4537 #define SQ_MSN_SEARCH_V3_NEXT_PSN_SFT 24 4538 #define SQ_MSN_SEARCH_V3_START_IDX_MASK 0xffff000000000000ULL 4539 #define SQ_MSN_SEARCH_V3_START_IDX_SFT 48 4540 __le32 wqe_opaque; 4541 u8 wqe_size; 4542 u8 signal; 4543 #define SQ_MSN_SEARCH_V3_SGNLD 0x1UL 4544 #define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE 0x2UL 4545 __le16 reserved; 4546 }; 4547 4548 /* sq_send_v3 (size:1024b/128B) */ 4549 struct sq_send_v3 { 4550 u8 wqe_type; 4551 #define SQ_SEND_V3_WQE_TYPE_SEND_V3 0x10UL 4552 #define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3 0x11UL 4553 #define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 0x12UL 4554 #define SQ_SEND_V3_WQE_TYPE_LAST SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 4555 u8 flags; 4556 #define SQ_SEND_V3_FLAGS_SIGNAL_COMP 0x1UL 4557 #define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4558 #define SQ_SEND_V3_FLAGS_UC_FENCE 0x4UL 4559 #define SQ_SEND_V3_FLAGS_SE 0x8UL 4560 #define SQ_SEND_V3_FLAGS_INLINE 0x10UL 4561 #define SQ_SEND_V3_FLAGS_WQE_TS_EN 0x20UL 4562 #define SQ_SEND_V3_FLAGS_DEBUG_TRACE 0x40UL 4563 u8 wqe_size; 4564 #define SQ_SEND_V3_WQE_SIZE_MASK 0x3fUL 4565 #define SQ_SEND_V3_WQE_SIZE_SFT 0 4566 u8 inline_length; 4567 #define SQ_SEND_V3_INLINE_LENGTH_MASK 0xfUL 4568 #define SQ_SEND_V3_INLINE_LENGTH_SFT 0 4569 __le32 opaque; 4570 __le32 inv_key_or_imm_data; 4571 __le32 timestamp; 4572 #define SQ_SEND_V3_TIMESTAMP_MASK 0xffffffUL 4573 #define SQ_SEND_V3_TIMESTAMP_SFT 0 4574 __le32 data[28]; 4575 }; 4576 4577 /* sq_send_hdr_v3 (size:128b/16B) */ 4578 struct sq_send_hdr_v3 { 4579 u8 wqe_type; 4580 #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3 0x10UL 4581 #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3 0x11UL 4582 #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 0x12UL 4583 #define SQ_SEND_HDR_V3_WQE_TYPE_LAST SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 4584 u8 flags; 4585 #define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 4586 #define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4587 #define SQ_SEND_HDR_V3_FLAGS_UC_FENCE 0x4UL 4588 #define SQ_SEND_HDR_V3_FLAGS_SE 0x8UL 4589 #define SQ_SEND_HDR_V3_FLAGS_INLINE 0x10UL 4590 #define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 4591 #define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 4592 u8 wqe_size; 4593 #define SQ_SEND_HDR_V3_WQE_SIZE_MASK 0x3fUL 4594 #define SQ_SEND_HDR_V3_WQE_SIZE_SFT 0 4595 u8 inline_length; 4596 #define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK 0xfUL 4597 #define SQ_SEND_HDR_V3_INLINE_LENGTH_SFT 0 4598 __le32 opaque; 4599 __le32 inv_key_or_imm_data; 4600 __le32 timestamp; 4601 #define SQ_SEND_HDR_V3_TIMESTAMP_MASK 0xffffffUL 4602 #define SQ_SEND_HDR_V3_TIMESTAMP_SFT 0 4603 }; 4604 4605 /* sq_rawqp1send_v3 (size:1024b/128B) */ 4606 struct sq_rawqp1send_v3 { 4607 u8 wqe_type; 4608 #define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 0x1dUL 4609 #define SQ_RAWQP1SEND_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 4610 u8 flags; 4611 #define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP 0x1UL 4612 #define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4613 #define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE 0x4UL 4614 #define SQ_RAWQP1SEND_V3_FLAGS_SE 0x8UL 4615 #define SQ_RAWQP1SEND_V3_FLAGS_INLINE 0x10UL 4616 #define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN 0x20UL 4617 #define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE 0x40UL 4618 u8 wqe_size; 4619 #define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK 0x3fUL 4620 #define SQ_RAWQP1SEND_V3_WQE_SIZE_SFT 0 4621 u8 inline_length; 4622 #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK 0xfUL 4623 #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_SFT 0 4624 __le32 opaque; 4625 __le16 lflags; 4626 #define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM 0x1UL 4627 #define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM 0x2UL 4628 #define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC 0x4UL 4629 #define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM 0x10UL 4630 #define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM 0x20UL 4631 #define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC 0x100UL 4632 #define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC 0x200UL 4633 __le16 cfa_action; 4634 __le16 cfa_action_high; 4635 #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK 0x3ffUL 4636 #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_SFT 0 4637 __le16 reserved_2; 4638 __le32 cfa_meta; 4639 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK 0xfffUL 4640 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_SFT 0 4641 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE 0x1000UL 4642 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK 0xe000UL 4643 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_SFT 13 4644 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK 0x70000UL 4645 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_SFT 16 4646 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 4647 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 4648 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 4649 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 4650 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 4651 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 4652 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG 4653 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 4654 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_SFT 19 4655 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK 0xf0000000UL 4656 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_SFT 28 4657 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE (0x0UL << 28) 4658 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 4659 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG 4660 __le32 timestamp; 4661 #define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK 0xffffffUL 4662 #define SQ_RAWQP1SEND_V3_TIMESTAMP_SFT 0 4663 __le64 reserved_3; 4664 __le32 data[24]; 4665 }; 4666 4667 /* sq_rawqp1send_hdr_v3 (size:256b/32B) */ 4668 struct sq_rawqp1send_hdr_v3 { 4669 u8 wqe_type; 4670 #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 0x1dUL 4671 #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 4672 u8 flags; 4673 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 4674 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4675 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE 0x4UL 4676 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE 0x8UL 4677 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE 0x10UL 4678 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 4679 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 4680 u8 wqe_size; 4681 #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK 0x3fUL 4682 #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_SFT 0 4683 u8 inline_length; 4684 #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK 0xfUL 4685 #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_SFT 0 4686 __le32 opaque; 4687 __le16 lflags; 4688 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM 0x1UL 4689 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM 0x2UL 4690 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC 0x4UL 4691 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM 0x10UL 4692 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM 0x20UL 4693 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC 0x100UL 4694 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC 0x200UL 4695 __le16 cfa_action; 4696 __le16 cfa_action_high; 4697 #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK 0x3ffUL 4698 #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_SFT 0 4699 __le16 reserved_2; 4700 __le32 cfa_meta; 4701 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK 0xfffUL 4702 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_SFT 0 4703 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE 0x1000UL 4704 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK 0xe000UL 4705 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_SFT 13 4706 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK 0x70000UL 4707 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_SFT 16 4708 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 4709 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 4710 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 4711 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 4712 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 4713 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 4714 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG 4715 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 4716 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_SFT 19 4717 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK 0xf0000000UL 4718 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_SFT 28 4719 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE (0x0UL << 28) 4720 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 4721 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG 4722 __le32 timestamp; 4723 #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK 0xffffffUL 4724 #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_SFT 0 4725 __le64 reserved_3; 4726 }; 4727 4728 /* sq_udsend_v3 (size:1024b/128B) */ 4729 struct sq_udsend_v3 { 4730 u8 wqe_type; 4731 #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3 0x13UL 4732 #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 0x14UL 4733 #define SQ_UDSEND_V3_WQE_TYPE_LAST SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 4734 u8 flags; 4735 #define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP 0x1UL 4736 #define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4737 #define SQ_UDSEND_V3_FLAGS_UC_FENCE 0x4UL 4738 #define SQ_UDSEND_V3_FLAGS_SE 0x8UL 4739 #define SQ_UDSEND_V3_FLAGS_INLINE 0x10UL 4740 #define SQ_UDSEND_V3_FLAGS_WQE_TS_EN 0x20UL 4741 #define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE 0x40UL 4742 u8 wqe_size; 4743 #define SQ_UDSEND_V3_WQE_SIZE_MASK 0x3fUL 4744 #define SQ_UDSEND_V3_WQE_SIZE_SFT 0 4745 u8 inline_length; 4746 #define SQ_UDSEND_V3_INLINE_LENGTH_MASK 0xfUL 4747 #define SQ_UDSEND_V3_INLINE_LENGTH_SFT 0 4748 __le32 opaque; 4749 __le32 imm_data; 4750 __le32 q_key; 4751 __le32 dst_qp; 4752 #define SQ_UDSEND_V3_DST_QP_MASK 0xffffffUL 4753 #define SQ_UDSEND_V3_DST_QP_SFT 0 4754 __le32 avid; 4755 #define SQ_UDSEND_V3_AVID_MASK 0xfffffUL 4756 #define SQ_UDSEND_V3_AVID_SFT 0 4757 __le32 reserved2; 4758 __le32 timestamp; 4759 #define SQ_UDSEND_V3_TIMESTAMP_MASK 0xffffffUL 4760 #define SQ_UDSEND_V3_TIMESTAMP_SFT 0 4761 __le32 data[24]; 4762 }; 4763 4764 /* sq_udsend_hdr_v3 (size:256b/32B) */ 4765 struct sq_udsend_hdr_v3 { 4766 u8 wqe_type; 4767 #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3 0x13UL 4768 #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 0x14UL 4769 #define SQ_UDSEND_HDR_V3_WQE_TYPE_LAST SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 4770 u8 flags; 4771 #define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 4772 #define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4773 #define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE 0x4UL 4774 #define SQ_UDSEND_HDR_V3_FLAGS_SE 0x8UL 4775 #define SQ_UDSEND_HDR_V3_FLAGS_INLINE 0x10UL 4776 #define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 4777 #define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 4778 u8 wqe_size; 4779 #define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK 0x3fUL 4780 #define SQ_UDSEND_HDR_V3_WQE_SIZE_SFT 0 4781 u8 inline_length; 4782 #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK 0xfUL 4783 #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_SFT 0 4784 __le32 opaque; 4785 __le32 imm_data; 4786 __le32 q_key; 4787 __le32 dst_qp; 4788 #define SQ_UDSEND_HDR_V3_DST_QP_MASK 0xffffffUL 4789 #define SQ_UDSEND_HDR_V3_DST_QP_SFT 0 4790 __le32 avid; 4791 #define SQ_UDSEND_HDR_V3_AVID_MASK 0xfffffUL 4792 #define SQ_UDSEND_HDR_V3_AVID_SFT 0 4793 __le32 reserved2; 4794 __le32 timestamp; 4795 #define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK 0xffffffUL 4796 #define SQ_UDSEND_HDR_V3_TIMESTAMP_SFT 0 4797 }; 4798 4799 /* sq_rdma_v3 (size:1024b/128B) */ 4800 struct sq_rdma_v3 { 4801 u8 wqe_type; 4802 #define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3 0x15UL 4803 #define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 0x16UL 4804 #define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 0x17UL 4805 #define SQ_RDMA_V3_WQE_TYPE_LAST SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 4806 u8 flags; 4807 #define SQ_RDMA_V3_FLAGS_SIGNAL_COMP 0x1UL 4808 #define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4809 #define SQ_RDMA_V3_FLAGS_UC_FENCE 0x4UL 4810 #define SQ_RDMA_V3_FLAGS_SE 0x8UL 4811 #define SQ_RDMA_V3_FLAGS_INLINE 0x10UL 4812 #define SQ_RDMA_V3_FLAGS_WQE_TS_EN 0x20UL 4813 #define SQ_RDMA_V3_FLAGS_DEBUG_TRACE 0x40UL 4814 u8 wqe_size; 4815 #define SQ_RDMA_V3_WQE_SIZE_MASK 0x3fUL 4816 #define SQ_RDMA_V3_WQE_SIZE_SFT 0 4817 u8 inline_length; 4818 #define SQ_RDMA_V3_INLINE_LENGTH_MASK 0xfUL 4819 #define SQ_RDMA_V3_INLINE_LENGTH_SFT 0 4820 __le32 opaque; 4821 __le32 imm_data; 4822 __le32 reserved2; 4823 __le64 remote_va; 4824 __le32 remote_key; 4825 __le32 timestamp; 4826 #define SQ_RDMA_V3_TIMESTAMP_MASK 0xffffffUL 4827 #define SQ_RDMA_V3_TIMESTAMP_SFT 0 4828 __le32 data[24]; 4829 }; 4830 4831 /* sq_rdma_hdr_v3 (size:256b/32B) */ 4832 struct sq_rdma_hdr_v3 { 4833 u8 wqe_type; 4834 #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3 0x15UL 4835 #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 0x16UL 4836 #define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 0x17UL 4837 #define SQ_RDMA_HDR_V3_WQE_TYPE_LAST SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 4838 u8 flags; 4839 #define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 4840 #define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4841 #define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE 0x4UL 4842 #define SQ_RDMA_HDR_V3_FLAGS_SE 0x8UL 4843 #define SQ_RDMA_HDR_V3_FLAGS_INLINE 0x10UL 4844 #define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 4845 #define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 4846 u8 wqe_size; 4847 #define SQ_RDMA_HDR_V3_WQE_SIZE_MASK 0x3fUL 4848 #define SQ_RDMA_HDR_V3_WQE_SIZE_SFT 0 4849 u8 inline_length; 4850 #define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK 0xfUL 4851 #define SQ_RDMA_HDR_V3_INLINE_LENGTH_SFT 0 4852 __le32 opaque; 4853 __le32 imm_data; 4854 __le32 reserved2; 4855 __le64 remote_va; 4856 __le32 remote_key; 4857 __le32 timestamp; 4858 #define SQ_RDMA_HDR_V3_TIMESTAMP_MASK 0xffffffUL 4859 #define SQ_RDMA_HDR_V3_TIMESTAMP_SFT 0 4860 }; 4861 4862 /* sq_atomic_v3 (size:448b/56B) */ 4863 struct sq_atomic_v3 { 4864 u8 wqe_type; 4865 #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 0x18UL 4866 #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 0x19UL 4867 #define SQ_ATOMIC_V3_WQE_TYPE_LAST SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 4868 u8 flags; 4869 #define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP 0x1UL 4870 #define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4871 #define SQ_ATOMIC_V3_FLAGS_UC_FENCE 0x4UL 4872 #define SQ_ATOMIC_V3_FLAGS_SE 0x8UL 4873 #define SQ_ATOMIC_V3_FLAGS_INLINE 0x10UL 4874 #define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN 0x20UL 4875 #define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE 0x40UL 4876 u8 wqe_size; 4877 #define SQ_ATOMIC_V3_WQE_SIZE_MASK 0x3fUL 4878 #define SQ_ATOMIC_V3_WQE_SIZE_SFT 0 4879 u8 reserved1; 4880 __le32 opaque; 4881 __le32 remote_key; 4882 __le32 reserved2; 4883 __le64 remote_va; 4884 __le64 swap_data; 4885 __le64 cmp_data; 4886 __le64 va_or_pa; 4887 __le32 l_key; 4888 __le32 size; 4889 }; 4890 4891 /* sq_atomic_hdr_v3 (size:320b/40B) */ 4892 struct sq_atomic_hdr_v3 { 4893 u8 wqe_type; 4894 #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 0x18UL 4895 #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 0x19UL 4896 #define SQ_ATOMIC_HDR_V3_WQE_TYPE_LAST SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 4897 u8 flags; 4898 #define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 4899 #define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4900 #define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE 0x4UL 4901 #define SQ_ATOMIC_HDR_V3_FLAGS_SE 0x8UL 4902 #define SQ_ATOMIC_HDR_V3_FLAGS_INLINE 0x10UL 4903 #define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 4904 #define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 4905 u8 wqe_size; 4906 #define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK 0x3fUL 4907 #define SQ_ATOMIC_HDR_V3_WQE_SIZE_SFT 0 4908 u8 reserved1; 4909 __le32 opaque; 4910 __le32 remote_key; 4911 __le32 reserved2; 4912 __le64 remote_va; 4913 __le64 swap_data; 4914 __le64 cmp_data; 4915 }; 4916 4917 /* sq_localinvalidate_v3 (size:128b/16B) */ 4918 struct sq_localinvalidate_v3 { 4919 u8 wqe_type; 4920 #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 0x1aUL 4921 #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 4922 u8 flags; 4923 #define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP 0x1UL 4924 #define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4925 #define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE 0x4UL 4926 #define SQ_LOCALINVALIDATE_V3_FLAGS_SE 0x8UL 4927 #define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE 0x10UL 4928 #define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN 0x20UL 4929 #define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE 0x40UL 4930 u8 wqe_size; 4931 #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK 0x3fUL 4932 #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_SFT 0 4933 u8 reserved1; 4934 __le32 opaque; 4935 __le32 inv_l_key; 4936 __le32 reserved2; 4937 }; 4938 4939 /* sq_localinvalidate_hdr_v3 (size:128b/16B) */ 4940 struct sq_localinvalidate_hdr_v3 { 4941 u8 wqe_type; 4942 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 0x1aUL 4943 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 4944 u8 flags; 4945 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 4946 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4947 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE 0x4UL 4948 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE 0x8UL 4949 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE 0x10UL 4950 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 4951 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 4952 u8 wqe_size; 4953 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK 0x3fUL 4954 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_SFT 0 4955 u8 reserved1; 4956 __le32 opaque; 4957 __le32 inv_l_key; 4958 __le32 reserved2; 4959 }; 4960 4961 /* sq_fr_pmr_v3 (size:320b/40B) */ 4962 struct sq_fr_pmr_v3 { 4963 u8 wqe_type; 4964 #define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 0x1bUL 4965 #define SQ_FR_PMR_V3_WQE_TYPE_LAST SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 4966 u8 flags; 4967 #define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP 0x1UL 4968 #define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 4969 #define SQ_FR_PMR_V3_FLAGS_UC_FENCE 0x4UL 4970 #define SQ_FR_PMR_V3_FLAGS_SE 0x8UL 4971 #define SQ_FR_PMR_V3_FLAGS_INLINE 0x10UL 4972 #define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN 0x20UL 4973 #define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE 0x40UL 4974 u8 wqe_size_zero_based; 4975 #define SQ_FR_PMR_V3_WQE_SIZE_MASK 0x3fUL 4976 #define SQ_FR_PMR_V3_WQE_SIZE_SFT 0 4977 #define SQ_FR_PMR_V3_ZERO_BASED 0x40UL 4978 u8 access_cntl; 4979 #define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL 4980 #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ 0x2UL 4981 #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL 4982 #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 4983 #define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL 4984 __le32 opaque; 4985 __le32 l_key; 4986 __le16 page_size_log; 4987 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK 0x1fUL 4988 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_SFT 0 4989 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 4990 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 4991 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 4992 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 4993 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 4994 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 4995 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 4996 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 4997 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 4998 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 4999 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 5000 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 5001 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 5002 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 5003 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 5004 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 5005 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 5006 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 5007 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 5008 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 5009 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 5010 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 5011 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 5012 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 5013 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 5014 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 5015 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 5016 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 5017 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 5018 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 5019 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 5020 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 5021 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T 5022 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK 0x3e0UL 5023 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_SFT 5 5024 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (0x0UL << 5) 5025 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (0x1UL << 5) 5026 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (0x2UL << 5) 5027 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (0x3UL << 5) 5028 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (0x4UL << 5) 5029 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (0x5UL << 5) 5030 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (0x6UL << 5) 5031 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (0x7UL << 5) 5032 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (0x8UL << 5) 5033 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (0x9UL << 5) 5034 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (0xaUL << 5) 5035 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (0xbUL << 5) 5036 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (0xcUL << 5) 5037 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (0xdUL << 5) 5038 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (0xeUL << 5) 5039 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (0xfUL << 5) 5040 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (0x10UL << 5) 5041 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (0x11UL << 5) 5042 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (0x12UL << 5) 5043 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (0x13UL << 5) 5044 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (0x14UL << 5) 5045 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (0x15UL << 5) 5046 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (0x16UL << 5) 5047 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (0x17UL << 5) 5048 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (0x18UL << 5) 5049 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (0x19UL << 5) 5050 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (0x1aUL << 5) 5051 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (0x1bUL << 5) 5052 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (0x1cUL << 5) 5053 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (0x1dUL << 5) 5054 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (0x1eUL << 5) 5055 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (0x1fUL << 5) 5056 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T 5057 #define SQ_FR_PMR_V3_NUMLEVELS_MASK 0xc00UL 5058 #define SQ_FR_PMR_V3_NUMLEVELS_SFT 10 5059 #define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL (0x0UL << 10) 5060 #define SQ_FR_PMR_V3_NUMLEVELS_LAYER1 (0x1UL << 10) 5061 #define SQ_FR_PMR_V3_NUMLEVELS_LAYER2 (0x2UL << 10) 5062 #define SQ_FR_PMR_V3_NUMLEVELS_LAST SQ_FR_PMR_V3_NUMLEVELS_LAYER2 5063 __le16 reserved; 5064 __le64 va; 5065 __le64 length; 5066 __le64 pbl_ptr; 5067 }; 5068 5069 /* sq_fr_pmr_hdr_v3 (size:320b/40B) */ 5070 struct sq_fr_pmr_hdr_v3 { 5071 u8 wqe_type; 5072 #define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 0x1bUL 5073 #define SQ_FR_PMR_HDR_V3_WQE_TYPE_LAST SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 5074 u8 flags; 5075 #define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 5076 #define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 5077 #define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE 0x4UL 5078 #define SQ_FR_PMR_HDR_V3_FLAGS_SE 0x8UL 5079 #define SQ_FR_PMR_HDR_V3_FLAGS_INLINE 0x10UL 5080 #define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 5081 #define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 5082 u8 wqe_size_zero_based; 5083 #define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK 0x3fUL 5084 #define SQ_FR_PMR_HDR_V3_WQE_SIZE_SFT 0 5085 #define SQ_FR_PMR_HDR_V3_ZERO_BASED 0x40UL 5086 u8 access_cntl; 5087 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL 5088 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ 0x2UL 5089 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL 5090 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 5091 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL 5092 __le32 opaque; 5093 __le32 l_key; 5094 __le16 page_size_log; 5095 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK 0x1fUL 5096 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_SFT 0 5097 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 5098 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 5099 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 5100 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 5101 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 5102 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 5103 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 5104 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 5105 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 5106 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 5107 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 5108 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 5109 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 5110 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 5111 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 5112 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 5113 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 5114 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 5115 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 5116 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 5117 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 5118 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 5119 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 5120 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 5121 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 5122 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 5123 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 5124 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 5125 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 5126 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 5127 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 5128 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 5129 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T 5130 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK 0x3e0UL 5131 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_SFT 5 5132 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (0x0UL << 5) 5133 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (0x1UL << 5) 5134 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (0x2UL << 5) 5135 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (0x3UL << 5) 5136 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (0x4UL << 5) 5137 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (0x5UL << 5) 5138 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (0x6UL << 5) 5139 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (0x7UL << 5) 5140 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (0x8UL << 5) 5141 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (0x9UL << 5) 5142 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (0xaUL << 5) 5143 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (0xbUL << 5) 5144 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (0xcUL << 5) 5145 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (0xdUL << 5) 5146 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (0xeUL << 5) 5147 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (0xfUL << 5) 5148 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (0x10UL << 5) 5149 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (0x11UL << 5) 5150 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (0x12UL << 5) 5151 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (0x13UL << 5) 5152 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (0x14UL << 5) 5153 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (0x15UL << 5) 5154 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (0x16UL << 5) 5155 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (0x17UL << 5) 5156 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (0x18UL << 5) 5157 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (0x19UL << 5) 5158 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (0x1aUL << 5) 5159 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (0x1bUL << 5) 5160 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (0x1cUL << 5) 5161 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (0x1dUL << 5) 5162 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (0x1eUL << 5) 5163 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (0x1fUL << 5) 5164 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T 5165 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK 0xc00UL 5166 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_SFT 10 5167 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL (0x0UL << 10) 5168 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1 (0x1UL << 10) 5169 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 (0x2UL << 10) 5170 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAST SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 5171 __le16 reserved; 5172 __le64 va; 5173 __le64 length; 5174 __le64 pbl_ptr; 5175 }; 5176 5177 /* sq_bind_v3 (size:256b/32B) */ 5178 struct sq_bind_v3 { 5179 u8 wqe_type; 5180 #define SQ_BIND_V3_WQE_TYPE_BIND_V3 0x1cUL 5181 #define SQ_BIND_V3_WQE_TYPE_LAST SQ_BIND_V3_WQE_TYPE_BIND_V3 5182 u8 flags; 5183 #define SQ_BIND_V3_FLAGS_SIGNAL_COMP 0x1UL 5184 #define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 5185 #define SQ_BIND_V3_FLAGS_UC_FENCE 0x4UL 5186 #define SQ_BIND_V3_FLAGS_SE 0x8UL 5187 #define SQ_BIND_V3_FLAGS_INLINE 0x10UL 5188 #define SQ_BIND_V3_FLAGS_WQE_TS_EN 0x20UL 5189 #define SQ_BIND_V3_FLAGS_DEBUG_TRACE 0x40UL 5190 u8 wqe_size_zero_based_mw_type; 5191 #define SQ_BIND_V3_WQE_SIZE_MASK 0x3fUL 5192 #define SQ_BIND_V3_WQE_SIZE_SFT 0 5193 #define SQ_BIND_V3_ZERO_BASED 0x40UL 5194 #define SQ_BIND_V3_MW_TYPE 0x80UL 5195 #define SQ_BIND_V3__TYPE1 (0x0UL << 7) 5196 #define SQ_BIND_V3__TYPE2 (0x1UL << 7) 5197 #define SQ_BIND_V3__LAST SQ_BIND_V3__TYPE2 5198 u8 access_cntl; 5199 #define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL 5200 #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ 0x2UL 5201 #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL 5202 #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 5203 #define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL 5204 __le32 opaque; 5205 __le32 parent_l_key; 5206 __le32 l_key; 5207 __le64 va; 5208 __le64 length; 5209 }; 5210 5211 /* sq_bind_hdr_v3 (size:256b/32B) */ 5212 struct sq_bind_hdr_v3 { 5213 u8 wqe_type; 5214 #define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 0x1cUL 5215 #define SQ_BIND_HDR_V3_WQE_TYPE_LAST SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 5216 u8 flags; 5217 #define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 5218 #define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 5219 #define SQ_BIND_HDR_V3_FLAGS_UC_FENCE 0x4UL 5220 #define SQ_BIND_HDR_V3_FLAGS_SE 0x8UL 5221 #define SQ_BIND_HDR_V3_FLAGS_INLINE 0x10UL 5222 #define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 5223 #define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 5224 u8 wqe_size_zero_based_mw_type; 5225 #define SQ_BIND_HDR_V3_WQE_SIZE_MASK 0x3fUL 5226 #define SQ_BIND_HDR_V3_WQE_SIZE_SFT 0 5227 #define SQ_BIND_HDR_V3_ZERO_BASED 0x40UL 5228 #define SQ_BIND_HDR_V3_MW_TYPE 0x80UL 5229 #define SQ_BIND_HDR_V3__TYPE1 (0x0UL << 7) 5230 #define SQ_BIND_HDR_V3__TYPE2 (0x1UL << 7) 5231 #define SQ_BIND_HDR_V3__LAST SQ_BIND_HDR_V3__TYPE2 5232 u8 access_cntl; 5233 #define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL 5234 #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ 0x2UL 5235 #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL 5236 #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 5237 #define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL 5238 __le32 opaque; 5239 __le32 parent_l_key; 5240 __le32 l_key; 5241 __le64 va; 5242 __le64 length; 5243 }; 5244 5245 /* sq_change_udpsrcport_v3 (size:128b/16B) */ 5246 struct sq_change_udpsrcport_v3 { 5247 u8 wqe_type; 5248 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 0x1eUL 5249 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 5250 u8 flags; 5251 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP 0x1UL 5252 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 5253 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE 0x4UL 5254 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE 0x8UL 5255 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE 0x10UL 5256 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN 0x20UL 5257 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE 0x40UL 5258 u8 wqe_size; 5259 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK 0x3fUL 5260 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_SFT 0 5261 u8 reserved_1; 5262 __le32 opaque; 5263 __le16 udp_src_port; 5264 __le16 reserved_2; 5265 __le32 reserved_3; 5266 }; 5267 5268 /* sq_change_udpsrcport_hdr_v3 (size:128b/16B) */ 5269 struct sq_change_udpsrcport_hdr_v3 { 5270 u8 wqe_type; 5271 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 0x1eUL 5272 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 5273 u8 flags; 5274 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL 5275 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 5276 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE 0x4UL 5277 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE 0x8UL 5278 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE 0x10UL 5279 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN 0x20UL 5280 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL 5281 u8 wqe_size; 5282 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK 0x3fUL 5283 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_SFT 0 5284 u8 reserved_1; 5285 __le32 opaque; 5286 __le16 udp_src_port; 5287 __le16 reserved_2; 5288 __le32 reserved_3; 5289 }; 5290 5291 /* rq_wqe (size:1024b/128B) */ 5292 struct rq_wqe { 5293 u8 wqe_type; 5294 #define RQ_WQE_WQE_TYPE_RCV 0x80UL 5295 #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV 5296 u8 flags; 5297 u8 wqe_size; 5298 u8 reserved8; 5299 __le32 reserved32; 5300 __le32 wr_id[2]; 5301 #define RQ_WQE_WR_ID_MASK 0xfffffUL 5302 #define RQ_WQE_WR_ID_SFT 0 5303 u8 reserved128[16]; 5304 __le32 data[24]; 5305 }; 5306 5307 /* rq_wqe_hdr (size:256b/32B) */ 5308 struct rq_wqe_hdr { 5309 u8 wqe_type; 5310 #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL 5311 #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV 5312 u8 flags; 5313 u8 wqe_size; 5314 u8 reserved8; 5315 __le32 reserved32; 5316 __le32 wr_id[2]; 5317 #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL 5318 #define RQ_WQE_HDR_WR_ID_SFT 0 5319 u8 reserved128[16]; 5320 }; 5321 5322 /* rq_wqe_v3 (size:4096b/512B) */ 5323 struct rq_wqe_v3 { 5324 u8 wqe_type; 5325 #define RQ_WQE_V3_WQE_TYPE_RCV_V3 0x90UL 5326 #define RQ_WQE_V3_WQE_TYPE_LAST RQ_WQE_V3_WQE_TYPE_RCV_V3 5327 u8 flags; 5328 u8 wqe_size; 5329 u8 reserved1; 5330 __le32 opaque; 5331 __le64 reserved2; 5332 __le32 data[124]; 5333 }; 5334 5335 /* rq_wqe_hdr_v3 (size:128b/16B) */ 5336 struct rq_wqe_hdr_v3 { 5337 u8 wqe_type; 5338 #define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 0x90UL 5339 #define RQ_WQE_HDR_V3_WQE_TYPE_LAST RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 5340 u8 flags; 5341 u8 wqe_size; 5342 u8 reserved1; 5343 __le32 opaque; 5344 __le64 reserved2; 5345 }; 5346 5347 /* cq_base (size:256b/32B) */ 5348 struct cq_base { 5349 __le64 reserved64_1; 5350 __le64 reserved64_2; 5351 __le64 reserved64_3; 5352 u8 cqe_type_toggle; 5353 #define CQ_BASE_TOGGLE 0x1UL 5354 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 5355 #define CQ_BASE_CQE_TYPE_SFT 1 5356 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 5357 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 5358 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 5359 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 5360 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 5361 #define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1) 5362 #define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1) 5363 #define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1) 5364 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1) 5365 #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1) 5366 #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1) 5367 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 5368 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 5369 #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF 5370 u8 status; 5371 #define CQ_BASE_STATUS_OK 0x0UL 5372 #define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL 5373 #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL 5374 #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 5375 #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5376 #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL 5377 #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL 5378 #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL 5379 #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL 5380 #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL 5381 #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL 5382 #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL 5383 #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL 5384 #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 5385 #define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL 5386 #define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL 5387 #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR 5388 __le16 reserved16; 5389 __le32 opaque; 5390 }; 5391 5392 /* cq_req (size:256b/32B) */ 5393 struct cq_req { 5394 __le64 qp_handle; 5395 __le16 sq_cons_idx; 5396 __le16 reserved16_1; 5397 __le32 reserved32_2; 5398 __le64 reserved64; 5399 u8 cqe_type_toggle; 5400 #define CQ_REQ_TOGGLE 0x1UL 5401 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 5402 #define CQ_REQ_CQE_TYPE_SFT 1 5403 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 5404 #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ 5405 #define CQ_REQ_PUSH 0x20UL 5406 u8 status; 5407 #define CQ_REQ_STATUS_OK 0x0UL 5408 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 5409 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 5410 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 5411 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 5412 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5413 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 5414 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 5415 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 5416 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 5417 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 5418 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 5419 #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 5420 __le16 reserved16_2; 5421 __le32 reserved32_1; 5422 }; 5423 5424 /* cq_res_rc (size:256b/32B) */ 5425 struct cq_res_rc { 5426 __le32 length; 5427 __le32 imm_data_or_inv_r_key; 5428 __le64 qp_handle; 5429 __le64 mr_handle; 5430 u8 cqe_type_toggle; 5431 #define CQ_RES_RC_TOGGLE 0x1UL 5432 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 5433 #define CQ_RES_RC_CQE_TYPE_SFT 1 5434 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 5435 #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC 5436 u8 status; 5437 #define CQ_RES_RC_STATUS_OK 0x0UL 5438 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5439 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 5440 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5441 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5442 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5443 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 5444 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5445 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 5446 #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR 5447 __le16 flags; 5448 #define CQ_RES_RC_FLAGS_SRQ 0x1UL 5449 #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL 5450 #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL 5451 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 5452 #define CQ_RES_RC_FLAGS_IMM 0x2UL 5453 #define CQ_RES_RC_FLAGS_INV 0x4UL 5454 #define CQ_RES_RC_FLAGS_RDMA 0x8UL 5455 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 5456 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 5457 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 5458 __le32 srq_or_rq_wr_id; 5459 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5460 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 5461 }; 5462 5463 /* cq_res_ud (size:256b/32B) */ 5464 struct cq_res_ud { 5465 __le16 length; 5466 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 5467 #define CQ_RES_UD_LENGTH_SFT 0 5468 __le16 cfa_metadata; 5469 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 5470 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 5471 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 5472 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 5473 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 5474 __le32 imm_data; 5475 __le64 qp_handle; 5476 __le16 src_mac[3]; 5477 __le16 src_qp_low; 5478 u8 cqe_type_toggle; 5479 #define CQ_RES_UD_TOGGLE 0x1UL 5480 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 5481 #define CQ_RES_UD_CQE_TYPE_SFT 1 5482 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 5483 #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD 5484 u8 status; 5485 #define CQ_RES_UD_STATUS_OK 0x0UL 5486 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5487 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 5488 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5489 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5490 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5491 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5492 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 5493 #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR 5494 __le16 flags; 5495 #define CQ_RES_UD_FLAGS_SRQ 0x1UL 5496 #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL 5497 #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL 5498 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 5499 #define CQ_RES_UD_FLAGS_IMM 0x2UL 5500 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 5501 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 5502 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 5503 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 5504 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 5505 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 5506 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 5507 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 5508 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 5509 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 5510 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 5511 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 5512 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 5513 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 5514 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 5515 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 5516 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 5517 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 5518 __le32 src_qp_high_srq_or_rq_wr_id; 5519 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5520 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 5521 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 5522 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 5523 }; 5524 5525 /* cq_res_ud_v2 (size:256b/32B) */ 5526 struct cq_res_ud_v2 { 5527 __le16 length; 5528 #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL 5529 #define CQ_RES_UD_V2_LENGTH_SFT 0 5530 __le16 cfa_metadata0; 5531 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL 5532 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 5533 #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL 5534 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL 5535 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 5536 __le32 imm_data; 5537 __le64 qp_handle; 5538 __le16 src_mac[3]; 5539 __le16 src_qp_low; 5540 u8 cqe_type_toggle; 5541 #define CQ_RES_UD_V2_TOGGLE 0x1UL 5542 #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL 5543 #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 5544 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1) 5545 #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD 5546 u8 status; 5547 #define CQ_RES_UD_V2_STATUS_OK 0x0UL 5548 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5549 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 5550 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5551 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5552 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5553 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5554 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL 5555 #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 5556 __le16 flags; 5557 #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL 5558 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL 5559 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL 5560 #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ 5561 #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL 5562 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL 5563 #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 5564 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 5565 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 5566 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 5567 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 5568 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 5569 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 5570 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 5571 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 5572 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 5573 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 5574 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 5575 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 5576 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 5577 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET 5578 __le32 src_qp_high_srq_or_rq_wr_id; 5579 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5580 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 5581 #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL 5582 #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 5583 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 5584 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 5585 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 5586 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 5587 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 5588 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 5589 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 5590 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 5591 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 5592 #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL 5593 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL 5594 #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 5595 }; 5596 5597 /* cq_res_ud_cfa (size:256b/32B) */ 5598 struct cq_res_ud_cfa { 5599 __le16 length; 5600 #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL 5601 #define CQ_RES_UD_CFA_LENGTH_SFT 0 5602 __le16 cfa_code; 5603 __le32 imm_data; 5604 __le32 qid; 5605 #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL 5606 #define CQ_RES_UD_CFA_QID_SFT 0 5607 __le32 cfa_metadata; 5608 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL 5609 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 5610 #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL 5611 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL 5612 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 5613 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL 5614 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 5615 __le16 src_mac[3]; 5616 __le16 src_qp_low; 5617 u8 cqe_type_toggle; 5618 #define CQ_RES_UD_CFA_TOGGLE 0x1UL 5619 #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL 5620 #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 5621 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 5622 #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA 5623 u8 status; 5624 #define CQ_RES_UD_CFA_STATUS_OK 0x0UL 5625 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5626 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 5627 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5628 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5629 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5630 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5631 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL 5632 #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 5633 __le16 flags; 5634 #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL 5635 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL 5636 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL 5637 #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 5638 #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL 5639 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL 5640 #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 5641 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL 5642 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 5643 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 5644 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 5645 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 5646 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 5647 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL 5648 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 5649 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6) 5650 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 5651 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 5652 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 5653 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 5654 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET 5655 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 5656 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 5657 __le32 src_qp_high_srq_or_rq_wr_id; 5658 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5659 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 5660 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL 5661 #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 5662 }; 5663 5664 /* cq_res_ud_cfa_v2 (size:256b/32B) */ 5665 struct cq_res_ud_cfa_v2 { 5666 __le16 length; 5667 #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL 5668 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 5669 __le16 cfa_metadata0; 5670 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL 5671 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 5672 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL 5673 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL 5674 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 5675 __le32 imm_data; 5676 __le32 qid; 5677 #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL 5678 #define CQ_RES_UD_CFA_V2_QID_SFT 0 5679 __le32 cfa_metadata2; 5680 __le16 src_mac[3]; 5681 __le16 src_qp_low; 5682 u8 cqe_type_toggle; 5683 #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL 5684 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL 5685 #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 5686 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 5687 #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA 5688 u8 status; 5689 #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL 5690 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5691 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 5692 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5693 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5694 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5695 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5696 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL 5697 #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 5698 __le16 flags; 5699 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL 5700 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL 5701 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL 5702 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 5703 #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL 5704 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL 5705 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 5706 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 5707 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 5708 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 5709 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 5710 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 5711 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 5712 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 5713 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 5714 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 5715 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 5716 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 5717 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 5718 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 5719 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET 5720 __le32 src_qp_high_srq_or_rq_wr_id; 5721 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5722 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 5723 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL 5724 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 5725 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 5726 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 5727 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 5728 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 5729 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 5730 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 5731 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 5732 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 5733 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 5734 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL 5735 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL 5736 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 5737 }; 5738 5739 /* cq_res_raweth_qp1 (size:256b/32B) */ 5740 struct cq_res_raweth_qp1 { 5741 __le16 length; 5742 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 5743 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 5744 __le16 raweth_qp1_flags; 5745 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 5746 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 5747 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 5748 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 5749 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 5750 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 5751 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 5752 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 5753 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 5754 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 5755 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 5756 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 5757 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 5758 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 5759 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 5760 __le16 raweth_qp1_errors; 5761 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 5762 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 5763 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 5764 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 5765 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 5766 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 5767 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 5768 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 5769 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 5770 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 5771 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 5772 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 5773 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 5774 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 5775 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 5776 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 5777 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 5778 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 5779 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 5780 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 5781 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 5782 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 5783 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 5784 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 5785 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 5786 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 5787 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 5788 __le16 raweth_qp1_cfa_code; 5789 __le64 qp_handle; 5790 __le32 raweth_qp1_flags2; 5791 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 5792 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 5793 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 5794 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 5795 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 5796 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 5797 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 5798 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4) 5799 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 5800 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 5801 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 5802 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 5803 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 5804 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 5805 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL 5806 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 5807 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 5808 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 5809 __le32 raweth_qp1_metadata; 5810 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL 5811 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 5812 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 5813 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 5814 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 5815 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 5816 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 5817 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 5818 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 5819 u8 cqe_type_toggle; 5820 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 5821 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 5822 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 5823 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 5824 #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 5825 u8 status; 5826 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 5827 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5828 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 5829 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5830 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5831 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5832 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5833 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 5834 #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 5835 __le16 flags; 5836 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 5837 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 5838 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 5839 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 5840 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 5841 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5842 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 5843 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 5844 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 5845 }; 5846 5847 /* cq_res_raweth_qp1_v2 (size:256b/32B) */ 5848 struct cq_res_raweth_qp1_v2 { 5849 __le16 length; 5850 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL 5851 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 5852 __le16 raweth_qp1_flags; 5853 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL 5854 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 5855 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL 5856 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 5857 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 5858 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 5859 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 5860 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 5861 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 5862 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 5863 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 5864 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 5865 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 5866 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 5867 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 5868 __le16 raweth_qp1_errors; 5869 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 5870 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 5871 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 5872 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 5873 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 5874 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 5875 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 5876 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 5877 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 5878 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 5879 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 5880 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 5881 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 5882 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 5883 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 5884 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 5885 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 5886 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 5887 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 5888 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 5889 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 5890 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 5891 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 5892 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 5893 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 5894 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 5895 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 5896 __le16 cfa_metadata0; 5897 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL 5898 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 5899 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL 5900 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL 5901 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 5902 __le64 qp_handle; 5903 __le32 raweth_qp1_flags2; 5904 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL 5905 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 5906 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 5907 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 5908 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4) 5909 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 5910 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 5911 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 5912 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 5913 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 5914 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 5915 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL 5916 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 5917 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 5918 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 5919 __le32 cfa_metadata2; 5920 u8 cqe_type_toggle; 5921 #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL 5922 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL 5923 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 5924 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 5925 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 5926 u8 status; 5927 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL 5928 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 5929 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 5930 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 5931 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 5932 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 5933 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 5934 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL 5935 #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 5936 __le16 flags; 5937 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL 5938 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL 5939 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL 5940 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 5941 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 5942 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 5943 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 5944 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL 5945 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 5946 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 5947 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 5948 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 5949 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 5950 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 5951 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 5952 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 5953 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 5954 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 5955 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL 5956 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 5957 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 5958 }; 5959 5960 /* cq_terminal (size:256b/32B) */ 5961 struct cq_terminal { 5962 __le64 qp_handle; 5963 __le16 sq_cons_idx; 5964 __le16 rq_cons_idx; 5965 __le32 reserved32_1; 5966 __le64 reserved64_3; 5967 u8 cqe_type_toggle; 5968 #define CQ_TERMINAL_TOGGLE 0x1UL 5969 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 5970 #define CQ_TERMINAL_CQE_TYPE_SFT 1 5971 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 5972 #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL 5973 u8 status; 5974 #define CQ_TERMINAL_STATUS_OK 0x0UL 5975 #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK 5976 __le16 reserved16; 5977 __le32 reserved32_2; 5978 }; 5979 5980 /* cq_cutoff (size:256b/32B) */ 5981 struct cq_cutoff { 5982 __le64 reserved64_1; 5983 __le64 reserved64_2; 5984 __le64 reserved64_3; 5985 u8 cqe_type_toggle; 5986 #define CQ_CUTOFF_TOGGLE 0x1UL 5987 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 5988 #define CQ_CUTOFF_CQE_TYPE_SFT 1 5989 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 5990 #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF 5991 #define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL 5992 #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 5993 u8 status; 5994 #define CQ_CUTOFF_STATUS_OK 0x0UL 5995 #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK 5996 __le16 reserved16; 5997 __le32 reserved32; 5998 }; 5999 6000 /* cq_req_v3 (size:256b/32B) */ 6001 struct cq_req_v3 { 6002 __le64 qp_handle; 6003 __le16 sq_cons_idx; 6004 __le16 reserved1; 6005 __le32 reserved2; 6006 __le64 reserved3; 6007 u8 cqe_type_toggle; 6008 #define CQ_REQ_V3_TOGGLE 0x1UL 6009 #define CQ_REQ_V3_CQE_TYPE_MASK 0x1eUL 6010 #define CQ_REQ_V3_CQE_TYPE_SFT 1 6011 #define CQ_REQ_V3_CQE_TYPE_REQ_V3 (0x8UL << 1) 6012 #define CQ_REQ_V3_CQE_TYPE_LAST CQ_REQ_V3_CQE_TYPE_REQ_V3 6013 #define CQ_REQ_V3_PUSH 0x20UL 6014 u8 status; 6015 #define CQ_REQ_V3_STATUS_OK 0x0UL 6016 #define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR 0x1UL 6017 #define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR 0x2UL 6018 #define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 6019 #define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL 6020 #define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL 6021 #define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL 6022 #define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR 0x9UL 6023 #define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR 0xaUL 6024 #define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL 6025 #define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL 6026 #define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 6027 #define CQ_REQ_V3_STATUS_OVERFLOW_ERR 0xfUL 6028 #define CQ_REQ_V3_STATUS_LAST CQ_REQ_V3_STATUS_OVERFLOW_ERR 6029 __le16 reserved4; 6030 __le32 opaque; 6031 }; 6032 6033 /* cq_res_rc_v3 (size:256b/32B) */ 6034 struct cq_res_rc_v3 { 6035 __le32 length; 6036 __le32 imm_data_or_inv_r_key; 6037 __le64 qp_handle; 6038 __le64 mr_handle; 6039 u8 cqe_type_toggle; 6040 #define CQ_RES_RC_V3_TOGGLE 0x1UL 6041 #define CQ_RES_RC_V3_CQE_TYPE_MASK 0x1eUL 6042 #define CQ_RES_RC_V3_CQE_TYPE_SFT 1 6043 #define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 (0x9UL << 1) 6044 #define CQ_RES_RC_V3_CQE_TYPE_LAST CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 6045 u8 status; 6046 #define CQ_RES_RC_V3_STATUS_OK 0x0UL 6047 #define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR 0x2UL 6048 #define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 6049 #define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL 6050 #define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR 0x6UL 6051 #define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL 6052 #define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 6053 #define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR 0xeUL 6054 #define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR 0xfUL 6055 #define CQ_RES_RC_V3_STATUS_LAST CQ_RES_RC_V3_STATUS_OVERFLOW_ERR 6056 __le16 flags; 6057 #define CQ_RES_RC_V3_FLAGS_SRQ 0x1UL 6058 #define CQ_RES_RC_V3_FLAGS_SRQ_RQ 0x0UL 6059 #define CQ_RES_RC_V3_FLAGS_SRQ_SRQ 0x1UL 6060 #define CQ_RES_RC_V3_FLAGS_SRQ_LAST CQ_RES_RC_V3_FLAGS_SRQ_SRQ 6061 #define CQ_RES_RC_V3_FLAGS_IMM 0x2UL 6062 #define CQ_RES_RC_V3_FLAGS_INV 0x4UL 6063 #define CQ_RES_RC_V3_FLAGS_RDMA 0x8UL 6064 #define CQ_RES_RC_V3_FLAGS_RDMA_SEND (0x0UL << 3) 6065 #define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 6066 #define CQ_RES_RC_V3_FLAGS_RDMA_LAST CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE 6067 __le32 opaque; 6068 }; 6069 6070 /* cq_res_ud_v3 (size:256b/32B) */ 6071 struct cq_res_ud_v3 { 6072 __le16 length; 6073 #define CQ_RES_UD_V3_LENGTH_MASK 0x3fffUL 6074 #define CQ_RES_UD_V3_LENGTH_SFT 0 6075 u8 reserved1; 6076 u8 src_qp_high; 6077 __le32 imm_data; 6078 __le64 qp_handle; 6079 __le16 src_mac[3]; 6080 __le16 src_qp_low; 6081 u8 cqe_type_toggle; 6082 #define CQ_RES_UD_V3_TOGGLE 0x1UL 6083 #define CQ_RES_UD_V3_CQE_TYPE_MASK 0x1eUL 6084 #define CQ_RES_UD_V3_CQE_TYPE_SFT 1 6085 #define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 (0xaUL << 1) 6086 #define CQ_RES_UD_V3_CQE_TYPE_LAST CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 6087 u8 status; 6088 #define CQ_RES_UD_V3_STATUS_OK 0x0UL 6089 #define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 6090 #define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 6091 #define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL 6092 #define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 6093 #define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR 0xeUL 6094 #define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR 0xfUL 6095 #define CQ_RES_UD_V3_STATUS_LAST CQ_RES_UD_V3_STATUS_OVERFLOW_ERR 6096 __le16 flags; 6097 #define CQ_RES_UD_V3_FLAGS_SRQ 0x1UL 6098 #define CQ_RES_UD_V3_FLAGS_SRQ_RQ 0x0UL 6099 #define CQ_RES_UD_V3_FLAGS_SRQ_SRQ 0x1UL 6100 #define CQ_RES_UD_V3_FLAGS_SRQ_LAST CQ_RES_UD_V3_FLAGS_SRQ_SRQ 6101 #define CQ_RES_UD_V3_FLAGS_IMM 0x2UL 6102 #define CQ_RES_UD_V3_FLAGS_UNUSED_MASK 0xcUL 6103 #define CQ_RES_UD_V3_FLAGS_UNUSED_SFT 2 6104 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK 0x30UL 6105 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_SFT 4 6106 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 6107 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 6108 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 6109 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 6110 __le32 opaque; 6111 }; 6112 6113 /* cq_res_raweth_qp1_v3 (size:256b/32B) */ 6114 struct cq_res_raweth_qp1_v3 { 6115 __le16 length; 6116 #define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK 0x3fffUL 6117 #define CQ_RES_RAWETH_QP1_V3_LENGTH_SFT 0 6118 __le16 raweth_qp1_flags_cfa_metadata1; 6119 #define CQ_RES_RAWETH_QP1_V3_ERROR 0x1UL 6120 #define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK 0x3c0UL 6121 #define CQ_RES_RAWETH_QP1_V3_ITYPE_SFT 6 6122 #define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN (0x0UL << 6) 6123 #define CQ_RES_RAWETH_QP1_V3_ITYPE_IP (0x1UL << 6) 6124 #define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP (0x2UL << 6) 6125 #define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP (0x3UL << 6) 6126 #define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE (0x4UL << 6) 6127 #define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE (0x5UL << 6) 6128 #define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP (0x7UL << 6) 6129 #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 6130 #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 6131 #define CQ_RES_RAWETH_QP1_V3_ITYPE_LAST CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP 6132 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK 0xf000UL 6133 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_SFT 12 6134 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK 0x7000UL 6135 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_SFT 12 6136 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID 0x8000UL 6137 __le16 raweth_qp1_errors; 6138 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 6139 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 6140 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 6141 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 6142 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 6143 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 6144 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 6145 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 6146 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 6147 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 6148 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x3UL << 9) 6149 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x4UL << 9) 6150 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x5UL << 9) 6151 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (0x6UL << 9) 6152 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR 6153 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 6154 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 6155 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 6156 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 6157 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 6158 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 6159 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 6160 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 6161 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 6162 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 6163 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 6164 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_SUPAR_CRC (0x9UL << 12) 6165 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_SUPAR_CRC 6166 __le16 cfa_metadata0; 6167 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK 0xfffUL 6168 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_SFT 0 6169 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE 0x1000UL 6170 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK 0xe000UL 6171 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_SFT 13 6172 __le64 qp_handle; 6173 __le32 raweth_qp1_flags2; 6174 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 6175 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 6176 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 6177 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 6178 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 6179 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 6180 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 6181 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4) 6182 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 6183 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 6184 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 6185 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_VNIC_ID (0x5UL << 4) 6186 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_VNIC_ID 6187 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 6188 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 6189 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE 0x400UL 6190 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4 (0x0UL << 10) 6191 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 (0x1UL << 10) 6192 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 6193 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 6194 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 6195 __le32 cfa_metadata2; 6196 u8 cqe_type_toggle; 6197 #define CQ_RES_RAWETH_QP1_V3_TOGGLE 0x1UL 6198 #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK 0x1eUL 6199 #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_SFT 1 6200 #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1) 6201 #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 6202 u8 status; 6203 #define CQ_RES_RAWETH_QP1_V3_STATUS_OK 0x0UL 6204 #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 6205 #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 6206 #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL 6207 #define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 6208 #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR 0xeUL 6209 #define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR 0xfUL 6210 #define CQ_RES_RAWETH_QP1_V3_STATUS_LAST CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR 6211 u8 flags; 6212 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ 0x1UL 6213 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ 0x0UL 6214 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ 0x1UL 6215 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ 6216 u8 raweth_qp1_payload_offset; 6217 __le32 opaque; 6218 }; 6219 6220 /* cq_res_ud_cfa_v3 (size:256b/32B) */ 6221 struct cq_res_ud_cfa_v3 { 6222 __le16 length; 6223 #define CQ_RES_UD_CFA_V3_LENGTH_MASK 0x3fffUL 6224 #define CQ_RES_UD_CFA_V3_LENGTH_SFT 0 6225 __le16 cfa_metadata0; 6226 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK 0xfffUL 6227 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_SFT 0 6228 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE 0x1000UL 6229 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK 0xe000UL 6230 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_SFT 13 6231 __le32 imm_data; 6232 __le32 qid_cfa_metadata1_src_qp_high; 6233 #define CQ_RES_UD_CFA_V3_QID_MASK 0x7ffUL 6234 #define CQ_RES_UD_CFA_V3_QID_SFT 0 6235 #define CQ_RES_UD_CFA_V3_UNUSED_MASK 0xff800UL 6236 #define CQ_RES_UD_CFA_V3_UNUSED_SFT 11 6237 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK 0xf00000UL 6238 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_SFT 20 6239 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 6240 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_SFT 20 6241 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID 0x800000UL 6242 #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK 0xff000000UL 6243 #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_SFT 24 6244 __le32 cfa_metadata2; 6245 __le16 src_mac[3]; 6246 __le16 src_qp_low; 6247 u8 cqe_type_toggle; 6248 #define CQ_RES_UD_CFA_V3_TOGGLE 0x1UL 6249 #define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK 0x1eUL 6250 #define CQ_RES_UD_CFA_V3_CQE_TYPE_SFT 1 6251 #define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1) 6252 #define CQ_RES_UD_CFA_V3_CQE_TYPE_LAST CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 6253 u8 status; 6254 #define CQ_RES_UD_CFA_V3_STATUS_OK 0x0UL 6255 #define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 6256 #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 6257 #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL 6258 #define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 6259 #define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR 0xeUL 6260 #define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR 0xfUL 6261 #define CQ_RES_UD_CFA_V3_STATUS_LAST CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR 6262 __le16 flags; 6263 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ 0x1UL 6264 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ 0x0UL 6265 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ 0x1UL 6266 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ 6267 #define CQ_RES_UD_CFA_V3_FLAGS_IMM 0x2UL 6268 #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK 0xcUL 6269 #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_SFT 2 6270 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK 0x30UL 6271 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_SFT 4 6272 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 6273 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 6274 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 6275 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 6276 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK 0x3c0UL 6277 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_SFT 6 6278 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE (0x0UL << 6) 6279 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 6280 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 6281 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 6282 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 6283 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_VNIC_ID (0x5UL << 6) 6284 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_VNIC_ID 6285 __le32 opaque; 6286 }; 6287 6288 /* nq_base (size:128b/16B) */ 6289 struct nq_base { 6290 __le16 info10_type; 6291 #define NQ_BASE_TYPE_MASK 0x3fUL 6292 #define NQ_BASE_TYPE_SFT 0 6293 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 6294 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 6295 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 6296 #define NQ_BASE_TYPE_QP_EVENT 0x38UL 6297 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 6298 #define NQ_BASE_TYPE_NQ_REASSIGN 0x3cUL 6299 #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_NQ_REASSIGN 6300 #define NQ_BASE_INFO10_MASK 0xffc0UL 6301 #define NQ_BASE_INFO10_SFT 6 6302 __le16 info16; 6303 __le32 info32; 6304 __le32 info63_v[2]; 6305 #define NQ_BASE_V 0x1UL 6306 #define NQ_BASE_INFO63_MASK 0xfffffffeUL 6307 #define NQ_BASE_INFO63_SFT 1 6308 }; 6309 6310 /* nq_cn (size:128b/16B) */ 6311 struct nq_cn { 6312 __le16 type; 6313 #define NQ_CN_TYPE_MASK 0x3fUL 6314 #define NQ_CN_TYPE_SFT 0 6315 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 6316 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 6317 #define NQ_CN_TOGGLE_MASK 0xc0UL 6318 #define NQ_CN_TOGGLE_SFT 6 6319 __le16 reserved16; 6320 __le32 cq_handle_low; 6321 __le32 v; 6322 #define NQ_CN_V 0x1UL 6323 __le32 cq_handle_high; 6324 }; 6325 6326 /* nq_srq_event (size:128b/16B) */ 6327 struct nq_srq_event { 6328 u8 type; 6329 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 6330 #define NQ_SRQ_EVENT_TYPE_SFT 0 6331 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 6332 #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT 6333 #define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL 6334 #define NQ_SRQ_EVENT_TOGGLE_SFT 6 6335 u8 event; 6336 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 6337 #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 6338 __le16 reserved16; 6339 __le32 srq_handle_low; 6340 __le32 v; 6341 #define NQ_SRQ_EVENT_V 0x1UL 6342 __le32 srq_handle_high; 6343 }; 6344 6345 /* nq_dbq_event (size:128b/16B) */ 6346 struct nq_dbq_event { 6347 u8 type; 6348 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 6349 #define NQ_DBQ_EVENT_TYPE_SFT 0 6350 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 6351 #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT 6352 u8 event; 6353 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 6354 #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 6355 __le16 db_pfid; 6356 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 6357 #define NQ_DBQ_EVENT_DB_PFID_SFT 0 6358 __le32 db_dpi; 6359 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 6360 #define NQ_DBQ_EVENT_DB_DPI_SFT 0 6361 __le32 v; 6362 #define NQ_DBQ_EVENT_V 0x1UL 6363 __le32 db_type_db_xid; 6364 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 6365 #define NQ_DBQ_EVENT_DB_XID_SFT 0 6366 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 6367 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 6368 }; 6369 6370 /* nq_reassign (size:128b/16B) */ 6371 struct nq_reassign { 6372 __le16 type; 6373 #define NQ_REASSIGN_TYPE_MASK 0x3fUL 6374 #define NQ_REASSIGN_TYPE_SFT 0 6375 #define NQ_REASSIGN_TYPE_NQ_REASSIGN 0x3cUL 6376 #define NQ_REASSIGN_TYPE_LAST NQ_REASSIGN_TYPE_NQ_REASSIGN 6377 __le16 reserved16; 6378 __le32 cq_handle_low; 6379 __le32 v; 6380 #define NQ_REASSIGN_V 0x1UL 6381 __le32 cq_handle_high; 6382 }; 6383 6384 /* xrrq_irrq (size:256b/32B) */ 6385 struct xrrq_irrq { 6386 __le16 credits_type; 6387 #define XRRQ_IRRQ_TYPE 0x1UL 6388 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 6389 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 6390 #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ 6391 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 6392 #define XRRQ_IRRQ_CREDITS_SFT 11 6393 __le16 reserved16; 6394 __le32 reserved32; 6395 __le32 psn; 6396 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 6397 #define XRRQ_IRRQ_PSN_SFT 0 6398 __le32 msn; 6399 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 6400 #define XRRQ_IRRQ_MSN_SFT 0 6401 __le64 va_or_atomic_result; 6402 __le32 rdma_r_key; 6403 __le32 length; 6404 }; 6405 6406 /* xrrq_orrq (size:256b/32B) */ 6407 struct xrrq_orrq { 6408 __le16 num_sges_type; 6409 #define XRRQ_ORRQ_TYPE 0x1UL 6410 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 6411 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 6412 #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ 6413 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 6414 #define XRRQ_ORRQ_NUM_SGES_SFT 11 6415 __le16 reserved16; 6416 __le32 length; 6417 __le32 psn; 6418 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 6419 #define XRRQ_ORRQ_PSN_SFT 0 6420 __le32 end_psn; 6421 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 6422 #define XRRQ_ORRQ_END_PSN_SFT 0 6423 __le64 first_sge_phy_or_sing_sge_va; 6424 __le32 single_sge_l_key; 6425 __le32 single_sge_size; 6426 }; 6427 6428 /* ptu_pte (size:64b/8B) */ 6429 struct ptu_pte { 6430 __le32 page_next_to_last_last_valid[2]; 6431 #define PTU_PTE_VALID 0x1UL 6432 #define PTU_PTE_LAST 0x2UL 6433 #define PTU_PTE_NEXT_TO_LAST 0x4UL 6434 #define PTU_PTE_UNUSED_MASK 0xff8UL 6435 #define PTU_PTE_UNUSED_SFT 3 6436 #define PTU_PTE_PAGE_MASK 0xfffffffffffff000ULL 6437 #define PTU_PTE_PAGE_SFT 12 6438 }; 6439 6440 /* ptu_pde (size:64b/8B) */ 6441 struct ptu_pde { 6442 __le32 page_valid[2]; 6443 #define PTU_PDE_VALID 0x1UL 6444 #define PTU_PDE_UNUSED_MASK 0xffeUL 6445 #define PTU_PDE_UNUSED_SFT 1 6446 #define PTU_PDE_PAGE_MASK 0xfffffffffffff000ULL 6447 #define PTU_PDE_PAGE_SFT 12 6448 }; 6449 6450 #endif /* _BNG_RE_HSI_H_ */ 6451