1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2026 InvenSense, Inc. 4 */ 5 6 #ifndef INV_ICM42607_H_ 7 #define INV_ICM42607_H_ 8 9 #include <linux/bits.h> 10 #include <linux/iio/iio.h> 11 #include <linux/mutex.h> 12 #include <linux/pm.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/time.h> 16 #include <linux/types.h> 17 18 #include <asm/byteorder.h> 19 20 /* 21 * Serial bus slew rates. Rates are expressed as range between the two 22 * values with the midpoint as the typical rate. For the final value of 23 * 2ns, 2ns is considered the max value with no expressed minimum or 24 * typical value. 25 */ 26 enum inv_icm42607_slew_rate { 27 INV_ICM42607_SLEW_RATE_20_60NS = 0, 28 INV_ICM42607_SLEW_RATE_12_36NS = 1, 29 INV_ICM42607_SLEW_RATE_6_19NS = 2, 30 INV_ICM42607_SLEW_RATE_4_14NS = 3, 31 INV_ICM42607_SLEW_RATE_2_6NS = 4, 32 INV_ICM42607_SLEW_RATE_2NS = 5, 33 INV_ICM42607_SLEW_RATE_NB 34 }; 35 36 enum inv_icm42607_sensor_mode { 37 INV_ICM42607_SENSOR_MODE_OFF = 0, 38 INV_ICM42607_SENSOR_MODE_STANDBY = 1, 39 INV_ICM42607_SENSOR_MODE_LOW_POWER = 2, 40 INV_ICM42607_SENSOR_MODE_LOW_NOISE = 3, 41 INV_ICM42607_SENSOR_MODE_NB 42 }; 43 44 /* gyroscope fullscale values */ 45 enum inv_icm42607_gyro_fs { 46 INV_ICM42607_GYRO_FS_2000DPS = 0, 47 INV_ICM42607_GYRO_FS_1000DPS = 1, 48 INV_ICM42607_GYRO_FS_500DPS = 2, 49 INV_ICM42607_GYRO_FS_250DPS = 3, 50 INV_ICM42607_GYRO_FS_NB 51 }; 52 53 /* accelerometer fullscale values */ 54 enum inv_icm42607_accel_fs { 55 INV_ICM42607_ACCEL_FS_16G = 0, 56 INV_ICM42607_ACCEL_FS_8G = 1, 57 INV_ICM42607_ACCEL_FS_4G = 2, 58 INV_ICM42607_ACCEL_FS_2G = 3, 59 INV_ICM42607_ACCEL_FS_NB 60 }; 61 62 /* ODR values - Note Gyro does not support ODR less than 12.5Hz */ 63 enum inv_icm42607_odr { 64 INV_ICM42607_ODR_1600HZ = 5, 65 INV_ICM42607_ODR_800HZ = 6, 66 INV_ICM42607_ODR_400HZ = 7, 67 INV_ICM42607_ODR_200HZ = 8, 68 INV_ICM42607_ODR_100HZ = 9, 69 INV_ICM42607_ODR_50HZ = 10, 70 INV_ICM42607_ODR_25HZ = 11, 71 INV_ICM42607_ODR_12_5HZ = 12, 72 INV_ICM42607_ODR_6_25HZ_LP = 13, 73 INV_ICM42607_ODR_3_125HZ_LP = 14, 74 INV_ICM42607_ODR_1_5625HZ_LP = 15, 75 INV_ICM42607_ODR_NB 76 }; 77 78 /* Low-Noise mode sensor data filter (bandwidth) */ 79 enum inv_icm42607_filter_bw { 80 INV_ICM42607_FILTER_BYPASS = 0, 81 INV_ICM42607_FILTER_BW_180HZ = 1, 82 INV_ICM42607_FILTER_BW_121HZ = 2, 83 INV_ICM42607_FILTER_BW_73HZ = 3, 84 INV_ICM42607_FILTER_BW_53HZ = 4, 85 INV_ICM42607_FILTER_BW_34HZ = 5, 86 INV_ICM42607_FILTER_BW_25HZ = 6, 87 INV_ICM42607_FILTER_BW_16HZ = 7, 88 INV_ICM42607_FILTER_BW_NB 89 }; 90 91 /* Low-Power mode sensor data filter (averaging) */ 92 enum inv_icm42607_filter_avg { 93 INV_ICM42607_FILTER_AVG_2X = 0, 94 INV_ICM42607_FILTER_AVG_4X = 1, 95 INV_ICM42607_FILTER_AVG_8X = 2, 96 INV_ICM42607_FILTER_AVG_16X = 3, 97 INV_ICM42607_FILTER_AVG_32X = 4, 98 INV_ICM42607_FILTER_AVG_64X = 5, 99 /* values 6 and 7 also correspond to 64x. */ 100 }; 101 102 /* Temperature sensor data filter (bandwidth) */ 103 enum inv_icm42607_temp_filter_bw { 104 INV_ICM42607_TEMP_FILTER_BYPASS = 0, 105 INV_ICM42607_TEMP_FILTER_BW_180HZ = 1, 106 INV_ICM42607_TEMP_FILTER_BW_72HZ = 2, 107 INV_ICM42607_TEMP_FILTER_BW_34HZ = 3, 108 INV_ICM42607_TEMP_FILTER_BW_16HZ = 4, 109 INV_ICM42607_TEMP_FILTER_BW_8HZ = 5, 110 INV_ICM42607_TEMP_FILTER_BW_4HZ = 6, 111 /* value 7 also corresponds to 4Hz */ 112 }; 113 114 /* Signed so that negative values can signify an invalid condition. */ 115 struct inv_icm42607_sensor_conf { 116 int mode; 117 int fs; 118 int odr; 119 int filter; 120 }; 121 #define INV_ICM42607_SENSOR_CONF_INIT { -1, -1, -1, -1 } 122 123 struct inv_icm42607_conf { 124 struct inv_icm42607_sensor_conf gyro; 125 struct inv_icm42607_sensor_conf accel; 126 ktime_t gyro_stop; /* earliest time to stop the gyro */ 127 }; 128 129 struct inv_icm42607_hw { 130 const char *name; 131 const struct inv_icm42607_conf *conf; 132 u8 whoami; 133 }; 134 135 /** 136 * struct inv_icm42607_state - driver state variables 137 * @hw: Hardware specific data. 138 * @lock: lock for serializing multiple registers access. 139 * @map: regmap pointer. 140 * @indio_accel: accelerometer IIO device. 141 * @indio_gyro: gyroscope IIO device. 142 * @vddio_supply: I/O voltage regulator for the chip. 143 * @vddio_en: I/O voltage status for runtime PM. 144 * @conf: chip sensors configurations. 145 * @orientation: sensor chip orientation relative to main hardware. 146 */ 147 struct inv_icm42607_state { 148 const struct inv_icm42607_hw *hw; 149 struct mutex lock; 150 struct regmap *map; 151 struct iio_dev *indio_accel; 152 struct iio_dev *indio_gyro; 153 struct regulator *vddio_supply; 154 bool vddio_en; 155 struct inv_icm42607_conf conf; 156 struct iio_mount_matrix orientation; 157 }; 158 159 /** 160 * struct inv_icm42607_sensor_state - sensor state variables 161 * @power_mode: sensor requested power mode (for common frequencies) 162 * @filter: sensor filter. 163 */ 164 struct inv_icm42607_sensor_state { 165 enum inv_icm42607_sensor_mode power_mode; 166 int filter; 167 }; 168 169 /* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */ 170 171 /* Register Map for User Bank 0 */ 172 #define INV_ICM42607_REG_MCLK_RDY 0x00 173 174 #define INV_ICM42607_REG_DEVICE_CONFIG 0x01 175 #define INV_ICM42607_DEVICE_CONFIG_SPI_AP_4WIRE BIT(2) 176 #define INV_ICM42607_DEVICE_CONFIG_SPI_MODE BIT(0) 177 178 #define INV_ICM42607_REG_SIGNAL_PATH_RESET 0x02 179 #define INV_ICM42607_SIGNAL_PATH_RESET_SOFT_RESET BIT(4) 180 #define INV_ICM42607_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(2) 181 182 #define INV_ICM42607_REG_DRIVE_CONFIG1 0x03 183 #define INV_ICM42607_DRIVE_CONFIG1_I3C_DDR_MASK GENMASK(5, 3) 184 #define INV_ICM42607_DRIVE_CONFIG1_I3C_SDR_MASK GENMASK(2, 0) 185 186 #define INV_ICM42607_REG_DRIVE_CONFIG2 0x04 187 #define INV_ICM42607_DRIVE_CONFIG2_I2C_MASK GENMASK(5, 3) 188 #define INV_ICM42607_DRIVE_CONFIG2_ALL_MASK GENMASK(2, 0) 189 190 #define INV_ICM42607_REG_DRIVE_CONFIG3 0x05 191 #define INV_ICM42607_DRIVE_CONFIG3_SPI_MASK GENMASK(2, 0) 192 193 #define INV_ICM42607_REG_INT_CONFIG 0x06 194 #define INV_ICM42607_INT_CONFIG_INT2_LATCHED BIT(5) 195 #define INV_ICM42607_INT_CONFIG_INT2_PUSH_PULL BIT(4) 196 #define INV_ICM42607_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3) 197 #define INV_ICM42607_INT_CONFIG_INT2_ACTIVE_LOW 0x00 198 #define INV_ICM42607_INT_CONFIG_INT1_LATCHED BIT(2) 199 #define INV_ICM42607_INT_CONFIG_INT1_PUSH_PULL BIT(1) 200 #define INV_ICM42607_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0) 201 #define INV_ICM42607_INT_CONFIG_INT1_ACTIVE_LOW 0x00 202 203 /* all sensor data are 16 bits (2 registers wide) in big-endian */ 204 #define INV_ICM42607_REG_TEMP_DATA1 0x09 205 #define INV_ICM42607_REG_TEMP_DATA0 0x0A 206 #define INV_ICM42607_REG_ACCEL_DATA_X1 0x0B 207 #define INV_ICM42607_REG_ACCEL_DATA_X0 0x0C 208 #define INV_ICM42607_REG_ACCEL_DATA_Y1 0x0D 209 #define INV_ICM42607_REG_ACCEL_DATA_Y0 0x0E 210 #define INV_ICM42607_REG_ACCEL_DATA_Z1 0x0F 211 #define INV_ICM42607_REG_ACCEL_DATA_Z0 0x10 212 #define INV_ICM42607_REG_GYRO_DATA_X1 0x11 213 #define INV_ICM42607_REG_GYRO_DATA_X0 0x12 214 #define INV_ICM42607_REG_GYRO_DATA_Y1 0x13 215 #define INV_ICM42607_REG_GYRO_DATA_Y0 0x14 216 #define INV_ICM42607_REG_GYRO_DATA_Z1 0x15 217 #define INV_ICM42607_REG_GYRO_DATA_Z0 0x16 218 #define INV_ICM42607_DATA_INVALID -32768 219 220 #define INV_ICM42607_REG_TMST_FSYNCH 0x17 221 #define INV_ICM42607_REG_TMST_FSYNCL 0x18 222 223 /* APEX Data Registers */ 224 #define INV_ICM42607_REG_APEX_DATA0 0x31 225 #define INV_ICM42607_REG_APEX_DATA1 0x32 226 #define INV_ICM42607_REG_APEX_DATA2 0x33 227 #define INV_ICM42607_REG_APEX_DATA3 0x34 228 #define INV_ICM42607_REG_APEX_DATA4 0x1D 229 #define INV_ICM42607_REG_APEX_DATA5 0x1E 230 231 #define INV_ICM42607_REG_PWR_MGMT0 0x1F 232 #define INV_ICM42607_PWR_MGMT0_ACCEL_LP_CLK_SEL BIT(7) 233 #define INV_ICM42607_PWR_MGMT0_IDLE BIT(4) 234 #define INV_ICM42607_PWR_MGMT0_GYRO_MODE_MASK GENMASK(3, 2) 235 #define INV_ICM42607_PWR_MGMT0_ACCEL_MODE_MASK GENMASK(1, 0) 236 237 #define INV_ICM42607_REG_GYRO_CONFIG0 0x20 238 #define INV_ICM42607_GYRO_CONFIG0_FS_SEL_MASK GENMASK(6, 5) 239 #define INV_ICM42607_GYRO_CONFIG0_ODR_MASK GENMASK(3, 0) 240 241 #define INV_ICM42607_REG_ACCEL_CONFIG0 0x21 242 #define INV_ICM42607_ACCEL_CONFIG0_FS_SEL_MASK GENMASK(6, 5) 243 #define INV_ICM42607_ACCEL_CONFIG0_ODR_MASK GENMASK(3, 0) 244 245 #define INV_ICM42607_REG_TEMP_CONFIG0 0x22 246 #define INV_ICM42607_TEMP_CONFIG0_FILTER_MASK GENMASK(6, 4) 247 248 #define INV_ICM42607_REG_GYRO_CONFIG1 0x23 249 #define INV_ICM42607_GYRO_CONFIG1_FILTER_MASK GENMASK(2, 0) 250 251 #define INV_ICM42607_REG_ACCEL_CONFIG1 0x24 252 #define INV_ICM42607_ACCEL_CONFIG1_AVG_MASK GENMASK(6, 4) 253 #define INV_ICM42607_ACCEL_CONFIG1_FILTER_MASK GENMASK(2, 0) 254 255 #define INV_ICM42607_REG_APEX_CONFIG0 0x25 256 #define INV_ICM42607_APEX_CONFIG0_DMP_POWER_SAVE_EN BIT(3) 257 #define INV_ICM42607_APEX_CONFIG0_DMP_INIT_EN BIT(2) 258 #define INV_ICM42607_APEX_CONFIG0_DMP_MEM_RESET_EN BIT(0) 259 260 #define INV_ICM42607_REG_APEX_CONFIG1 0x26 261 #define INV_ICM42607_APEX_CONFIG1_SMD_ENABLE BIT(6) 262 #define INV_ICM42607_APEX_CONFIG1_FF_ENABLE BIT(5) 263 #define INV_ICM42607_APEX_CONFIG1_TILT_ENABLE BIT(4) 264 #define INV_ICM42607_APEX_CONFIG1_PED_ENABLE BIT(3) 265 #define INV_ICM42607_APEX_CONFIG1_DMP_ODR_MASK GENMASK(1, 0) 266 267 #define INV_ICM42607_REG_WOM_CONFIG 0x27 268 #define INV_ICM42607_WOM_CONFIG_INT_DUR_MASK GENMASK(4, 3) 269 #define INV_ICM42607_WOM_CONFIG_INT_MODE BIT(2) 270 #define INV_ICM42607_WOM_CONFIG_MODE BIT(1) 271 #define INV_ICM42607_WOM_CONFIG_EN BIT(0) 272 273 #define INV_ICM42607_REG_FIFO_CONFIG1 0x28 274 #define INV_ICM42607_FIFO_CONFIG1_MODE BIT(1) 275 #define INV_ICM42607_FIFO_CONFIG1_BYPASS BIT(0) 276 277 #define INV_ICM42607_REG_FIFO_CONFIG2 0x29 278 #define INV_ICM42607_REG_FIFO_CONFIG3 0x2A 279 #define INV_ICM42607_FIFO_WATERMARK_VAL(_wm) \ 280 cpu_to_le16((_wm) & GENMASK(11, 0)) 281 /* FIFO is 2048 bytes, let 12 samples for reading latency */ 282 #define INV_ICM42607_FIFO_WATERMARK_MAX (2048 - 12 * 16) 283 #define INV_ICM42607_FIFO_1SENSOR_PACKET_SIZE 8 284 #define INV_ICM42607_FIFO_2SENSORS_PACKET_SIZE 16 285 286 #define INV_ICM42607_REG_INT_SOURCE0 0x2B 287 #define INV_ICM42607_INT_SOURCE0_ST_INT1_EN BIT(7) 288 #define INV_ICM42607_INT_SOURCE0_FSYNC_INT1_EN BIT(6) 289 #define INV_ICM42607_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5) 290 #define INV_ICM42607_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4) 291 #define INV_ICM42607_INT_SOURCE0_DRDY_INT1_EN BIT(3) 292 #define INV_ICM42607_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2) 293 #define INV_ICM42607_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1) 294 #define INV_ICM42607_INT_SOURCE0_AGC_RDY_INT1_EN BIT(0) 295 296 #define INV_ICM42607_REG_INT_SOURCE1 0x2C 297 #define INV_ICM42607_INT_SOURCE1_I3C_ERROR_INT1_EN BIT(6) 298 #define INV_ICM42607_INT_SOURCE1_SMD_INT1_EN BIT(3) 299 #define INV_ICM42607_INT_SOURCE1_WOM_INT1_EN GENMASK(2, 0) 300 301 #define INV_ICM42607_REG_INT_SOURCE3 0x2D 302 #define INV_ICM42607_INT_SOURCE3_ST_INT2_EN BIT(7) 303 #define INV_ICM42607_INT_SOURCE3_FSYNC_INT2_EN BIT(6) 304 #define INV_ICM42607_INT_SOURCE3_PLL_RDY_INT2_EN BIT(5) 305 #define INV_ICM42607_INT_SOURCE3_RESET_DONE_INT2_EN BIT(4) 306 #define INV_ICM42607_INT_SOURCE3_DRDY_INT2_EN BIT(3) 307 #define INV_ICM42607_INT_SOURCE3_FIFO_THS_INT2_EN BIT(2) 308 #define INV_ICM42607_INT_SOURCE3_FIFO_FULL_INT2_EN BIT(1) 309 #define INV_ICM42607_INT_SOURCE3_AGC_RDY_INT2_EN BIT(0) 310 311 #define INV_ICM42607_REG_INT_SOURCE4 0x2E 312 #define INV_ICM42607_INT_SOURCE4_I3C_ERROR_INT2_EN BIT(6) 313 #define INV_ICM42607_INT_SOURCE4_SMD_INT2_EN BIT(3) 314 #define INV_ICM42607_INT_SOURCE4_WOM_Z_INT2_EN BIT(2) 315 #define INV_ICM42607_INT_SOURCE4_WOM_Y_INT2_EN BIT(1) 316 #define INV_ICM42607_INT_SOURCE4_WOM_X_INT2_EN BIT(0) 317 318 #define INV_ICM42607_REG_FIFO_LOST_PKT0 0x2F 319 #define INV_ICM42607_REG_FIFO_LOST_PKT1 0x30 320 321 #define INV_ICM42607_REG_INTF_CONFIG0 0x35 322 #define INV_ICM42607_INTF_CONFIG0_FIFO_COUNT_FORMAT BIT(6) 323 #define INV_ICM42607_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5) 324 #define INV_ICM42607_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4) 325 #define INV_ICM42607_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0) 326 #define INV_ICM42607_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS 2 327 #define INV_ICM42607_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS 3 328 329 #define INV_ICM42607_REG_INTF_CONFIG1 0x36 330 #define INV_ICM42607_INTF_CONFIG1_I3C_SDR_EN BIT(3) 331 #define INV_ICM42607_INTF_CONFIG1_I3C_DDR_EN BIT(2) 332 #define INV_ICM42607_INTF_CONFIG1_CLKSEL_MASK GENMASK(1, 0) 333 #define INV_ICM42607_INTF_CONFIG1_CLKSEL_INT 0 334 #define INV_ICM42607_INTF_CONFIG1_CLKSEL_PLL 1 335 #define INV_ICM42607_INTF_CONFIG1_CLKSEL_OFF 2 336 337 #define INV_ICM42607_REG_INT_STATUS_DRDY 0x39 338 #define INV_ICM42607_INT_STATUS_DRDY_DATA_RDY BIT(0) 339 340 #define INV_ICM42607_REG_INT_STATUS 0x3A 341 #define INV_ICM42607_INT_STATUS_ST BIT(7) 342 #define INV_ICM42607_INT_STATUS_FSYNC BIT(6) 343 #define INV_ICM42607_INT_STATUS_PLL_RDY BIT(5) 344 #define INV_ICM42607_INT_STATUS_RESET_DONE BIT(4) 345 #define INV_ICM42607_INT_STATUS_FIFO_THS BIT(2) 346 #define INV_ICM42607_INT_STATUS_FIFO_FULL BIT(1) 347 #define INV_ICM42607_INT_STATUS_AGC_RDY BIT(0) 348 349 #define INV_ICM42607_REG_INT_STATUS2 0x3B 350 #define INV_ICM42607_INT_STATUS2_SMD BIT(3) 351 #define INV_ICM42607_INT_STATUS2_WOM_INT GENMASK(2, 0) 352 353 #define INV_ICM42607_REG_INT_STATUS3 0x3C 354 #define INV_ICM42607_INT_STATUS3_STEP_DET BIT(5) 355 #define INV_ICM42607_INT_STATUS3_STEP_CNT_OVF BIT(4) 356 #define INV_ICM42607_INT_STATUS3_TILT_DET BIT(3) 357 #define INV_ICM42607_INT_STATUS3_FF_DET BIT(2) 358 359 /* 360 * FIFO access registers 361 * FIFO count is 16 bits (2 registers) big-endian 362 * FIFO data is a continuous read register to read FIFO content 363 */ 364 #define INV_ICM42607_REG_FIFO_COUNTH 0x3D 365 #define INV_ICM42607_REG_FIFO_COUNTL 0x3E 366 #define INV_ICM42607_REG_FIFO_DATA 0x3F 367 368 #define INV_ICM42607_REG_WHOAMI 0x75 369 #define INV_ICM42607P_WHOAMI 0x60 370 #define INV_ICM42607_WHOAMI 0x67 371 372 /* 373 * Timings as listed in section 3 of datasheet, all values listed in datasheet 374 * in ms except temp startup time... setting all values in us and using 375 * USEC_PER_MSEC to convert from values displayed in datasheet. 376 */ 377 #define INV_ICM42607_POWER_UP_TIME_US (100 * USEC_PER_MSEC) 378 #define INV_ICM42607_RESET_TIME_US (1 * USEC_PER_MSEC) 379 #define INV_ICM42607_ACCEL_STARTUP_TIME_US (10 * USEC_PER_MSEC) 380 #define INV_ICM42607_GYRO_STARTUP_TIME_US (30 * USEC_PER_MSEC) 381 #define INV_ICM42607_GYRO_STOP_TIME_US (45 * USEC_PER_MSEC) 382 #define INV_ICM42607_TEMP_STARTUP_TIME_US 77 383 384 /* 385 * Suspend delay assumed from other icm42600 series device, not 386 * documented in datasheet. 387 */ 388 #define INV_ICM42607_SUSPEND_DELAY_MS (2 * MSEC_PER_SEC) 389 390 typedef int (*inv_icm42607_bus_setup)(struct inv_icm42607_state *); 391 392 extern const struct regmap_config inv_icm42607_regmap_config; 393 extern const struct inv_icm42607_hw inv_icm42607_hw_data; 394 extern const struct inv_icm42607_hw inv_icm42607p_hw_data; 395 extern const struct dev_pm_ops inv_icm42607_pm_ops; 396 397 const struct iio_mount_matrix * 398 inv_icm42607_get_mount_matrix(struct iio_dev *indio_dev, 399 const struct iio_chan_spec *chan); 400 401 int inv_icm42607_get_pwr_mgmt0(struct inv_icm42607_state *st, 402 enum inv_icm42607_sensor_mode *gyro, 403 enum inv_icm42607_sensor_mode *accel); 404 405 int inv_icm42607_set_sensor_conf(struct inv_icm42607_state *st, 406 struct inv_icm42607_sensor_conf *conf, 407 enum iio_chan_type chan_type); 408 409 int inv_icm42607_read_sensor(struct iio_dev *indio_dev, 410 struct iio_chan_spec const *chan, 411 s16 *val); 412 413 int inv_icm42607_core_probe(struct regmap *regmap, 414 const struct inv_icm42607_hw *hw, 415 inv_icm42607_bus_setup bus_setup); 416 417 struct iio_dev *inv_icm42607_gyro_init(struct inv_icm42607_state *st); 418 419 struct iio_dev *inv_icm42607_accel_init(struct inv_icm42607_state *st); 420 421 #endif 422