1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/of_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/math.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/spi/spi.h> 16 #include <linux/module.h> 17 #include <linux/lcm.h> 18 #include <linux/swab.h> 19 #include <linux/crc32.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/imu/adis.h> 24 #include <linux/iio/trigger_consumer.h> 25 26 #include <linux/debugfs.h> 27 28 #define ADIS16480_PAGE_SIZE 0x80 29 30 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 31 32 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 33 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 34 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 35 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 36 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 37 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 38 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 39 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 40 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 41 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 42 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 43 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 44 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 45 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 46 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 47 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 48 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 49 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 50 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 51 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 52 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 53 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 54 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 55 56 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 57 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 58 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 59 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 60 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 61 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 62 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 63 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 64 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 65 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 66 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 67 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 68 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 69 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 70 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 71 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 72 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 73 74 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 75 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 76 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 77 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 78 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 79 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 80 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 81 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 82 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 83 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 84 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 85 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 86 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 87 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 88 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 89 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 90 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 91 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 92 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 93 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 94 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 95 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 96 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 97 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 98 99 /* 100 * External clock scaling in PPS mode. 101 * Available only for ADIS1649x devices 102 */ 103 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 104 #define ADIS16495_REG_BURST_CMD ADIS16480_REG(0x00, 0x7C) 105 #define ADIS16495_BURST_ID 0xA5A5 106 /* total number of segments in burst */ 107 #define ADIS16495_BURST_MAX_DATA 20 108 /* spi max speed in burst mode */ 109 #define ADIS16495_BURST_MAX_SPEED 6000000 110 111 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 112 113 /* Each filter coefficent bank spans two pages */ 114 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 115 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 116 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 117 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 118 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 119 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 120 121 /* ADIS16480_REG_FNCTIO_CTRL */ 122 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 123 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 124 #define ADIS16480_DRDY_POL_MSK BIT(2) 125 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 126 #define ADIS16480_DRDY_EN_MSK BIT(3) 127 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 128 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 129 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 130 #define ADIS16480_SYNC_EN_MSK BIT(7) 131 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 132 #define ADIS16480_SYNC_MODE_MSK BIT(8) 133 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 134 135 struct adis16480_chip_info { 136 unsigned int num_channels; 137 const struct iio_chan_spec *channels; 138 unsigned int gyro_max_val; 139 unsigned int gyro_max_scale; 140 unsigned int accel_max_val; 141 unsigned int accel_max_scale; 142 unsigned int temp_scale; 143 unsigned int int_clk; 144 unsigned int max_dec_rate; 145 const unsigned int *filter_freqs; 146 bool has_pps_clk_mode; 147 const struct adis_data adis_data; 148 }; 149 150 enum adis16480_int_pin { 151 ADIS16480_PIN_DIO1, 152 ADIS16480_PIN_DIO2, 153 ADIS16480_PIN_DIO3, 154 ADIS16480_PIN_DIO4 155 }; 156 157 enum adis16480_clock_mode { 158 ADIS16480_CLK_SYNC, 159 ADIS16480_CLK_PPS, 160 ADIS16480_CLK_INT 161 }; 162 163 struct adis16480 { 164 const struct adis16480_chip_info *chip_info; 165 166 struct adis adis; 167 struct clk *ext_clk; 168 enum adis16480_clock_mode clk_mode; 169 unsigned int clk_freq; 170 /* Alignment needed for the timestamp */ 171 __be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8); 172 }; 173 174 static const char * const adis16480_int_pin_names[4] = { 175 [ADIS16480_PIN_DIO1] = "DIO1", 176 [ADIS16480_PIN_DIO2] = "DIO2", 177 [ADIS16480_PIN_DIO3] = "DIO3", 178 [ADIS16480_PIN_DIO4] = "DIO4", 179 }; 180 181 static bool low_rate_allow; 182 module_param(low_rate_allow, bool, 0444); 183 MODULE_PARM_DESC(low_rate_allow, 184 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)"); 185 186 #ifdef CONFIG_DEBUG_FS 187 188 static ssize_t adis16480_show_firmware_revision(struct file *file, 189 char __user *userbuf, size_t count, loff_t *ppos) 190 { 191 struct adis16480 *adis16480 = file->private_data; 192 char buf[7]; 193 size_t len; 194 u16 rev; 195 int ret; 196 197 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 198 if (ret) 199 return ret; 200 201 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 202 203 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 204 } 205 206 static const struct file_operations adis16480_firmware_revision_fops = { 207 .open = simple_open, 208 .read = adis16480_show_firmware_revision, 209 .llseek = default_llseek, 210 .owner = THIS_MODULE, 211 }; 212 213 static ssize_t adis16480_show_firmware_date(struct file *file, 214 char __user *userbuf, size_t count, loff_t *ppos) 215 { 216 struct adis16480 *adis16480 = file->private_data; 217 u16 md, year; 218 char buf[12]; 219 size_t len; 220 int ret; 221 222 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 223 if (ret) 224 return ret; 225 226 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 227 if (ret) 228 return ret; 229 230 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 231 md >> 8, md & 0xff, year); 232 233 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 234 } 235 236 static const struct file_operations adis16480_firmware_date_fops = { 237 .open = simple_open, 238 .read = adis16480_show_firmware_date, 239 .llseek = default_llseek, 240 .owner = THIS_MODULE, 241 }; 242 243 static int adis16480_show_serial_number(void *arg, u64 *val) 244 { 245 struct adis16480 *adis16480 = arg; 246 u16 serial; 247 int ret; 248 249 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 250 &serial); 251 if (ret) 252 return ret; 253 254 *val = serial; 255 256 return 0; 257 } 258 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 259 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 260 261 static int adis16480_show_product_id(void *arg, u64 *val) 262 { 263 struct adis16480 *adis16480 = arg; 264 u16 prod_id; 265 int ret; 266 267 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 268 &prod_id); 269 if (ret) 270 return ret; 271 272 *val = prod_id; 273 274 return 0; 275 } 276 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 277 adis16480_show_product_id, NULL, "%llu\n"); 278 279 static int adis16480_show_flash_count(void *arg, u64 *val) 280 { 281 struct adis16480 *adis16480 = arg; 282 u32 flash_count; 283 int ret; 284 285 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 286 &flash_count); 287 if (ret) 288 return ret; 289 290 *val = flash_count; 291 292 return 0; 293 } 294 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 295 adis16480_show_flash_count, NULL, "%lld\n"); 296 297 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 298 { 299 struct adis16480 *adis16480 = iio_priv(indio_dev); 300 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 301 302 debugfs_create_file_unsafe("firmware_revision", 0400, 303 d, adis16480, &adis16480_firmware_revision_fops); 304 debugfs_create_file_unsafe("firmware_date", 0400, 305 d, adis16480, &adis16480_firmware_date_fops); 306 debugfs_create_file_unsafe("serial_number", 0400, 307 d, adis16480, &adis16480_serial_number_fops); 308 debugfs_create_file_unsafe("product_id", 0400, 309 d, adis16480, &adis16480_product_id_fops); 310 debugfs_create_file_unsafe("flash_count", 0400, 311 d, adis16480, &adis16480_flash_count_fops); 312 313 return 0; 314 } 315 316 #else 317 318 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 319 { 320 return 0; 321 } 322 323 #endif 324 325 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 326 { 327 struct adis16480 *st = iio_priv(indio_dev); 328 unsigned int t, sample_rate = st->clk_freq; 329 int ret; 330 331 if (val < 0 || val2 < 0) 332 return -EINVAL; 333 334 t = val * 1000 + val2 / 1000; 335 if (t == 0) 336 return -EINVAL; 337 338 adis_dev_lock(&st->adis); 339 /* 340 * When using PPS mode, the input clock needs to be scaled so that we have an IMU 341 * sample rate between (optimally) 4000 and 4250. After this, we can use the 342 * decimation filter to lower the sampling rate in order to get what the user wants. 343 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 344 * the input clock. Hence, calculating the sync_scale dynamically gives us better 345 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 346 * 1. lcm of the input clock and the desired output rate. 347 * 2. get the highest multiple of the previous result lower than the adis max rate. 348 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 349 * and DEC_RATE (to get the user output rate) 350 */ 351 if (st->clk_mode == ADIS16480_CLK_PPS) { 352 unsigned long scaled_rate = lcm(st->clk_freq, t); 353 int sync_scale; 354 355 /* 356 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 357 * solution. In this case, we get the highest multiple of the input clock 358 * lower than the IMU max sample rate. 359 */ 360 if (scaled_rate > st->chip_info->int_clk) 361 scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq; 362 else 363 scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate; 364 365 /* 366 * This is not an hard requirement but it's not advised to run the IMU 367 * with a sample rate lower than 4000Hz due to possible undersampling 368 * issues. However, there are users that might really want to take the risk. 369 * Hence, we provide a module parameter for them. If set, we allow sample 370 * rates lower than 4KHz. By default, we won't allow this and we just roundup 371 * the rate to the next multiple of the input clock bigger than 4KHz. This 372 * is done like this as in some cases (when DEC_RATE is 0) might give 373 * us the closest value to the one desired by the user... 374 */ 375 if (scaled_rate < 4000000 && !low_rate_allow) 376 scaled_rate = roundup(4000000, st->clk_freq); 377 378 sync_scale = scaled_rate / st->clk_freq; 379 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 380 if (ret) 381 goto error; 382 383 sample_rate = scaled_rate; 384 } 385 386 t = DIV_ROUND_CLOSEST(sample_rate, t); 387 if (t) 388 t--; 389 390 if (t > st->chip_info->max_dec_rate) 391 t = st->chip_info->max_dec_rate; 392 393 ret = __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t); 394 error: 395 adis_dev_unlock(&st->adis); 396 return ret; 397 } 398 399 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 400 { 401 struct adis16480 *st = iio_priv(indio_dev); 402 uint16_t t; 403 int ret; 404 unsigned int freq, sample_rate = st->clk_freq; 405 406 adis_dev_lock(&st->adis); 407 408 if (st->clk_mode == ADIS16480_CLK_PPS) { 409 u16 sync_scale; 410 411 ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale); 412 if (ret) 413 goto error; 414 415 sample_rate = st->clk_freq * sync_scale; 416 } 417 418 ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t); 419 if (ret) 420 goto error; 421 422 adis_dev_unlock(&st->adis); 423 424 freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1)); 425 426 *val = freq / 1000; 427 *val2 = (freq % 1000) * 1000; 428 429 return IIO_VAL_INT_PLUS_MICRO; 430 error: 431 adis_dev_unlock(&st->adis); 432 return ret; 433 } 434 435 enum { 436 ADIS16480_SCAN_GYRO_X, 437 ADIS16480_SCAN_GYRO_Y, 438 ADIS16480_SCAN_GYRO_Z, 439 ADIS16480_SCAN_ACCEL_X, 440 ADIS16480_SCAN_ACCEL_Y, 441 ADIS16480_SCAN_ACCEL_Z, 442 ADIS16480_SCAN_MAGN_X, 443 ADIS16480_SCAN_MAGN_Y, 444 ADIS16480_SCAN_MAGN_Z, 445 ADIS16480_SCAN_BARO, 446 ADIS16480_SCAN_TEMP, 447 }; 448 449 static const unsigned int adis16480_calibbias_regs[] = { 450 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 451 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 452 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 453 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 454 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 455 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 456 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 457 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 458 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 459 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 460 }; 461 462 static const unsigned int adis16480_calibscale_regs[] = { 463 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 464 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 465 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 466 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 467 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 468 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 469 }; 470 471 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 472 const struct iio_chan_spec *chan, int bias) 473 { 474 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 475 struct adis16480 *st = iio_priv(indio_dev); 476 477 switch (chan->type) { 478 case IIO_MAGN: 479 case IIO_PRESSURE: 480 if (bias < -0x8000 || bias >= 0x8000) 481 return -EINVAL; 482 return adis_write_reg_16(&st->adis, reg, bias); 483 case IIO_ANGL_VEL: 484 case IIO_ACCEL: 485 return adis_write_reg_32(&st->adis, reg, bias); 486 default: 487 break; 488 } 489 490 return -EINVAL; 491 } 492 493 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 494 const struct iio_chan_spec *chan, int *bias) 495 { 496 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 497 struct adis16480 *st = iio_priv(indio_dev); 498 uint16_t val16; 499 uint32_t val32; 500 int ret; 501 502 switch (chan->type) { 503 case IIO_MAGN: 504 case IIO_PRESSURE: 505 ret = adis_read_reg_16(&st->adis, reg, &val16); 506 if (ret == 0) 507 *bias = sign_extend32(val16, 15); 508 break; 509 case IIO_ANGL_VEL: 510 case IIO_ACCEL: 511 ret = adis_read_reg_32(&st->adis, reg, &val32); 512 if (ret == 0) 513 *bias = sign_extend32(val32, 31); 514 break; 515 default: 516 ret = -EINVAL; 517 } 518 519 if (ret) 520 return ret; 521 522 return IIO_VAL_INT; 523 } 524 525 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 526 const struct iio_chan_spec *chan, int scale) 527 { 528 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 529 struct adis16480 *st = iio_priv(indio_dev); 530 531 if (scale < -0x8000 || scale >= 0x8000) 532 return -EINVAL; 533 534 return adis_write_reg_16(&st->adis, reg, scale); 535 } 536 537 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 538 const struct iio_chan_spec *chan, int *scale) 539 { 540 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 541 struct adis16480 *st = iio_priv(indio_dev); 542 uint16_t val16; 543 int ret; 544 545 ret = adis_read_reg_16(&st->adis, reg, &val16); 546 if (ret) 547 return ret; 548 549 *scale = sign_extend32(val16, 15); 550 return IIO_VAL_INT; 551 } 552 553 static const unsigned int adis16480_def_filter_freqs[] = { 554 310, 555 55, 556 275, 557 63, 558 }; 559 560 static const unsigned int adis16495_def_filter_freqs[] = { 561 300, 562 100, 563 300, 564 100, 565 }; 566 567 static const unsigned int ad16480_filter_data[][2] = { 568 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 569 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 570 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 571 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 572 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 573 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 574 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 575 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 576 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 577 }; 578 579 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 580 const struct iio_chan_spec *chan, int *freq) 581 { 582 struct adis16480 *st = iio_priv(indio_dev); 583 unsigned int enable_mask, offset, reg; 584 uint16_t val; 585 int ret; 586 587 reg = ad16480_filter_data[chan->scan_index][0]; 588 offset = ad16480_filter_data[chan->scan_index][1]; 589 enable_mask = BIT(offset + 2); 590 591 ret = adis_read_reg_16(&st->adis, reg, &val); 592 if (ret) 593 return ret; 594 595 if (!(val & enable_mask)) 596 *freq = 0; 597 else 598 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 599 600 return IIO_VAL_INT; 601 } 602 603 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 604 const struct iio_chan_spec *chan, unsigned int freq) 605 { 606 struct adis16480 *st = iio_priv(indio_dev); 607 unsigned int enable_mask, offset, reg; 608 unsigned int diff, best_diff; 609 unsigned int i, best_freq; 610 uint16_t val; 611 int ret; 612 613 reg = ad16480_filter_data[chan->scan_index][0]; 614 offset = ad16480_filter_data[chan->scan_index][1]; 615 enable_mask = BIT(offset + 2); 616 617 adis_dev_lock(&st->adis); 618 619 ret = __adis_read_reg_16(&st->adis, reg, &val); 620 if (ret) 621 goto out_unlock; 622 623 if (freq == 0) { 624 val &= ~enable_mask; 625 } else { 626 best_freq = 0; 627 best_diff = st->chip_info->filter_freqs[0]; 628 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 629 if (st->chip_info->filter_freqs[i] >= freq) { 630 diff = st->chip_info->filter_freqs[i] - freq; 631 if (diff < best_diff) { 632 best_diff = diff; 633 best_freq = i; 634 } 635 } 636 } 637 638 val &= ~(0x3 << offset); 639 val |= best_freq << offset; 640 val |= enable_mask; 641 } 642 643 ret = __adis_write_reg_16(&st->adis, reg, val); 644 out_unlock: 645 adis_dev_unlock(&st->adis); 646 647 return ret; 648 } 649 650 static int adis16480_read_raw(struct iio_dev *indio_dev, 651 const struct iio_chan_spec *chan, int *val, int *val2, long info) 652 { 653 struct adis16480 *st = iio_priv(indio_dev); 654 unsigned int temp; 655 656 switch (info) { 657 case IIO_CHAN_INFO_RAW: 658 return adis_single_conversion(indio_dev, chan, 0, val); 659 case IIO_CHAN_INFO_SCALE: 660 switch (chan->type) { 661 case IIO_ANGL_VEL: 662 *val = st->chip_info->gyro_max_scale; 663 *val2 = st->chip_info->gyro_max_val; 664 return IIO_VAL_FRACTIONAL; 665 case IIO_ACCEL: 666 *val = st->chip_info->accel_max_scale; 667 *val2 = st->chip_info->accel_max_val; 668 return IIO_VAL_FRACTIONAL; 669 case IIO_MAGN: 670 *val = 0; 671 *val2 = 100; /* 0.0001 gauss */ 672 return IIO_VAL_INT_PLUS_MICRO; 673 case IIO_TEMP: 674 /* 675 * +85 degrees Celsius = temp_max_scale 676 * +25 degrees Celsius = 0 677 * LSB, 25 degrees Celsius = 60 / temp_max_scale 678 */ 679 *val = st->chip_info->temp_scale / 1000; 680 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 681 return IIO_VAL_INT_PLUS_MICRO; 682 case IIO_PRESSURE: 683 /* 684 * max scale is 1310 mbar 685 * max raw value is 32767 shifted for 32bits 686 */ 687 *val = 131; /* 1310mbar = 131 kPa */ 688 *val2 = 32767 << 16; 689 return IIO_VAL_FRACTIONAL; 690 default: 691 return -EINVAL; 692 } 693 case IIO_CHAN_INFO_OFFSET: 694 /* Only the temperature channel has a offset */ 695 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 696 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 697 return IIO_VAL_INT; 698 case IIO_CHAN_INFO_CALIBBIAS: 699 return adis16480_get_calibbias(indio_dev, chan, val); 700 case IIO_CHAN_INFO_CALIBSCALE: 701 return adis16480_get_calibscale(indio_dev, chan, val); 702 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 703 return adis16480_get_filter_freq(indio_dev, chan, val); 704 case IIO_CHAN_INFO_SAMP_FREQ: 705 return adis16480_get_freq(indio_dev, val, val2); 706 default: 707 return -EINVAL; 708 } 709 } 710 711 static int adis16480_write_raw(struct iio_dev *indio_dev, 712 const struct iio_chan_spec *chan, int val, int val2, long info) 713 { 714 switch (info) { 715 case IIO_CHAN_INFO_CALIBBIAS: 716 return adis16480_set_calibbias(indio_dev, chan, val); 717 case IIO_CHAN_INFO_CALIBSCALE: 718 return adis16480_set_calibscale(indio_dev, chan, val); 719 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 720 return adis16480_set_filter_freq(indio_dev, chan, val); 721 case IIO_CHAN_INFO_SAMP_FREQ: 722 return adis16480_set_freq(indio_dev, val, val2); 723 724 default: 725 return -EINVAL; 726 } 727 } 728 729 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 730 { \ 731 .type = (_type), \ 732 .modified = 1, \ 733 .channel2 = (_mod), \ 734 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 735 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 736 _info_sep, \ 737 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 738 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 739 .address = (_address), \ 740 .scan_index = (_si), \ 741 .scan_type = { \ 742 .sign = 's', \ 743 .realbits = (_bits), \ 744 .storagebits = (_bits), \ 745 .endianness = IIO_BE, \ 746 }, \ 747 } 748 749 #define ADIS16480_GYRO_CHANNEL(_mod) \ 750 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 751 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 752 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 753 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 754 32) 755 756 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 757 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 758 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 759 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 760 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 761 32) 762 763 #define ADIS16480_MAGN_CHANNEL(_mod) \ 764 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 765 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 766 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 767 16) 768 769 #define ADIS16480_PRESSURE_CHANNEL() \ 770 { \ 771 .type = IIO_PRESSURE, \ 772 .indexed = 1, \ 773 .channel = 0, \ 774 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 775 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 776 BIT(IIO_CHAN_INFO_SCALE), \ 777 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 778 .address = ADIS16480_REG_BAROM_OUT, \ 779 .scan_index = ADIS16480_SCAN_BARO, \ 780 .scan_type = { \ 781 .sign = 's', \ 782 .realbits = 32, \ 783 .storagebits = 32, \ 784 .endianness = IIO_BE, \ 785 }, \ 786 } 787 788 #define ADIS16480_TEMP_CHANNEL() { \ 789 .type = IIO_TEMP, \ 790 .indexed = 1, \ 791 .channel = 0, \ 792 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 793 BIT(IIO_CHAN_INFO_SCALE) | \ 794 BIT(IIO_CHAN_INFO_OFFSET), \ 795 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 796 .address = ADIS16480_REG_TEMP_OUT, \ 797 .scan_index = ADIS16480_SCAN_TEMP, \ 798 .scan_type = { \ 799 .sign = 's', \ 800 .realbits = 16, \ 801 .storagebits = 16, \ 802 .endianness = IIO_BE, \ 803 }, \ 804 } 805 806 static const struct iio_chan_spec adis16480_channels[] = { 807 ADIS16480_GYRO_CHANNEL(X), 808 ADIS16480_GYRO_CHANNEL(Y), 809 ADIS16480_GYRO_CHANNEL(Z), 810 ADIS16480_ACCEL_CHANNEL(X), 811 ADIS16480_ACCEL_CHANNEL(Y), 812 ADIS16480_ACCEL_CHANNEL(Z), 813 ADIS16480_MAGN_CHANNEL(X), 814 ADIS16480_MAGN_CHANNEL(Y), 815 ADIS16480_MAGN_CHANNEL(Z), 816 ADIS16480_PRESSURE_CHANNEL(), 817 ADIS16480_TEMP_CHANNEL(), 818 IIO_CHAN_SOFT_TIMESTAMP(11) 819 }; 820 821 static const struct iio_chan_spec adis16485_channels[] = { 822 ADIS16480_GYRO_CHANNEL(X), 823 ADIS16480_GYRO_CHANNEL(Y), 824 ADIS16480_GYRO_CHANNEL(Z), 825 ADIS16480_ACCEL_CHANNEL(X), 826 ADIS16480_ACCEL_CHANNEL(Y), 827 ADIS16480_ACCEL_CHANNEL(Z), 828 ADIS16480_TEMP_CHANNEL(), 829 IIO_CHAN_SOFT_TIMESTAMP(7) 830 }; 831 832 enum adis16480_variant { 833 ADIS16375, 834 ADIS16480, 835 ADIS16485, 836 ADIS16488, 837 ADIS16490, 838 ADIS16495_1, 839 ADIS16495_2, 840 ADIS16495_3, 841 ADIS16497_1, 842 ADIS16497_2, 843 ADIS16497_3, 844 }; 845 846 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 847 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 848 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 849 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 850 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 851 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 852 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 853 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 854 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 855 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 856 857 static const char * const adis16480_status_error_msgs[] = { 858 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 859 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 860 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 861 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 862 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 863 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 864 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 865 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 866 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 867 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 868 }; 869 870 static int adis16480_enable_irq(struct adis *adis, bool enable); 871 872 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len) \ 873 { \ 874 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \ 875 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \ 876 .prod_id_reg = ADIS16480_REG_PROD_ID, \ 877 .prod_id = (_prod_id), \ 878 .has_paging = true, \ 879 .read_delay = 5, \ 880 .write_delay = 5, \ 881 .self_test_mask = BIT(1), \ 882 .self_test_reg = ADIS16480_REG_GLOB_CMD, \ 883 .status_error_msgs = adis16480_status_error_msgs, \ 884 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \ 885 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \ 886 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \ 887 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \ 888 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \ 889 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \ 890 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \ 891 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \ 892 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \ 893 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \ 894 .enable_irq = adis16480_enable_irq, \ 895 .timeouts = (_timeouts), \ 896 .burst_reg_cmd = ADIS16495_REG_BURST_CMD, \ 897 .burst_len = (_burst_len), \ 898 .burst_max_speed_hz = ADIS16495_BURST_MAX_SPEED \ 899 } 900 901 static const struct adis_timeout adis16485_timeouts = { 902 .reset_ms = 560, 903 .sw_reset_ms = 120, 904 .self_test_ms = 12, 905 }; 906 907 static const struct adis_timeout adis16480_timeouts = { 908 .reset_ms = 560, 909 .sw_reset_ms = 560, 910 .self_test_ms = 12, 911 }; 912 913 static const struct adis_timeout adis16495_timeouts = { 914 .reset_ms = 170, 915 .sw_reset_ms = 130, 916 .self_test_ms = 40, 917 }; 918 919 static const struct adis_timeout adis16495_1_timeouts = { 920 .reset_ms = 250, 921 .sw_reset_ms = 210, 922 .self_test_ms = 20, 923 }; 924 925 static const struct adis16480_chip_info adis16480_chip_info[] = { 926 [ADIS16375] = { 927 .channels = adis16485_channels, 928 .num_channels = ARRAY_SIZE(adis16485_channels), 929 /* 930 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 931 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 932 * it gives better approximation. However, in this case we 933 * cannot do it since it would not fit in a 32bit variable. 934 */ 935 .gyro_max_val = 22887 << 16, 936 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 937 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 938 .accel_max_scale = 18, 939 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 940 .int_clk = 2460000, 941 .max_dec_rate = 2048, 942 .filter_freqs = adis16480_def_filter_freqs, 943 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0), 944 }, 945 [ADIS16480] = { 946 .channels = adis16480_channels, 947 .num_channels = ARRAY_SIZE(adis16480_channels), 948 .gyro_max_val = 22500 << 16, 949 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 950 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 951 .accel_max_scale = 10, 952 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 953 .int_clk = 2460000, 954 .max_dec_rate = 2048, 955 .filter_freqs = adis16480_def_filter_freqs, 956 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0), 957 }, 958 [ADIS16485] = { 959 .channels = adis16485_channels, 960 .num_channels = ARRAY_SIZE(adis16485_channels), 961 .gyro_max_val = 22500 << 16, 962 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 963 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 964 .accel_max_scale = 5, 965 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 966 .int_clk = 2460000, 967 .max_dec_rate = 2048, 968 .filter_freqs = adis16480_def_filter_freqs, 969 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0), 970 }, 971 [ADIS16488] = { 972 .channels = adis16480_channels, 973 .num_channels = ARRAY_SIZE(adis16480_channels), 974 .gyro_max_val = 22500 << 16, 975 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 976 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 977 .accel_max_scale = 18, 978 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 979 .int_clk = 2460000, 980 .max_dec_rate = 2048, 981 .filter_freqs = adis16480_def_filter_freqs, 982 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0), 983 }, 984 [ADIS16490] = { 985 .channels = adis16485_channels, 986 .num_channels = ARRAY_SIZE(adis16485_channels), 987 .gyro_max_val = 20000 << 16, 988 .gyro_max_scale = IIO_DEGREE_TO_RAD(100), 989 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16), 990 .accel_max_scale = 8, 991 .temp_scale = 14285, /* 14.285 milli degree Celsius */ 992 .int_clk = 4250000, 993 .max_dec_rate = 4250, 994 .filter_freqs = adis16495_def_filter_freqs, 995 .has_pps_clk_mode = true, 996 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0), 997 }, 998 [ADIS16495_1] = { 999 .channels = adis16485_channels, 1000 .num_channels = ARRAY_SIZE(adis16485_channels), 1001 .gyro_max_val = 20000 << 16, 1002 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1003 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1004 .accel_max_scale = 8, 1005 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1006 .int_clk = 4250000, 1007 .max_dec_rate = 4250, 1008 .filter_freqs = adis16495_def_filter_freqs, 1009 .has_pps_clk_mode = true, 1010 /* 20 elements of 16bits */ 1011 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1012 ADIS16495_BURST_MAX_DATA * 2), 1013 }, 1014 [ADIS16495_2] = { 1015 .channels = adis16485_channels, 1016 .num_channels = ARRAY_SIZE(adis16485_channels), 1017 .gyro_max_val = 18000 << 16, 1018 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1019 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1020 .accel_max_scale = 8, 1021 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1022 .int_clk = 4250000, 1023 .max_dec_rate = 4250, 1024 .filter_freqs = adis16495_def_filter_freqs, 1025 .has_pps_clk_mode = true, 1026 /* 20 elements of 16bits */ 1027 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1028 ADIS16495_BURST_MAX_DATA * 2), 1029 }, 1030 [ADIS16495_3] = { 1031 .channels = adis16485_channels, 1032 .num_channels = ARRAY_SIZE(adis16485_channels), 1033 .gyro_max_val = 20000 << 16, 1034 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1035 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1036 .accel_max_scale = 8, 1037 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1038 .int_clk = 4250000, 1039 .max_dec_rate = 4250, 1040 .filter_freqs = adis16495_def_filter_freqs, 1041 .has_pps_clk_mode = true, 1042 /* 20 elements of 16bits */ 1043 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1044 ADIS16495_BURST_MAX_DATA * 2), 1045 }, 1046 [ADIS16497_1] = { 1047 .channels = adis16485_channels, 1048 .num_channels = ARRAY_SIZE(adis16485_channels), 1049 .gyro_max_val = 20000 << 16, 1050 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1051 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1052 .accel_max_scale = 40, 1053 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1054 .int_clk = 4250000, 1055 .max_dec_rate = 4250, 1056 .filter_freqs = adis16495_def_filter_freqs, 1057 .has_pps_clk_mode = true, 1058 /* 20 elements of 16bits */ 1059 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1060 ADIS16495_BURST_MAX_DATA * 2), 1061 }, 1062 [ADIS16497_2] = { 1063 .channels = adis16485_channels, 1064 .num_channels = ARRAY_SIZE(adis16485_channels), 1065 .gyro_max_val = 18000 << 16, 1066 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1067 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1068 .accel_max_scale = 40, 1069 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1070 .int_clk = 4250000, 1071 .max_dec_rate = 4250, 1072 .filter_freqs = adis16495_def_filter_freqs, 1073 .has_pps_clk_mode = true, 1074 /* 20 elements of 16bits */ 1075 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1076 ADIS16495_BURST_MAX_DATA * 2), 1077 }, 1078 [ADIS16497_3] = { 1079 .channels = adis16485_channels, 1080 .num_channels = ARRAY_SIZE(adis16485_channels), 1081 .gyro_max_val = 20000 << 16, 1082 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1083 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1084 .accel_max_scale = 40, 1085 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1086 .int_clk = 4250000, 1087 .max_dec_rate = 4250, 1088 .filter_freqs = adis16495_def_filter_freqs, 1089 .has_pps_clk_mode = true, 1090 /* 20 elements of 16bits */ 1091 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1092 ADIS16495_BURST_MAX_DATA * 2), 1093 }, 1094 }; 1095 1096 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc) 1097 { 1098 u32 crc_calc; 1099 u16 crc_buf[15]; 1100 int j; 1101 1102 for (j = 0; j < n_elem; j++) 1103 crc_buf[j] = swab16(buf[j]); 1104 1105 crc_calc = crc32(~0, crc_buf, n_elem * 2); 1106 crc_calc ^= ~0; 1107 1108 return (crc == crc_calc); 1109 } 1110 1111 static irqreturn_t adis16480_trigger_handler(int irq, void *p) 1112 { 1113 struct iio_poll_func *pf = p; 1114 struct iio_dev *indio_dev = pf->indio_dev; 1115 struct adis16480 *st = iio_priv(indio_dev); 1116 struct adis *adis = &st->adis; 1117 int ret, bit, offset, i = 0; 1118 __be16 *buffer; 1119 u32 crc; 1120 bool valid; 1121 1122 adis_dev_lock(adis); 1123 if (adis->current_page != 0) { 1124 adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID); 1125 adis->tx[1] = 0; 1126 ret = spi_write(adis->spi, adis->tx, 2); 1127 if (ret) { 1128 dev_err(&adis->spi->dev, "Failed to change device page: %d\n", ret); 1129 adis_dev_unlock(adis); 1130 goto irq_done; 1131 } 1132 1133 adis->current_page = 0; 1134 } 1135 1136 ret = spi_sync(adis->spi, &adis->msg); 1137 if (ret) { 1138 dev_err(&adis->spi->dev, "Failed to read data: %d\n", ret); 1139 adis_dev_unlock(adis); 1140 goto irq_done; 1141 } 1142 1143 adis_dev_unlock(adis); 1144 1145 /* 1146 * After making the burst request, the response can have one or two 1147 * 16-bit responses containing the BURST_ID depending on the sclk. If 1148 * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ, 1149 * we have only one. To manage that variation, we use the transition from the 1150 * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5. If 1151 * we not find this variation in the first 4 segments, then the data should 1152 * not be valid. 1153 */ 1154 buffer = adis->buffer; 1155 for (offset = 0; offset < 4; offset++) { 1156 u16 curr = be16_to_cpu(buffer[offset]); 1157 u16 next = be16_to_cpu(buffer[offset + 1]); 1158 1159 if (curr == ADIS16495_BURST_ID && next != ADIS16495_BURST_ID) { 1160 offset++; 1161 break; 1162 } 1163 } 1164 1165 if (offset == 4) { 1166 dev_err(&adis->spi->dev, "Invalid burst data\n"); 1167 goto irq_done; 1168 } 1169 1170 crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]); 1171 valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc); 1172 if (!valid) { 1173 dev_err(&adis->spi->dev, "Invalid crc\n"); 1174 goto irq_done; 1175 } 1176 1177 for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { 1178 /* 1179 * When burst mode is used, temperature is the first data 1180 * channel in the sequence, but the temperature scan index 1181 * is 10. 1182 */ 1183 switch (bit) { 1184 case ADIS16480_SCAN_TEMP: 1185 st->data[i++] = buffer[offset + 1]; 1186 break; 1187 case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z: 1188 /* The lower register data is sequenced first */ 1189 st->data[i++] = buffer[2 * bit + offset + 3]; 1190 st->data[i++] = buffer[2 * bit + offset + 2]; 1191 break; 1192 } 1193 } 1194 1195 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1196 irq_done: 1197 iio_trigger_notify_done(indio_dev->trig); 1198 1199 return IRQ_HANDLED; 1200 } 1201 1202 static const struct iio_info adis16480_info = { 1203 .read_raw = &adis16480_read_raw, 1204 .write_raw = &adis16480_write_raw, 1205 .update_scan_mode = adis_update_scan_mode, 1206 .debugfs_reg_access = adis_debugfs_reg_access, 1207 }; 1208 1209 static int adis16480_stop_device(struct iio_dev *indio_dev) 1210 { 1211 struct adis16480 *st = iio_priv(indio_dev); 1212 int ret; 1213 1214 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 1215 if (ret) 1216 dev_err(&indio_dev->dev, 1217 "Could not power down device: %d\n", ret); 1218 1219 return ret; 1220 } 1221 1222 static int adis16480_enable_irq(struct adis *adis, bool enable) 1223 { 1224 uint16_t val; 1225 int ret; 1226 1227 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1228 if (ret) 1229 return ret; 1230 1231 val &= ~ADIS16480_DRDY_EN_MSK; 1232 val |= ADIS16480_DRDY_EN(enable); 1233 1234 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 1235 } 1236 1237 static int adis16480_config_irq_pin(struct device_node *of_node, 1238 struct adis16480 *st) 1239 { 1240 struct irq_data *desc; 1241 enum adis16480_int_pin pin; 1242 unsigned int irq_type; 1243 uint16_t val; 1244 int i, irq = 0; 1245 1246 desc = irq_get_irq_data(st->adis.spi->irq); 1247 if (!desc) { 1248 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1249 return -EINVAL; 1250 } 1251 1252 /* Disable data ready since the default after reset is on */ 1253 val = ADIS16480_DRDY_EN(0); 1254 1255 /* 1256 * Get the interrupt from the devicetre by reading the interrupt-names 1257 * property. If it is not specified, use DIO1 pin as default. 1258 * According to the datasheet, the factory default assigns DIO2 as data 1259 * ready signal. However, in the previous versions of the driver, DIO1 1260 * pin was used. So, we should leave it as is since some devices might 1261 * be expecting the interrupt on the wrong physical pin. 1262 */ 1263 pin = ADIS16480_PIN_DIO1; 1264 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1265 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1266 if (irq > 0) { 1267 pin = i; 1268 break; 1269 } 1270 } 1271 1272 val |= ADIS16480_DRDY_SEL(pin); 1273 1274 /* 1275 * Get the interrupt line behaviour. The data ready polarity can be 1276 * configured as positive or negative, corresponding to 1277 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively. 1278 */ 1279 irq_type = irqd_get_trigger_type(desc); 1280 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */ 1281 val |= ADIS16480_DRDY_POL(1); 1282 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1283 val |= ADIS16480_DRDY_POL(0); 1284 } else { 1285 dev_err(&st->adis.spi->dev, 1286 "Invalid interrupt type 0x%x specified\n", irq_type); 1287 return -EINVAL; 1288 } 1289 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1290 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1291 } 1292 1293 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1294 struct device_node *of_node) 1295 { 1296 const char *ext_clk_pin; 1297 enum adis16480_int_pin pin; 1298 int i; 1299 1300 pin = ADIS16480_PIN_DIO2; 1301 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1302 goto clk_input_not_found; 1303 1304 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1305 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1306 return i; 1307 } 1308 1309 clk_input_not_found: 1310 dev_info(&st->adis.spi->dev, 1311 "clk input line not specified, using DIO2\n"); 1312 return pin; 1313 } 1314 1315 static int adis16480_ext_clk_config(struct adis16480 *st, 1316 struct device_node *of_node, 1317 bool enable) 1318 { 1319 unsigned int mode, mask; 1320 enum adis16480_int_pin pin; 1321 uint16_t val; 1322 int ret; 1323 1324 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1325 if (ret) 1326 return ret; 1327 1328 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1329 /* 1330 * Each DIOx pin supports only one function at a time. When a single pin 1331 * has two assignments, the enable bit for a lower priority function 1332 * automatically resets to zero (disabling the lower priority function). 1333 */ 1334 if (pin == ADIS16480_DRDY_SEL(val)) 1335 dev_warn(&st->adis.spi->dev, 1336 "DIO%x pin supports only one function at a time\n", 1337 pin + 1); 1338 1339 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1340 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1341 /* Only ADIS1649x devices support pps ext clock mode */ 1342 if (st->chip_info->has_pps_clk_mode) { 1343 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1344 mask |= ADIS16480_SYNC_MODE_MSK; 1345 } 1346 1347 val &= ~mask; 1348 val |= mode; 1349 1350 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1351 if (ret) 1352 return ret; 1353 1354 return clk_prepare_enable(st->ext_clk); 1355 } 1356 1357 static int adis16480_get_ext_clocks(struct adis16480 *st) 1358 { 1359 st->clk_mode = ADIS16480_CLK_INT; 1360 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1361 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1362 st->clk_mode = ADIS16480_CLK_SYNC; 1363 return 0; 1364 } 1365 1366 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1367 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1368 return PTR_ERR(st->ext_clk); 1369 } 1370 1371 if (st->chip_info->has_pps_clk_mode) { 1372 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1373 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1374 st->clk_mode = ADIS16480_CLK_PPS; 1375 return 0; 1376 } 1377 1378 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1379 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1380 return PTR_ERR(st->ext_clk); 1381 } 1382 } 1383 1384 return 0; 1385 } 1386 1387 static void adis16480_stop(void *data) 1388 { 1389 adis16480_stop_device(data); 1390 } 1391 1392 static void adis16480_clk_disable(void *data) 1393 { 1394 clk_disable_unprepare(data); 1395 } 1396 1397 static int adis16480_probe(struct spi_device *spi) 1398 { 1399 const struct spi_device_id *id = spi_get_device_id(spi); 1400 const struct adis_data *adis16480_data; 1401 struct iio_dev *indio_dev; 1402 struct adis16480 *st; 1403 int ret; 1404 1405 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1406 if (indio_dev == NULL) 1407 return -ENOMEM; 1408 1409 st = iio_priv(indio_dev); 1410 1411 st->chip_info = &adis16480_chip_info[id->driver_data]; 1412 indio_dev->name = spi_get_device_id(spi)->name; 1413 indio_dev->channels = st->chip_info->channels; 1414 indio_dev->num_channels = st->chip_info->num_channels; 1415 indio_dev->info = &adis16480_info; 1416 indio_dev->modes = INDIO_DIRECT_MODE; 1417 1418 adis16480_data = &st->chip_info->adis_data; 1419 1420 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data); 1421 if (ret) 1422 return ret; 1423 1424 ret = __adis_initial_startup(&st->adis); 1425 if (ret) 1426 return ret; 1427 1428 ret = devm_add_action_or_reset(&spi->dev, adis16480_stop, indio_dev); 1429 if (ret) 1430 return ret; 1431 1432 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1433 if (ret) 1434 return ret; 1435 1436 ret = adis16480_get_ext_clocks(st); 1437 if (ret) 1438 return ret; 1439 1440 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1441 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1442 if (ret) 1443 return ret; 1444 1445 ret = devm_add_action_or_reset(&spi->dev, adis16480_clk_disable, st->ext_clk); 1446 if (ret) 1447 return ret; 1448 1449 st->clk_freq = clk_get_rate(st->ext_clk); 1450 st->clk_freq *= 1000; /* micro */ 1451 if (st->clk_mode == ADIS16480_CLK_PPS) { 1452 u16 sync_scale; 1453 1454 /* 1455 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence, 1456 * default the IMU sample rate to the highest multiple of the input clock 1457 * lower than the IMU max sample rate. The internal sample rate is the 1458 * max... 1459 */ 1460 sync_scale = st->chip_info->int_clk / st->clk_freq; 1461 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 1462 if (ret) 1463 return ret; 1464 } 1465 } else { 1466 st->clk_freq = st->chip_info->int_clk; 1467 } 1468 1469 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1470 adis16480_trigger_handler); 1471 if (ret) 1472 return ret; 1473 1474 ret = devm_iio_device_register(&spi->dev, indio_dev); 1475 if (ret) 1476 return ret; 1477 1478 adis16480_debugfs_init(indio_dev); 1479 1480 return 0; 1481 } 1482 1483 static const struct spi_device_id adis16480_ids[] = { 1484 { "adis16375", ADIS16375 }, 1485 { "adis16480", ADIS16480 }, 1486 { "adis16485", ADIS16485 }, 1487 { "adis16488", ADIS16488 }, 1488 { "adis16490", ADIS16490 }, 1489 { "adis16495-1", ADIS16495_1 }, 1490 { "adis16495-2", ADIS16495_2 }, 1491 { "adis16495-3", ADIS16495_3 }, 1492 { "adis16497-1", ADIS16497_1 }, 1493 { "adis16497-2", ADIS16497_2 }, 1494 { "adis16497-3", ADIS16497_3 }, 1495 { } 1496 }; 1497 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1498 1499 static const struct of_device_id adis16480_of_match[] = { 1500 { .compatible = "adi,adis16375" }, 1501 { .compatible = "adi,adis16480" }, 1502 { .compatible = "adi,adis16485" }, 1503 { .compatible = "adi,adis16488" }, 1504 { .compatible = "adi,adis16490" }, 1505 { .compatible = "adi,adis16495-1" }, 1506 { .compatible = "adi,adis16495-2" }, 1507 { .compatible = "adi,adis16495-3" }, 1508 { .compatible = "adi,adis16497-1" }, 1509 { .compatible = "adi,adis16497-2" }, 1510 { .compatible = "adi,adis16497-3" }, 1511 { }, 1512 }; 1513 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1514 1515 static struct spi_driver adis16480_driver = { 1516 .driver = { 1517 .name = "adis16480", 1518 .of_match_table = adis16480_of_match, 1519 }, 1520 .id_table = adis16480_ids, 1521 .probe = adis16480_probe, 1522 }; 1523 module_spi_driver(adis16480_driver); 1524 1525 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1526 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1527 MODULE_LICENSE("GPL v2"); 1528