1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/of_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/delay.h> 13 #include <linux/math.h> 14 #include <linux/mutex.h> 15 #include <linux/device.h> 16 #include <linux/kernel.h> 17 #include <linux/spi/spi.h> 18 #include <linux/slab.h> 19 #include <linux/sysfs.h> 20 #include <linux/module.h> 21 #include <linux/lcm.h> 22 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/imu/adis.h> 27 28 #include <linux/debugfs.h> 29 30 #define ADIS16480_PAGE_SIZE 0x80 31 32 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 33 34 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 35 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 36 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 37 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 38 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 39 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 40 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 41 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 42 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 43 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 44 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 45 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 46 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 47 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 48 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 49 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 50 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 51 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 52 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 53 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 54 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 55 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 56 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 57 58 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 59 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 60 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 61 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 62 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 63 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 64 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 65 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 66 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 67 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 68 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 69 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 70 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 71 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 72 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 73 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 74 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 75 76 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 77 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 78 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 79 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 80 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 81 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 82 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 83 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 84 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 85 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 86 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 87 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 88 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 89 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 90 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 91 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 92 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 93 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 94 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 95 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 96 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 97 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 98 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 99 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 100 101 /* 102 * External clock scaling in PPS mode. 103 * Available only for ADIS1649x devices 104 */ 105 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 106 107 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 108 109 /* Each filter coefficent bank spans two pages */ 110 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 111 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 112 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 113 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 114 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 115 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 116 117 /* ADIS16480_REG_FNCTIO_CTRL */ 118 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 119 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 120 #define ADIS16480_DRDY_POL_MSK BIT(2) 121 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 122 #define ADIS16480_DRDY_EN_MSK BIT(3) 123 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 124 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 125 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 126 #define ADIS16480_SYNC_EN_MSK BIT(7) 127 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 128 #define ADIS16480_SYNC_MODE_MSK BIT(8) 129 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 130 131 struct adis16480_chip_info { 132 unsigned int num_channels; 133 const struct iio_chan_spec *channels; 134 unsigned int gyro_max_val; 135 unsigned int gyro_max_scale; 136 unsigned int accel_max_val; 137 unsigned int accel_max_scale; 138 unsigned int temp_scale; 139 unsigned int int_clk; 140 unsigned int max_dec_rate; 141 const unsigned int *filter_freqs; 142 bool has_pps_clk_mode; 143 const struct adis_data adis_data; 144 }; 145 146 enum adis16480_int_pin { 147 ADIS16480_PIN_DIO1, 148 ADIS16480_PIN_DIO2, 149 ADIS16480_PIN_DIO3, 150 ADIS16480_PIN_DIO4 151 }; 152 153 enum adis16480_clock_mode { 154 ADIS16480_CLK_SYNC, 155 ADIS16480_CLK_PPS, 156 ADIS16480_CLK_INT 157 }; 158 159 struct adis16480 { 160 const struct adis16480_chip_info *chip_info; 161 162 struct adis adis; 163 struct clk *ext_clk; 164 enum adis16480_clock_mode clk_mode; 165 unsigned int clk_freq; 166 }; 167 168 static const char * const adis16480_int_pin_names[4] = { 169 [ADIS16480_PIN_DIO1] = "DIO1", 170 [ADIS16480_PIN_DIO2] = "DIO2", 171 [ADIS16480_PIN_DIO3] = "DIO3", 172 [ADIS16480_PIN_DIO4] = "DIO4", 173 }; 174 175 static bool low_rate_allow; 176 module_param(low_rate_allow, bool, 0444); 177 MODULE_PARM_DESC(low_rate_allow, 178 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)"); 179 180 #ifdef CONFIG_DEBUG_FS 181 182 static ssize_t adis16480_show_firmware_revision(struct file *file, 183 char __user *userbuf, size_t count, loff_t *ppos) 184 { 185 struct adis16480 *adis16480 = file->private_data; 186 char buf[7]; 187 size_t len; 188 u16 rev; 189 int ret; 190 191 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 192 if (ret) 193 return ret; 194 195 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 196 197 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 198 } 199 200 static const struct file_operations adis16480_firmware_revision_fops = { 201 .open = simple_open, 202 .read = adis16480_show_firmware_revision, 203 .llseek = default_llseek, 204 .owner = THIS_MODULE, 205 }; 206 207 static ssize_t adis16480_show_firmware_date(struct file *file, 208 char __user *userbuf, size_t count, loff_t *ppos) 209 { 210 struct adis16480 *adis16480 = file->private_data; 211 u16 md, year; 212 char buf[12]; 213 size_t len; 214 int ret; 215 216 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 217 if (ret) 218 return ret; 219 220 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 221 if (ret) 222 return ret; 223 224 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 225 md >> 8, md & 0xff, year); 226 227 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 228 } 229 230 static const struct file_operations adis16480_firmware_date_fops = { 231 .open = simple_open, 232 .read = adis16480_show_firmware_date, 233 .llseek = default_llseek, 234 .owner = THIS_MODULE, 235 }; 236 237 static int adis16480_show_serial_number(void *arg, u64 *val) 238 { 239 struct adis16480 *adis16480 = arg; 240 u16 serial; 241 int ret; 242 243 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 244 &serial); 245 if (ret) 246 return ret; 247 248 *val = serial; 249 250 return 0; 251 } 252 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 253 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 254 255 static int adis16480_show_product_id(void *arg, u64 *val) 256 { 257 struct adis16480 *adis16480 = arg; 258 u16 prod_id; 259 int ret; 260 261 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 262 &prod_id); 263 if (ret) 264 return ret; 265 266 *val = prod_id; 267 268 return 0; 269 } 270 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 271 adis16480_show_product_id, NULL, "%llu\n"); 272 273 static int adis16480_show_flash_count(void *arg, u64 *val) 274 { 275 struct adis16480 *adis16480 = arg; 276 u32 flash_count; 277 int ret; 278 279 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 280 &flash_count); 281 if (ret) 282 return ret; 283 284 *val = flash_count; 285 286 return 0; 287 } 288 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 289 adis16480_show_flash_count, NULL, "%lld\n"); 290 291 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 292 { 293 struct adis16480 *adis16480 = iio_priv(indio_dev); 294 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 295 296 debugfs_create_file_unsafe("firmware_revision", 0400, 297 d, adis16480, &adis16480_firmware_revision_fops); 298 debugfs_create_file_unsafe("firmware_date", 0400, 299 d, adis16480, &adis16480_firmware_date_fops); 300 debugfs_create_file_unsafe("serial_number", 0400, 301 d, adis16480, &adis16480_serial_number_fops); 302 debugfs_create_file_unsafe("product_id", 0400, 303 d, adis16480, &adis16480_product_id_fops); 304 debugfs_create_file_unsafe("flash_count", 0400, 305 d, adis16480, &adis16480_flash_count_fops); 306 307 return 0; 308 } 309 310 #else 311 312 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 313 { 314 return 0; 315 } 316 317 #endif 318 319 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 320 { 321 struct adis16480 *st = iio_priv(indio_dev); 322 unsigned int t, sample_rate = st->clk_freq; 323 int ret; 324 325 if (val < 0 || val2 < 0) 326 return -EINVAL; 327 328 t = val * 1000 + val2 / 1000; 329 if (t == 0) 330 return -EINVAL; 331 332 adis_dev_lock(&st->adis); 333 /* 334 * When using PPS mode, the input clock needs to be scaled so that we have an IMU 335 * sample rate between (optimally) 4000 and 4250. After this, we can use the 336 * decimation filter to lower the sampling rate in order to get what the user wants. 337 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 338 * the input clock. Hence, calculating the sync_scale dynamically gives us better 339 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 340 * 1. lcm of the input clock and the desired output rate. 341 * 2. get the highest multiple of the previous result lower than the adis max rate. 342 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 343 * and DEC_RATE (to get the user output rate) 344 */ 345 if (st->clk_mode == ADIS16480_CLK_PPS) { 346 unsigned long scaled_rate = lcm(st->clk_freq, t); 347 int sync_scale; 348 349 /* 350 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 351 * solution. In this case, we get the highest multiple of the input clock 352 * lower than the IMU max sample rate. 353 */ 354 if (scaled_rate > st->chip_info->int_clk) 355 scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq; 356 else 357 scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate; 358 359 /* 360 * This is not an hard requirement but it's not advised to run the IMU 361 * with a sample rate lower than 4000Hz due to possible undersampling 362 * issues. However, there are users that might really want to take the risk. 363 * Hence, we provide a module parameter for them. If set, we allow sample 364 * rates lower than 4KHz. By default, we won't allow this and we just roundup 365 * the rate to the next multiple of the input clock bigger than 4KHz. This 366 * is done like this as in some cases (when DEC_RATE is 0) might give 367 * us the closest value to the one desired by the user... 368 */ 369 if (scaled_rate < 4000000 && !low_rate_allow) 370 scaled_rate = roundup(4000000, st->clk_freq); 371 372 sync_scale = scaled_rate / st->clk_freq; 373 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 374 if (ret) 375 goto error; 376 377 sample_rate = scaled_rate; 378 } 379 380 t = DIV_ROUND_CLOSEST(sample_rate, t); 381 if (t) 382 t--; 383 384 if (t > st->chip_info->max_dec_rate) 385 t = st->chip_info->max_dec_rate; 386 387 ret = __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t); 388 error: 389 adis_dev_unlock(&st->adis); 390 return ret; 391 } 392 393 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 394 { 395 struct adis16480 *st = iio_priv(indio_dev); 396 uint16_t t; 397 int ret; 398 unsigned int freq, sample_rate = st->clk_freq; 399 400 adis_dev_lock(&st->adis); 401 402 if (st->clk_mode == ADIS16480_CLK_PPS) { 403 u16 sync_scale; 404 405 ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale); 406 if (ret) 407 goto error; 408 409 sample_rate = st->clk_freq * sync_scale; 410 } 411 412 ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t); 413 if (ret) 414 goto error; 415 416 adis_dev_unlock(&st->adis); 417 418 freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1)); 419 420 *val = freq / 1000; 421 *val2 = (freq % 1000) * 1000; 422 423 return IIO_VAL_INT_PLUS_MICRO; 424 error: 425 adis_dev_unlock(&st->adis); 426 return ret; 427 } 428 429 enum { 430 ADIS16480_SCAN_GYRO_X, 431 ADIS16480_SCAN_GYRO_Y, 432 ADIS16480_SCAN_GYRO_Z, 433 ADIS16480_SCAN_ACCEL_X, 434 ADIS16480_SCAN_ACCEL_Y, 435 ADIS16480_SCAN_ACCEL_Z, 436 ADIS16480_SCAN_MAGN_X, 437 ADIS16480_SCAN_MAGN_Y, 438 ADIS16480_SCAN_MAGN_Z, 439 ADIS16480_SCAN_BARO, 440 ADIS16480_SCAN_TEMP, 441 }; 442 443 static const unsigned int adis16480_calibbias_regs[] = { 444 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 445 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 446 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 447 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 448 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 449 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 450 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 451 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 452 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 453 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 454 }; 455 456 static const unsigned int adis16480_calibscale_regs[] = { 457 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 458 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 459 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 460 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 461 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 462 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 463 }; 464 465 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 466 const struct iio_chan_spec *chan, int bias) 467 { 468 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 469 struct adis16480 *st = iio_priv(indio_dev); 470 471 switch (chan->type) { 472 case IIO_MAGN: 473 case IIO_PRESSURE: 474 if (bias < -0x8000 || bias >= 0x8000) 475 return -EINVAL; 476 return adis_write_reg_16(&st->adis, reg, bias); 477 case IIO_ANGL_VEL: 478 case IIO_ACCEL: 479 return adis_write_reg_32(&st->adis, reg, bias); 480 default: 481 break; 482 } 483 484 return -EINVAL; 485 } 486 487 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 488 const struct iio_chan_spec *chan, int *bias) 489 { 490 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 491 struct adis16480 *st = iio_priv(indio_dev); 492 uint16_t val16; 493 uint32_t val32; 494 int ret; 495 496 switch (chan->type) { 497 case IIO_MAGN: 498 case IIO_PRESSURE: 499 ret = adis_read_reg_16(&st->adis, reg, &val16); 500 if (ret == 0) 501 *bias = sign_extend32(val16, 15); 502 break; 503 case IIO_ANGL_VEL: 504 case IIO_ACCEL: 505 ret = adis_read_reg_32(&st->adis, reg, &val32); 506 if (ret == 0) 507 *bias = sign_extend32(val32, 31); 508 break; 509 default: 510 ret = -EINVAL; 511 } 512 513 if (ret) 514 return ret; 515 516 return IIO_VAL_INT; 517 } 518 519 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 520 const struct iio_chan_spec *chan, int scale) 521 { 522 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 523 struct adis16480 *st = iio_priv(indio_dev); 524 525 if (scale < -0x8000 || scale >= 0x8000) 526 return -EINVAL; 527 528 return adis_write_reg_16(&st->adis, reg, scale); 529 } 530 531 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 532 const struct iio_chan_spec *chan, int *scale) 533 { 534 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 535 struct adis16480 *st = iio_priv(indio_dev); 536 uint16_t val16; 537 int ret; 538 539 ret = adis_read_reg_16(&st->adis, reg, &val16); 540 if (ret) 541 return ret; 542 543 *scale = sign_extend32(val16, 15); 544 return IIO_VAL_INT; 545 } 546 547 static const unsigned int adis16480_def_filter_freqs[] = { 548 310, 549 55, 550 275, 551 63, 552 }; 553 554 static const unsigned int adis16495_def_filter_freqs[] = { 555 300, 556 100, 557 300, 558 100, 559 }; 560 561 static const unsigned int ad16480_filter_data[][2] = { 562 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 563 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 564 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 565 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 566 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 567 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 568 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 569 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 570 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 571 }; 572 573 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 574 const struct iio_chan_spec *chan, int *freq) 575 { 576 struct adis16480 *st = iio_priv(indio_dev); 577 unsigned int enable_mask, offset, reg; 578 uint16_t val; 579 int ret; 580 581 reg = ad16480_filter_data[chan->scan_index][0]; 582 offset = ad16480_filter_data[chan->scan_index][1]; 583 enable_mask = BIT(offset + 2); 584 585 ret = adis_read_reg_16(&st->adis, reg, &val); 586 if (ret) 587 return ret; 588 589 if (!(val & enable_mask)) 590 *freq = 0; 591 else 592 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 593 594 return IIO_VAL_INT; 595 } 596 597 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 598 const struct iio_chan_spec *chan, unsigned int freq) 599 { 600 struct adis16480 *st = iio_priv(indio_dev); 601 unsigned int enable_mask, offset, reg; 602 unsigned int diff, best_diff; 603 unsigned int i, best_freq; 604 uint16_t val; 605 int ret; 606 607 reg = ad16480_filter_data[chan->scan_index][0]; 608 offset = ad16480_filter_data[chan->scan_index][1]; 609 enable_mask = BIT(offset + 2); 610 611 adis_dev_lock(&st->adis); 612 613 ret = __adis_read_reg_16(&st->adis, reg, &val); 614 if (ret) 615 goto out_unlock; 616 617 if (freq == 0) { 618 val &= ~enable_mask; 619 } else { 620 best_freq = 0; 621 best_diff = st->chip_info->filter_freqs[0]; 622 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 623 if (st->chip_info->filter_freqs[i] >= freq) { 624 diff = st->chip_info->filter_freqs[i] - freq; 625 if (diff < best_diff) { 626 best_diff = diff; 627 best_freq = i; 628 } 629 } 630 } 631 632 val &= ~(0x3 << offset); 633 val |= best_freq << offset; 634 val |= enable_mask; 635 } 636 637 ret = __adis_write_reg_16(&st->adis, reg, val); 638 out_unlock: 639 adis_dev_unlock(&st->adis); 640 641 return ret; 642 } 643 644 static int adis16480_read_raw(struct iio_dev *indio_dev, 645 const struct iio_chan_spec *chan, int *val, int *val2, long info) 646 { 647 struct adis16480 *st = iio_priv(indio_dev); 648 unsigned int temp; 649 650 switch (info) { 651 case IIO_CHAN_INFO_RAW: 652 return adis_single_conversion(indio_dev, chan, 0, val); 653 case IIO_CHAN_INFO_SCALE: 654 switch (chan->type) { 655 case IIO_ANGL_VEL: 656 *val = st->chip_info->gyro_max_scale; 657 *val2 = st->chip_info->gyro_max_val; 658 return IIO_VAL_FRACTIONAL; 659 case IIO_ACCEL: 660 *val = st->chip_info->accel_max_scale; 661 *val2 = st->chip_info->accel_max_val; 662 return IIO_VAL_FRACTIONAL; 663 case IIO_MAGN: 664 *val = 0; 665 *val2 = 100; /* 0.0001 gauss */ 666 return IIO_VAL_INT_PLUS_MICRO; 667 case IIO_TEMP: 668 /* 669 * +85 degrees Celsius = temp_max_scale 670 * +25 degrees Celsius = 0 671 * LSB, 25 degrees Celsius = 60 / temp_max_scale 672 */ 673 *val = st->chip_info->temp_scale / 1000; 674 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 675 return IIO_VAL_INT_PLUS_MICRO; 676 case IIO_PRESSURE: 677 /* 678 * max scale is 1310 mbar 679 * max raw value is 32767 shifted for 32bits 680 */ 681 *val = 131; /* 1310mbar = 131 kPa */ 682 *val2 = 32767 << 16; 683 return IIO_VAL_FRACTIONAL; 684 default: 685 return -EINVAL; 686 } 687 case IIO_CHAN_INFO_OFFSET: 688 /* Only the temperature channel has a offset */ 689 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 690 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 691 return IIO_VAL_INT; 692 case IIO_CHAN_INFO_CALIBBIAS: 693 return adis16480_get_calibbias(indio_dev, chan, val); 694 case IIO_CHAN_INFO_CALIBSCALE: 695 return adis16480_get_calibscale(indio_dev, chan, val); 696 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 697 return adis16480_get_filter_freq(indio_dev, chan, val); 698 case IIO_CHAN_INFO_SAMP_FREQ: 699 return adis16480_get_freq(indio_dev, val, val2); 700 default: 701 return -EINVAL; 702 } 703 } 704 705 static int adis16480_write_raw(struct iio_dev *indio_dev, 706 const struct iio_chan_spec *chan, int val, int val2, long info) 707 { 708 switch (info) { 709 case IIO_CHAN_INFO_CALIBBIAS: 710 return adis16480_set_calibbias(indio_dev, chan, val); 711 case IIO_CHAN_INFO_CALIBSCALE: 712 return adis16480_set_calibscale(indio_dev, chan, val); 713 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 714 return adis16480_set_filter_freq(indio_dev, chan, val); 715 case IIO_CHAN_INFO_SAMP_FREQ: 716 return adis16480_set_freq(indio_dev, val, val2); 717 718 default: 719 return -EINVAL; 720 } 721 } 722 723 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 724 { \ 725 .type = (_type), \ 726 .modified = 1, \ 727 .channel2 = (_mod), \ 728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 729 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 730 _info_sep, \ 731 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 732 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 733 .address = (_address), \ 734 .scan_index = (_si), \ 735 .scan_type = { \ 736 .sign = 's', \ 737 .realbits = (_bits), \ 738 .storagebits = (_bits), \ 739 .endianness = IIO_BE, \ 740 }, \ 741 } 742 743 #define ADIS16480_GYRO_CHANNEL(_mod) \ 744 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 745 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 746 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 747 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 748 32) 749 750 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 751 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 752 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 753 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 754 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 755 32) 756 757 #define ADIS16480_MAGN_CHANNEL(_mod) \ 758 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 759 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 760 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 761 16) 762 763 #define ADIS16480_PRESSURE_CHANNEL() \ 764 { \ 765 .type = IIO_PRESSURE, \ 766 .indexed = 1, \ 767 .channel = 0, \ 768 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 769 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 770 BIT(IIO_CHAN_INFO_SCALE), \ 771 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 772 .address = ADIS16480_REG_BAROM_OUT, \ 773 .scan_index = ADIS16480_SCAN_BARO, \ 774 .scan_type = { \ 775 .sign = 's', \ 776 .realbits = 32, \ 777 .storagebits = 32, \ 778 .endianness = IIO_BE, \ 779 }, \ 780 } 781 782 #define ADIS16480_TEMP_CHANNEL() { \ 783 .type = IIO_TEMP, \ 784 .indexed = 1, \ 785 .channel = 0, \ 786 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 787 BIT(IIO_CHAN_INFO_SCALE) | \ 788 BIT(IIO_CHAN_INFO_OFFSET), \ 789 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 790 .address = ADIS16480_REG_TEMP_OUT, \ 791 .scan_index = ADIS16480_SCAN_TEMP, \ 792 .scan_type = { \ 793 .sign = 's', \ 794 .realbits = 16, \ 795 .storagebits = 16, \ 796 .endianness = IIO_BE, \ 797 }, \ 798 } 799 800 static const struct iio_chan_spec adis16480_channels[] = { 801 ADIS16480_GYRO_CHANNEL(X), 802 ADIS16480_GYRO_CHANNEL(Y), 803 ADIS16480_GYRO_CHANNEL(Z), 804 ADIS16480_ACCEL_CHANNEL(X), 805 ADIS16480_ACCEL_CHANNEL(Y), 806 ADIS16480_ACCEL_CHANNEL(Z), 807 ADIS16480_MAGN_CHANNEL(X), 808 ADIS16480_MAGN_CHANNEL(Y), 809 ADIS16480_MAGN_CHANNEL(Z), 810 ADIS16480_PRESSURE_CHANNEL(), 811 ADIS16480_TEMP_CHANNEL(), 812 IIO_CHAN_SOFT_TIMESTAMP(11) 813 }; 814 815 static const struct iio_chan_spec adis16485_channels[] = { 816 ADIS16480_GYRO_CHANNEL(X), 817 ADIS16480_GYRO_CHANNEL(Y), 818 ADIS16480_GYRO_CHANNEL(Z), 819 ADIS16480_ACCEL_CHANNEL(X), 820 ADIS16480_ACCEL_CHANNEL(Y), 821 ADIS16480_ACCEL_CHANNEL(Z), 822 ADIS16480_TEMP_CHANNEL(), 823 IIO_CHAN_SOFT_TIMESTAMP(7) 824 }; 825 826 enum adis16480_variant { 827 ADIS16375, 828 ADIS16480, 829 ADIS16485, 830 ADIS16488, 831 ADIS16490, 832 ADIS16495_1, 833 ADIS16495_2, 834 ADIS16495_3, 835 ADIS16497_1, 836 ADIS16497_2, 837 ADIS16497_3, 838 }; 839 840 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 841 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 842 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 843 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 844 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 845 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 846 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 847 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 848 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 849 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 850 851 static const char * const adis16480_status_error_msgs[] = { 852 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 853 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 854 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 855 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 856 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 857 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 858 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 859 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 860 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 861 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 862 }; 863 864 static int adis16480_enable_irq(struct adis *adis, bool enable); 865 866 #define ADIS16480_DATA(_prod_id, _timeouts) \ 867 { \ 868 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \ 869 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \ 870 .prod_id_reg = ADIS16480_REG_PROD_ID, \ 871 .prod_id = (_prod_id), \ 872 .has_paging = true, \ 873 .read_delay = 5, \ 874 .write_delay = 5, \ 875 .self_test_mask = BIT(1), \ 876 .self_test_reg = ADIS16480_REG_GLOB_CMD, \ 877 .status_error_msgs = adis16480_status_error_msgs, \ 878 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \ 879 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \ 880 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \ 881 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \ 882 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \ 883 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \ 884 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \ 885 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \ 886 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \ 887 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \ 888 .enable_irq = adis16480_enable_irq, \ 889 .timeouts = (_timeouts), \ 890 } 891 892 static const struct adis_timeout adis16485_timeouts = { 893 .reset_ms = 560, 894 .sw_reset_ms = 120, 895 .self_test_ms = 12, 896 }; 897 898 static const struct adis_timeout adis16480_timeouts = { 899 .reset_ms = 560, 900 .sw_reset_ms = 560, 901 .self_test_ms = 12, 902 }; 903 904 static const struct adis_timeout adis16495_timeouts = { 905 .reset_ms = 170, 906 .sw_reset_ms = 130, 907 .self_test_ms = 40, 908 }; 909 910 static const struct adis_timeout adis16495_1_timeouts = { 911 .reset_ms = 250, 912 .sw_reset_ms = 210, 913 .self_test_ms = 20, 914 }; 915 916 static const struct adis16480_chip_info adis16480_chip_info[] = { 917 [ADIS16375] = { 918 .channels = adis16485_channels, 919 .num_channels = ARRAY_SIZE(adis16485_channels), 920 /* 921 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 922 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 923 * it gives better approximation. However, in this case we 924 * cannot do it since it would not fit in a 32bit variable. 925 */ 926 .gyro_max_val = 22887 << 16, 927 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 928 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 929 .accel_max_scale = 18, 930 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 931 .int_clk = 2460000, 932 .max_dec_rate = 2048, 933 .filter_freqs = adis16480_def_filter_freqs, 934 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts), 935 }, 936 [ADIS16480] = { 937 .channels = adis16480_channels, 938 .num_channels = ARRAY_SIZE(adis16480_channels), 939 .gyro_max_val = 22500 << 16, 940 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 941 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 942 .accel_max_scale = 10, 943 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 944 .int_clk = 2460000, 945 .max_dec_rate = 2048, 946 .filter_freqs = adis16480_def_filter_freqs, 947 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts), 948 }, 949 [ADIS16485] = { 950 .channels = adis16485_channels, 951 .num_channels = ARRAY_SIZE(adis16485_channels), 952 .gyro_max_val = 22500 << 16, 953 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 954 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 955 .accel_max_scale = 5, 956 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 957 .int_clk = 2460000, 958 .max_dec_rate = 2048, 959 .filter_freqs = adis16480_def_filter_freqs, 960 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts), 961 }, 962 [ADIS16488] = { 963 .channels = adis16480_channels, 964 .num_channels = ARRAY_SIZE(adis16480_channels), 965 .gyro_max_val = 22500 << 16, 966 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 967 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 968 .accel_max_scale = 18, 969 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 970 .int_clk = 2460000, 971 .max_dec_rate = 2048, 972 .filter_freqs = adis16480_def_filter_freqs, 973 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts), 974 }, 975 [ADIS16490] = { 976 .channels = adis16485_channels, 977 .num_channels = ARRAY_SIZE(adis16485_channels), 978 .gyro_max_val = 20000 << 16, 979 .gyro_max_scale = IIO_DEGREE_TO_RAD(100), 980 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16), 981 .accel_max_scale = 8, 982 .temp_scale = 14285, /* 14.285 milli degree Celsius */ 983 .int_clk = 4250000, 984 .max_dec_rate = 4250, 985 .filter_freqs = adis16495_def_filter_freqs, 986 .has_pps_clk_mode = true, 987 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts), 988 }, 989 [ADIS16495_1] = { 990 .channels = adis16485_channels, 991 .num_channels = ARRAY_SIZE(adis16485_channels), 992 .gyro_max_val = 20000 << 16, 993 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 994 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 995 .accel_max_scale = 8, 996 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 997 .int_clk = 4250000, 998 .max_dec_rate = 4250, 999 .filter_freqs = adis16495_def_filter_freqs, 1000 .has_pps_clk_mode = true, 1001 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 1002 }, 1003 [ADIS16495_2] = { 1004 .channels = adis16485_channels, 1005 .num_channels = ARRAY_SIZE(adis16485_channels), 1006 .gyro_max_val = 18000 << 16, 1007 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1008 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1009 .accel_max_scale = 8, 1010 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1011 .int_clk = 4250000, 1012 .max_dec_rate = 4250, 1013 .filter_freqs = adis16495_def_filter_freqs, 1014 .has_pps_clk_mode = true, 1015 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 1016 }, 1017 [ADIS16495_3] = { 1018 .channels = adis16485_channels, 1019 .num_channels = ARRAY_SIZE(adis16485_channels), 1020 .gyro_max_val = 20000 << 16, 1021 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1022 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1023 .accel_max_scale = 8, 1024 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1025 .int_clk = 4250000, 1026 .max_dec_rate = 4250, 1027 .filter_freqs = adis16495_def_filter_freqs, 1028 .has_pps_clk_mode = true, 1029 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 1030 }, 1031 [ADIS16497_1] = { 1032 .channels = adis16485_channels, 1033 .num_channels = ARRAY_SIZE(adis16485_channels), 1034 .gyro_max_val = 20000 << 16, 1035 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1036 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1037 .accel_max_scale = 40, 1038 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1039 .int_clk = 4250000, 1040 .max_dec_rate = 4250, 1041 .filter_freqs = adis16495_def_filter_freqs, 1042 .has_pps_clk_mode = true, 1043 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1044 }, 1045 [ADIS16497_2] = { 1046 .channels = adis16485_channels, 1047 .num_channels = ARRAY_SIZE(adis16485_channels), 1048 .gyro_max_val = 18000 << 16, 1049 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1050 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1051 .accel_max_scale = 40, 1052 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1053 .int_clk = 4250000, 1054 .max_dec_rate = 4250, 1055 .filter_freqs = adis16495_def_filter_freqs, 1056 .has_pps_clk_mode = true, 1057 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1058 }, 1059 [ADIS16497_3] = { 1060 .channels = adis16485_channels, 1061 .num_channels = ARRAY_SIZE(adis16485_channels), 1062 .gyro_max_val = 20000 << 16, 1063 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1064 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1065 .accel_max_scale = 40, 1066 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1067 .int_clk = 4250000, 1068 .max_dec_rate = 4250, 1069 .filter_freqs = adis16495_def_filter_freqs, 1070 .has_pps_clk_mode = true, 1071 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1072 }, 1073 }; 1074 1075 static const struct iio_info adis16480_info = { 1076 .read_raw = &adis16480_read_raw, 1077 .write_raw = &adis16480_write_raw, 1078 .update_scan_mode = adis_update_scan_mode, 1079 .debugfs_reg_access = adis_debugfs_reg_access, 1080 }; 1081 1082 static int adis16480_stop_device(struct iio_dev *indio_dev) 1083 { 1084 struct adis16480 *st = iio_priv(indio_dev); 1085 int ret; 1086 1087 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 1088 if (ret) 1089 dev_err(&indio_dev->dev, 1090 "Could not power down device: %d\n", ret); 1091 1092 return ret; 1093 } 1094 1095 static int adis16480_enable_irq(struct adis *adis, bool enable) 1096 { 1097 uint16_t val; 1098 int ret; 1099 1100 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1101 if (ret) 1102 return ret; 1103 1104 val &= ~ADIS16480_DRDY_EN_MSK; 1105 val |= ADIS16480_DRDY_EN(enable); 1106 1107 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 1108 } 1109 1110 static int adis16480_config_irq_pin(struct device_node *of_node, 1111 struct adis16480 *st) 1112 { 1113 struct irq_data *desc; 1114 enum adis16480_int_pin pin; 1115 unsigned int irq_type; 1116 uint16_t val; 1117 int i, irq = 0; 1118 1119 desc = irq_get_irq_data(st->adis.spi->irq); 1120 if (!desc) { 1121 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1122 return -EINVAL; 1123 } 1124 1125 /* Disable data ready since the default after reset is on */ 1126 val = ADIS16480_DRDY_EN(0); 1127 1128 /* 1129 * Get the interrupt from the devicetre by reading the interrupt-names 1130 * property. If it is not specified, use DIO1 pin as default. 1131 * According to the datasheet, the factory default assigns DIO2 as data 1132 * ready signal. However, in the previous versions of the driver, DIO1 1133 * pin was used. So, we should leave it as is since some devices might 1134 * be expecting the interrupt on the wrong physical pin. 1135 */ 1136 pin = ADIS16480_PIN_DIO1; 1137 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1138 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1139 if (irq > 0) { 1140 pin = i; 1141 break; 1142 } 1143 } 1144 1145 val |= ADIS16480_DRDY_SEL(pin); 1146 1147 /* 1148 * Get the interrupt line behaviour. The data ready polarity can be 1149 * configured as positive or negative, corresponding to 1150 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively. 1151 */ 1152 irq_type = irqd_get_trigger_type(desc); 1153 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */ 1154 val |= ADIS16480_DRDY_POL(1); 1155 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1156 val |= ADIS16480_DRDY_POL(0); 1157 } else { 1158 dev_err(&st->adis.spi->dev, 1159 "Invalid interrupt type 0x%x specified\n", irq_type); 1160 return -EINVAL; 1161 } 1162 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1163 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1164 } 1165 1166 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1167 struct device_node *of_node) 1168 { 1169 const char *ext_clk_pin; 1170 enum adis16480_int_pin pin; 1171 int i; 1172 1173 pin = ADIS16480_PIN_DIO2; 1174 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1175 goto clk_input_not_found; 1176 1177 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1178 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1179 return i; 1180 } 1181 1182 clk_input_not_found: 1183 dev_info(&st->adis.spi->dev, 1184 "clk input line not specified, using DIO2\n"); 1185 return pin; 1186 } 1187 1188 static int adis16480_ext_clk_config(struct adis16480 *st, 1189 struct device_node *of_node, 1190 bool enable) 1191 { 1192 unsigned int mode, mask; 1193 enum adis16480_int_pin pin; 1194 uint16_t val; 1195 int ret; 1196 1197 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1198 if (ret) 1199 return ret; 1200 1201 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1202 /* 1203 * Each DIOx pin supports only one function at a time. When a single pin 1204 * has two assignments, the enable bit for a lower priority function 1205 * automatically resets to zero (disabling the lower priority function). 1206 */ 1207 if (pin == ADIS16480_DRDY_SEL(val)) 1208 dev_warn(&st->adis.spi->dev, 1209 "DIO%x pin supports only one function at a time\n", 1210 pin + 1); 1211 1212 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1213 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1214 /* Only ADIS1649x devices support pps ext clock mode */ 1215 if (st->chip_info->has_pps_clk_mode) { 1216 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1217 mask |= ADIS16480_SYNC_MODE_MSK; 1218 } 1219 1220 val &= ~mask; 1221 val |= mode; 1222 1223 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1224 if (ret) 1225 return ret; 1226 1227 return clk_prepare_enable(st->ext_clk); 1228 } 1229 1230 static int adis16480_get_ext_clocks(struct adis16480 *st) 1231 { 1232 st->clk_mode = ADIS16480_CLK_INT; 1233 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1234 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1235 st->clk_mode = ADIS16480_CLK_SYNC; 1236 return 0; 1237 } 1238 1239 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1240 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1241 return PTR_ERR(st->ext_clk); 1242 } 1243 1244 if (st->chip_info->has_pps_clk_mode) { 1245 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1246 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1247 st->clk_mode = ADIS16480_CLK_PPS; 1248 return 0; 1249 } 1250 1251 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1252 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1253 return PTR_ERR(st->ext_clk); 1254 } 1255 } 1256 1257 return 0; 1258 } 1259 1260 static void adis16480_stop(void *data) 1261 { 1262 adis16480_stop_device(data); 1263 } 1264 1265 static void adis16480_clk_disable(void *data) 1266 { 1267 clk_disable_unprepare(data); 1268 } 1269 1270 static int adis16480_probe(struct spi_device *spi) 1271 { 1272 const struct spi_device_id *id = spi_get_device_id(spi); 1273 const struct adis_data *adis16480_data; 1274 struct iio_dev *indio_dev; 1275 struct adis16480 *st; 1276 int ret; 1277 1278 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1279 if (indio_dev == NULL) 1280 return -ENOMEM; 1281 1282 spi_set_drvdata(spi, indio_dev); 1283 1284 st = iio_priv(indio_dev); 1285 1286 st->chip_info = &adis16480_chip_info[id->driver_data]; 1287 indio_dev->name = spi_get_device_id(spi)->name; 1288 indio_dev->channels = st->chip_info->channels; 1289 indio_dev->num_channels = st->chip_info->num_channels; 1290 indio_dev->info = &adis16480_info; 1291 indio_dev->modes = INDIO_DIRECT_MODE; 1292 1293 adis16480_data = &st->chip_info->adis_data; 1294 1295 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data); 1296 if (ret) 1297 return ret; 1298 1299 ret = __adis_initial_startup(&st->adis); 1300 if (ret) 1301 return ret; 1302 1303 ret = devm_add_action_or_reset(&spi->dev, adis16480_stop, indio_dev); 1304 if (ret) 1305 return ret; 1306 1307 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1308 if (ret) 1309 return ret; 1310 1311 ret = adis16480_get_ext_clocks(st); 1312 if (ret) 1313 return ret; 1314 1315 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1316 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1317 if (ret) 1318 return ret; 1319 1320 ret = devm_add_action_or_reset(&spi->dev, adis16480_clk_disable, st->ext_clk); 1321 if (ret) 1322 return ret; 1323 1324 st->clk_freq = clk_get_rate(st->ext_clk); 1325 st->clk_freq *= 1000; /* micro */ 1326 if (st->clk_mode == ADIS16480_CLK_PPS) { 1327 u16 sync_scale; 1328 1329 /* 1330 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence, 1331 * default the IMU sample rate to the highest multiple of the input clock 1332 * lower than the IMU max sample rate. The internal sample rate is the 1333 * max... 1334 */ 1335 sync_scale = st->chip_info->int_clk / st->clk_freq; 1336 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 1337 if (ret) 1338 return ret; 1339 } 1340 } else { 1341 st->clk_freq = st->chip_info->int_clk; 1342 } 1343 1344 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1345 if (ret) 1346 return ret; 1347 1348 ret = devm_iio_device_register(&spi->dev, indio_dev); 1349 if (ret) 1350 return ret; 1351 1352 adis16480_debugfs_init(indio_dev); 1353 1354 return 0; 1355 } 1356 1357 static const struct spi_device_id adis16480_ids[] = { 1358 { "adis16375", ADIS16375 }, 1359 { "adis16480", ADIS16480 }, 1360 { "adis16485", ADIS16485 }, 1361 { "adis16488", ADIS16488 }, 1362 { "adis16490", ADIS16490 }, 1363 { "adis16495-1", ADIS16495_1 }, 1364 { "adis16495-2", ADIS16495_2 }, 1365 { "adis16495-3", ADIS16495_3 }, 1366 { "adis16497-1", ADIS16497_1 }, 1367 { "adis16497-2", ADIS16497_2 }, 1368 { "adis16497-3", ADIS16497_3 }, 1369 { } 1370 }; 1371 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1372 1373 static const struct of_device_id adis16480_of_match[] = { 1374 { .compatible = "adi,adis16375" }, 1375 { .compatible = "adi,adis16480" }, 1376 { .compatible = "adi,adis16485" }, 1377 { .compatible = "adi,adis16488" }, 1378 { .compatible = "adi,adis16490" }, 1379 { .compatible = "adi,adis16495-1" }, 1380 { .compatible = "adi,adis16495-2" }, 1381 { .compatible = "adi,adis16495-3" }, 1382 { .compatible = "adi,adis16497-1" }, 1383 { .compatible = "adi,adis16497-2" }, 1384 { .compatible = "adi,adis16497-3" }, 1385 { }, 1386 }; 1387 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1388 1389 static struct spi_driver adis16480_driver = { 1390 .driver = { 1391 .name = "adis16480", 1392 .of_match_table = adis16480_of_match, 1393 }, 1394 .id_table = adis16480_ids, 1395 .probe = adis16480_probe, 1396 }; 1397 module_spi_driver(adis16480_driver); 1398 1399 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1400 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1401 MODULE_LICENSE("GPL v2"); 1402