1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/bitfield.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/math.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/spi/spi.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/lcm.h> 19 #include <linux/property.h> 20 #include <linux/swab.h> 21 #include <linux/crc32.h> 22 23 #include <linux/iio/iio.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/imu/adis.h> 26 #include <linux/iio/trigger_consumer.h> 27 28 #include <linux/debugfs.h> 29 30 #define ADIS16480_PAGE_SIZE 0x80 31 32 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 33 34 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 35 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 36 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 37 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 38 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 39 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 40 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 41 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 42 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 43 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 44 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 45 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 46 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 47 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 48 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 49 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 50 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 51 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 52 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 53 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 54 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 55 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 56 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 57 58 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 59 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 60 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 61 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 62 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 63 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 64 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 65 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 66 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 67 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 68 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 69 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 70 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 71 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 72 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 73 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 74 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 75 76 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 77 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 78 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 79 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 80 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 81 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 82 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 83 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 84 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 85 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 86 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 87 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 88 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 89 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 90 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 91 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 92 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 93 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 94 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 95 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 96 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 97 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 98 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 99 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 100 101 /* 102 * External clock scaling in PPS mode. 103 * Available only for ADIS1649x devices 104 */ 105 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 106 #define ADIS16495_REG_BURST_CMD ADIS16480_REG(0x00, 0x7C) 107 #define ADIS16495_GYRO_ACCEL_BURST_ID 0xA5A5 108 #define ADIS16545_DELTA_ANG_VEL_BURST_ID 0xC3C3 109 /* total number of segments in burst */ 110 #define ADIS16495_BURST_MAX_DATA 20 111 112 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 113 114 /* Each filter coefficent bank spans two pages */ 115 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 116 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 117 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 118 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 119 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 120 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 121 122 /* ADIS16480_REG_FNCTIO_CTRL */ 123 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 124 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 125 #define ADIS16480_DRDY_POL_MSK BIT(2) 126 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 127 #define ADIS16480_DRDY_EN_MSK BIT(3) 128 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 129 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 130 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 131 #define ADIS16480_SYNC_EN_MSK BIT(7) 132 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 133 #define ADIS16480_SYNC_MODE_MSK BIT(8) 134 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 135 136 #define ADIS16545_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) 137 #define ADIS16545_BURST_DATA_SEL_1_CHN_MASK GENMASK(16, 11) 138 #define ADIS16545_BURST_DATA_SEL_MASK BIT(8) 139 140 struct adis16480_chip_info { 141 unsigned int num_channels; 142 const struct iio_chan_spec *channels; 143 unsigned int gyro_max_val; 144 unsigned int gyro_max_scale; 145 unsigned int accel_max_val; 146 unsigned int accel_max_scale; 147 unsigned int temp_scale; 148 unsigned int deltang_max_val; 149 unsigned int deltvel_max_val; 150 unsigned int int_clk; 151 unsigned int max_dec_rate; 152 const unsigned int *filter_freqs; 153 bool has_pps_clk_mode; 154 bool has_sleep_cnt; 155 bool has_burst_delta_data; 156 const struct adis_data adis_data; 157 }; 158 159 enum adis16480_int_pin { 160 ADIS16480_PIN_DIO1, 161 ADIS16480_PIN_DIO2, 162 ADIS16480_PIN_DIO3, 163 ADIS16480_PIN_DIO4 164 }; 165 166 enum adis16480_clock_mode { 167 ADIS16480_CLK_SYNC, 168 ADIS16480_CLK_PPS, 169 ADIS16480_CLK_INT 170 }; 171 172 struct adis16480 { 173 const struct adis16480_chip_info *chip_info; 174 175 struct adis adis; 176 struct clk *ext_clk; 177 enum adis16480_clock_mode clk_mode; 178 unsigned int clk_freq; 179 u16 burst_id; 180 /* Alignment needed for the timestamp */ 181 __be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8); 182 }; 183 184 static const char * const adis16480_int_pin_names[4] = { 185 [ADIS16480_PIN_DIO1] = "DIO1", 186 [ADIS16480_PIN_DIO2] = "DIO2", 187 [ADIS16480_PIN_DIO3] = "DIO3", 188 [ADIS16480_PIN_DIO4] = "DIO4", 189 }; 190 191 static bool low_rate_allow; 192 module_param(low_rate_allow, bool, 0444); 193 MODULE_PARM_DESC(low_rate_allow, 194 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)"); 195 196 #ifdef CONFIG_DEBUG_FS 197 198 static ssize_t adis16480_show_firmware_revision(struct file *file, 199 char __user *userbuf, size_t count, loff_t *ppos) 200 { 201 struct adis16480 *adis16480 = file->private_data; 202 char buf[7]; 203 size_t len; 204 u16 rev; 205 int ret; 206 207 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 208 if (ret) 209 return ret; 210 211 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 212 213 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 214 } 215 216 static const struct file_operations adis16480_firmware_revision_fops = { 217 .open = simple_open, 218 .read = adis16480_show_firmware_revision, 219 .llseek = default_llseek, 220 .owner = THIS_MODULE, 221 }; 222 223 static ssize_t adis16480_show_firmware_date(struct file *file, 224 char __user *userbuf, size_t count, loff_t *ppos) 225 { 226 struct adis16480 *adis16480 = file->private_data; 227 u16 md, year; 228 char buf[12]; 229 size_t len; 230 int ret; 231 232 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 233 if (ret) 234 return ret; 235 236 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 237 if (ret) 238 return ret; 239 240 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 241 md >> 8, md & 0xff, year); 242 243 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 244 } 245 246 static const struct file_operations adis16480_firmware_date_fops = { 247 .open = simple_open, 248 .read = adis16480_show_firmware_date, 249 .llseek = default_llseek, 250 .owner = THIS_MODULE, 251 }; 252 253 static int adis16480_show_serial_number(void *arg, u64 *val) 254 { 255 struct adis16480 *adis16480 = arg; 256 u16 serial; 257 int ret; 258 259 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 260 &serial); 261 if (ret) 262 return ret; 263 264 *val = serial; 265 266 return 0; 267 } 268 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 269 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 270 271 static int adis16480_show_product_id(void *arg, u64 *val) 272 { 273 struct adis16480 *adis16480 = arg; 274 u16 prod_id; 275 int ret; 276 277 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 278 &prod_id); 279 if (ret) 280 return ret; 281 282 *val = prod_id; 283 284 return 0; 285 } 286 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 287 adis16480_show_product_id, NULL, "%llu\n"); 288 289 static int adis16480_show_flash_count(void *arg, u64 *val) 290 { 291 struct adis16480 *adis16480 = arg; 292 u32 flash_count; 293 int ret; 294 295 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 296 &flash_count); 297 if (ret) 298 return ret; 299 300 *val = flash_count; 301 302 return 0; 303 } 304 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 305 adis16480_show_flash_count, NULL, "%lld\n"); 306 307 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 308 { 309 struct adis16480 *adis16480 = iio_priv(indio_dev); 310 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 311 312 debugfs_create_file_unsafe("firmware_revision", 0400, 313 d, adis16480, &adis16480_firmware_revision_fops); 314 debugfs_create_file_unsafe("firmware_date", 0400, 315 d, adis16480, &adis16480_firmware_date_fops); 316 debugfs_create_file_unsafe("serial_number", 0400, 317 d, adis16480, &adis16480_serial_number_fops); 318 debugfs_create_file_unsafe("product_id", 0400, 319 d, adis16480, &adis16480_product_id_fops); 320 debugfs_create_file_unsafe("flash_count", 0400, 321 d, adis16480, &adis16480_flash_count_fops); 322 323 return 0; 324 } 325 326 #else 327 328 static int adis16480_debugfs_init(struct iio_dev *indio_dev) 329 { 330 return 0; 331 } 332 333 #endif 334 335 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 336 { 337 struct adis16480 *st = iio_priv(indio_dev); 338 unsigned int t, sample_rate = st->clk_freq; 339 int ret; 340 341 if (val < 0 || val2 < 0) 342 return -EINVAL; 343 344 t = val * 1000 + val2 / 1000; 345 if (t == 0) 346 return -EINVAL; 347 348 adis_dev_auto_lock(&st->adis); 349 /* 350 * When using PPS mode, the input clock needs to be scaled so that we have an IMU 351 * sample rate between (optimally) 4000 and 4250. After this, we can use the 352 * decimation filter to lower the sampling rate in order to get what the user wants. 353 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 354 * the input clock. Hence, calculating the sync_scale dynamically gives us better 355 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 356 * 1. lcm of the input clock and the desired output rate. 357 * 2. get the highest multiple of the previous result lower than the adis max rate. 358 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 359 * and DEC_RATE (to get the user output rate) 360 */ 361 if (st->clk_mode == ADIS16480_CLK_PPS) { 362 unsigned long scaled_rate = lcm(st->clk_freq, t); 363 int sync_scale; 364 365 /* 366 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 367 * solution. In this case, we get the highest multiple of the input clock 368 * lower than the IMU max sample rate. 369 */ 370 if (scaled_rate > st->chip_info->int_clk) 371 scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq; 372 else 373 scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate; 374 375 /* 376 * This is not an hard requirement but it's not advised to run the IMU 377 * with a sample rate lower than 4000Hz due to possible undersampling 378 * issues. However, there are users that might really want to take the risk. 379 * Hence, we provide a module parameter for them. If set, we allow sample 380 * rates lower than 4KHz. By default, we won't allow this and we just roundup 381 * the rate to the next multiple of the input clock bigger than 4KHz. This 382 * is done like this as in some cases (when DEC_RATE is 0) might give 383 * us the closest value to the one desired by the user... 384 */ 385 if (scaled_rate < 4000000 && !low_rate_allow) 386 scaled_rate = roundup(4000000, st->clk_freq); 387 388 sync_scale = scaled_rate / st->clk_freq; 389 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 390 if (ret) 391 return ret; 392 393 sample_rate = scaled_rate; 394 } 395 396 t = DIV_ROUND_CLOSEST(sample_rate, t); 397 if (t) 398 t--; 399 400 if (t > st->chip_info->max_dec_rate) 401 t = st->chip_info->max_dec_rate; 402 403 return __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t); 404 } 405 406 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 407 { 408 struct adis16480 *st = iio_priv(indio_dev); 409 uint16_t t; 410 int ret; 411 unsigned int freq, sample_rate = st->clk_freq; 412 413 adis_dev_auto_lock(&st->adis); 414 415 if (st->clk_mode == ADIS16480_CLK_PPS) { 416 u16 sync_scale; 417 418 ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale); 419 if (ret) 420 return ret; 421 422 sample_rate = st->clk_freq * sync_scale; 423 } 424 425 ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t); 426 if (ret) 427 return ret; 428 429 freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1)); 430 431 *val = freq / 1000; 432 *val2 = (freq % 1000) * 1000; 433 434 return IIO_VAL_INT_PLUS_MICRO; 435 } 436 437 enum { 438 ADIS16480_SCAN_GYRO_X, 439 ADIS16480_SCAN_GYRO_Y, 440 ADIS16480_SCAN_GYRO_Z, 441 ADIS16480_SCAN_ACCEL_X, 442 ADIS16480_SCAN_ACCEL_Y, 443 ADIS16480_SCAN_ACCEL_Z, 444 ADIS16480_SCAN_MAGN_X, 445 ADIS16480_SCAN_MAGN_Y, 446 ADIS16480_SCAN_MAGN_Z, 447 ADIS16480_SCAN_BARO, 448 ADIS16480_SCAN_TEMP, 449 ADIS16480_SCAN_DELTANG_X, 450 ADIS16480_SCAN_DELTANG_Y, 451 ADIS16480_SCAN_DELTANG_Z, 452 ADIS16480_SCAN_DELTVEL_X, 453 ADIS16480_SCAN_DELTVEL_Y, 454 ADIS16480_SCAN_DELTVEL_Z, 455 }; 456 457 static const unsigned int adis16480_calibbias_regs[] = { 458 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 459 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 460 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 461 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 462 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 463 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 464 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 465 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 466 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 467 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 468 }; 469 470 static const unsigned int adis16480_calibscale_regs[] = { 471 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 472 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 473 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 474 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 475 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 476 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 477 }; 478 479 static int adis16480_set_calibbias(struct iio_dev *indio_dev, 480 const struct iio_chan_spec *chan, int bias) 481 { 482 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 483 struct adis16480 *st = iio_priv(indio_dev); 484 485 switch (chan->type) { 486 case IIO_MAGN: 487 case IIO_PRESSURE: 488 if (bias < -0x8000 || bias >= 0x8000) 489 return -EINVAL; 490 return adis_write_reg_16(&st->adis, reg, bias); 491 case IIO_ANGL_VEL: 492 case IIO_ACCEL: 493 return adis_write_reg_32(&st->adis, reg, bias); 494 default: 495 break; 496 } 497 498 return -EINVAL; 499 } 500 501 static int adis16480_get_calibbias(struct iio_dev *indio_dev, 502 const struct iio_chan_spec *chan, int *bias) 503 { 504 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 505 struct adis16480 *st = iio_priv(indio_dev); 506 uint16_t val16; 507 uint32_t val32; 508 int ret; 509 510 switch (chan->type) { 511 case IIO_MAGN: 512 case IIO_PRESSURE: 513 ret = adis_read_reg_16(&st->adis, reg, &val16); 514 if (ret == 0) 515 *bias = sign_extend32(val16, 15); 516 break; 517 case IIO_ANGL_VEL: 518 case IIO_ACCEL: 519 ret = adis_read_reg_32(&st->adis, reg, &val32); 520 if (ret == 0) 521 *bias = sign_extend32(val32, 31); 522 break; 523 default: 524 ret = -EINVAL; 525 } 526 527 if (ret) 528 return ret; 529 530 return IIO_VAL_INT; 531 } 532 533 static int adis16480_set_calibscale(struct iio_dev *indio_dev, 534 const struct iio_chan_spec *chan, int scale) 535 { 536 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 537 struct adis16480 *st = iio_priv(indio_dev); 538 539 if (scale < -0x8000 || scale >= 0x8000) 540 return -EINVAL; 541 542 return adis_write_reg_16(&st->adis, reg, scale); 543 } 544 545 static int adis16480_get_calibscale(struct iio_dev *indio_dev, 546 const struct iio_chan_spec *chan, int *scale) 547 { 548 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 549 struct adis16480 *st = iio_priv(indio_dev); 550 uint16_t val16; 551 int ret; 552 553 ret = adis_read_reg_16(&st->adis, reg, &val16); 554 if (ret) 555 return ret; 556 557 *scale = sign_extend32(val16, 15); 558 return IIO_VAL_INT; 559 } 560 561 static const unsigned int adis16480_def_filter_freqs[] = { 562 310, 563 55, 564 275, 565 63, 566 }; 567 568 static const unsigned int adis16495_def_filter_freqs[] = { 569 300, 570 100, 571 300, 572 100, 573 }; 574 575 static const unsigned int ad16480_filter_data[][2] = { 576 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 577 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 578 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 579 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 580 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 581 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 582 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 583 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 584 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 585 }; 586 587 static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 588 const struct iio_chan_spec *chan, int *freq) 589 { 590 struct adis16480 *st = iio_priv(indio_dev); 591 unsigned int enable_mask, offset, reg; 592 uint16_t val; 593 int ret; 594 595 reg = ad16480_filter_data[chan->scan_index][0]; 596 offset = ad16480_filter_data[chan->scan_index][1]; 597 enable_mask = BIT(offset + 2); 598 599 ret = adis_read_reg_16(&st->adis, reg, &val); 600 if (ret) 601 return ret; 602 603 if (!(val & enable_mask)) 604 *freq = 0; 605 else 606 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 607 608 return IIO_VAL_INT; 609 } 610 611 static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 612 const struct iio_chan_spec *chan, unsigned int freq) 613 { 614 struct adis16480 *st = iio_priv(indio_dev); 615 unsigned int enable_mask, offset, reg; 616 unsigned int diff, best_diff; 617 unsigned int i, best_freq; 618 uint16_t val; 619 int ret; 620 621 reg = ad16480_filter_data[chan->scan_index][0]; 622 offset = ad16480_filter_data[chan->scan_index][1]; 623 enable_mask = BIT(offset + 2); 624 625 adis_dev_auto_lock(&st->adis); 626 627 ret = __adis_read_reg_16(&st->adis, reg, &val); 628 if (ret) 629 return ret; 630 631 if (freq == 0) { 632 val &= ~enable_mask; 633 } else { 634 best_freq = 0; 635 best_diff = st->chip_info->filter_freqs[0]; 636 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 637 if (st->chip_info->filter_freqs[i] >= freq) { 638 diff = st->chip_info->filter_freqs[i] - freq; 639 if (diff < best_diff) { 640 best_diff = diff; 641 best_freq = i; 642 } 643 } 644 } 645 646 val &= ~(0x3 << offset); 647 val |= best_freq << offset; 648 val |= enable_mask; 649 } 650 651 return __adis_write_reg_16(&st->adis, reg, val); 652 } 653 654 static int adis16480_read_raw(struct iio_dev *indio_dev, 655 const struct iio_chan_spec *chan, int *val, int *val2, long info) 656 { 657 struct adis16480 *st = iio_priv(indio_dev); 658 unsigned int temp; 659 660 switch (info) { 661 case IIO_CHAN_INFO_RAW: 662 return adis_single_conversion(indio_dev, chan, 0, val); 663 case IIO_CHAN_INFO_SCALE: 664 switch (chan->type) { 665 case IIO_ANGL_VEL: 666 *val = st->chip_info->gyro_max_scale; 667 *val2 = st->chip_info->gyro_max_val; 668 return IIO_VAL_FRACTIONAL; 669 case IIO_ACCEL: 670 *val = st->chip_info->accel_max_scale; 671 *val2 = st->chip_info->accel_max_val; 672 return IIO_VAL_FRACTIONAL; 673 case IIO_MAGN: 674 *val = 0; 675 *val2 = 100; /* 0.0001 gauss */ 676 return IIO_VAL_INT_PLUS_MICRO; 677 case IIO_TEMP: 678 /* 679 * +85 degrees Celsius = temp_max_scale 680 * +25 degrees Celsius = 0 681 * LSB, 25 degrees Celsius = 60 / temp_max_scale 682 */ 683 *val = st->chip_info->temp_scale / 1000; 684 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 685 return IIO_VAL_INT_PLUS_MICRO; 686 case IIO_PRESSURE: 687 /* 688 * max scale is 1310 mbar 689 * max raw value is 32767 shifted for 32bits 690 */ 691 *val = 131; /* 1310mbar = 131 kPa */ 692 *val2 = 32767 << 16; 693 return IIO_VAL_FRACTIONAL; 694 case IIO_DELTA_ANGL: 695 *val = st->chip_info->deltang_max_val; 696 *val2 = 31; 697 return IIO_VAL_FRACTIONAL_LOG2; 698 case IIO_DELTA_VELOCITY: 699 *val = st->chip_info->deltvel_max_val; 700 *val2 = 31; 701 return IIO_VAL_FRACTIONAL_LOG2; 702 default: 703 return -EINVAL; 704 } 705 case IIO_CHAN_INFO_OFFSET: 706 /* Only the temperature channel has a offset */ 707 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 708 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 709 return IIO_VAL_INT; 710 case IIO_CHAN_INFO_CALIBBIAS: 711 return adis16480_get_calibbias(indio_dev, chan, val); 712 case IIO_CHAN_INFO_CALIBSCALE: 713 return adis16480_get_calibscale(indio_dev, chan, val); 714 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 715 return adis16480_get_filter_freq(indio_dev, chan, val); 716 case IIO_CHAN_INFO_SAMP_FREQ: 717 return adis16480_get_freq(indio_dev, val, val2); 718 default: 719 return -EINVAL; 720 } 721 } 722 723 static int adis16480_write_raw(struct iio_dev *indio_dev, 724 const struct iio_chan_spec *chan, int val, int val2, long info) 725 { 726 switch (info) { 727 case IIO_CHAN_INFO_CALIBBIAS: 728 return adis16480_set_calibbias(indio_dev, chan, val); 729 case IIO_CHAN_INFO_CALIBSCALE: 730 return adis16480_set_calibscale(indio_dev, chan, val); 731 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 732 return adis16480_set_filter_freq(indio_dev, chan, val); 733 case IIO_CHAN_INFO_SAMP_FREQ: 734 return adis16480_set_freq(indio_dev, val, val2); 735 736 default: 737 return -EINVAL; 738 } 739 } 740 741 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 742 { \ 743 .type = (_type), \ 744 .modified = 1, \ 745 .channel2 = (_mod), \ 746 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 747 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 748 _info_sep, \ 749 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 750 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 751 .address = (_address), \ 752 .scan_index = (_si), \ 753 .scan_type = { \ 754 .sign = 's', \ 755 .realbits = (_bits), \ 756 .storagebits = (_bits), \ 757 .endianness = IIO_BE, \ 758 }, \ 759 } 760 761 #define ADIS16480_GYRO_CHANNEL(_mod) \ 762 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 763 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 764 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 765 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 766 32) 767 768 #define ADIS16480_ACCEL_CHANNEL(_mod) \ 769 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 770 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 771 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 772 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 773 32) 774 775 #define ADIS16480_DELTANG_CHANNEL(_mod) \ 776 ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 777 ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, ADIS16480_SCAN_DELTANG_ ## _mod, \ 778 0, 32) 779 780 #define ADIS16480_DELTANG_CHANNEL_NO_SCAN(_mod) \ 781 ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 782 ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, -1, 0, 32) 783 784 #define ADIS16480_DELTVEL_CHANNEL(_mod) \ 785 ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 786 ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, ADIS16480_SCAN_DELTVEL_ ## _mod, \ 787 0, 32) 788 789 #define ADIS16480_DELTVEL_CHANNEL_NO_SCAN(_mod) \ 790 ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 791 ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, -1, 0, 32) 792 793 #define ADIS16480_MAGN_CHANNEL(_mod) \ 794 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 795 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 796 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 797 16) 798 799 #define ADIS16480_PRESSURE_CHANNEL() \ 800 { \ 801 .type = IIO_PRESSURE, \ 802 .indexed = 1, \ 803 .channel = 0, \ 804 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 805 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 806 BIT(IIO_CHAN_INFO_SCALE), \ 807 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 808 .address = ADIS16480_REG_BAROM_OUT, \ 809 .scan_index = ADIS16480_SCAN_BARO, \ 810 .scan_type = { \ 811 .sign = 's', \ 812 .realbits = 32, \ 813 .storagebits = 32, \ 814 .endianness = IIO_BE, \ 815 }, \ 816 } 817 818 #define ADIS16480_TEMP_CHANNEL() { \ 819 .type = IIO_TEMP, \ 820 .indexed = 1, \ 821 .channel = 0, \ 822 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 823 BIT(IIO_CHAN_INFO_SCALE) | \ 824 BIT(IIO_CHAN_INFO_OFFSET), \ 825 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 826 .address = ADIS16480_REG_TEMP_OUT, \ 827 .scan_index = ADIS16480_SCAN_TEMP, \ 828 .scan_type = { \ 829 .sign = 's', \ 830 .realbits = 16, \ 831 .storagebits = 16, \ 832 .endianness = IIO_BE, \ 833 }, \ 834 } 835 836 static const struct iio_chan_spec adis16480_channels[] = { 837 ADIS16480_GYRO_CHANNEL(X), 838 ADIS16480_GYRO_CHANNEL(Y), 839 ADIS16480_GYRO_CHANNEL(Z), 840 ADIS16480_ACCEL_CHANNEL(X), 841 ADIS16480_ACCEL_CHANNEL(Y), 842 ADIS16480_ACCEL_CHANNEL(Z), 843 ADIS16480_MAGN_CHANNEL(X), 844 ADIS16480_MAGN_CHANNEL(Y), 845 ADIS16480_MAGN_CHANNEL(Z), 846 ADIS16480_PRESSURE_CHANNEL(), 847 ADIS16480_TEMP_CHANNEL(), 848 IIO_CHAN_SOFT_TIMESTAMP(11), 849 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X), 850 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y), 851 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z), 852 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X), 853 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y), 854 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z), 855 }; 856 857 static const struct iio_chan_spec adis16485_channels[] = { 858 ADIS16480_GYRO_CHANNEL(X), 859 ADIS16480_GYRO_CHANNEL(Y), 860 ADIS16480_GYRO_CHANNEL(Z), 861 ADIS16480_ACCEL_CHANNEL(X), 862 ADIS16480_ACCEL_CHANNEL(Y), 863 ADIS16480_ACCEL_CHANNEL(Z), 864 ADIS16480_TEMP_CHANNEL(), 865 IIO_CHAN_SOFT_TIMESTAMP(7), 866 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X), 867 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y), 868 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z), 869 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X), 870 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y), 871 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z), 872 }; 873 874 static const struct iio_chan_spec adis16545_channels[] = { 875 ADIS16480_GYRO_CHANNEL(X), 876 ADIS16480_GYRO_CHANNEL(Y), 877 ADIS16480_GYRO_CHANNEL(Z), 878 ADIS16480_ACCEL_CHANNEL(X), 879 ADIS16480_ACCEL_CHANNEL(Y), 880 ADIS16480_ACCEL_CHANNEL(Z), 881 ADIS16480_TEMP_CHANNEL(), 882 ADIS16480_DELTANG_CHANNEL(X), 883 ADIS16480_DELTANG_CHANNEL(Y), 884 ADIS16480_DELTANG_CHANNEL(Z), 885 ADIS16480_DELTVEL_CHANNEL(X), 886 ADIS16480_DELTVEL_CHANNEL(Y), 887 ADIS16480_DELTVEL_CHANNEL(Z), 888 IIO_CHAN_SOFT_TIMESTAMP(17), 889 }; 890 891 enum adis16480_variant { 892 ADIS16375, 893 ADIS16480, 894 ADIS16485, 895 ADIS16488, 896 ADIS16490, 897 ADIS16495_1, 898 ADIS16495_2, 899 ADIS16495_3, 900 ADIS16497_1, 901 ADIS16497_2, 902 ADIS16497_3, 903 ADIS16545_1, 904 ADIS16545_2, 905 ADIS16545_3, 906 ADIS16547_1, 907 ADIS16547_2, 908 ADIS16547_3 909 }; 910 911 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 912 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 913 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 914 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3 915 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4 916 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 917 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 918 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 919 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 920 #define ADIS16480_DIAG_STAT_BARO_FAIL 11 921 922 static const char * const adis16480_status_error_msgs[] = { 923 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 924 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 925 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 926 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 927 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 928 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 929 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 930 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 931 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 932 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 933 }; 934 935 static int adis16480_enable_irq(struct adis *adis, bool enable); 936 937 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len, _burst_max_speed) \ 938 { \ 939 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \ 940 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \ 941 .prod_id_reg = ADIS16480_REG_PROD_ID, \ 942 .prod_id = (_prod_id), \ 943 .has_paging = true, \ 944 .read_delay = 5, \ 945 .write_delay = 5, \ 946 .self_test_mask = BIT(1), \ 947 .self_test_reg = ADIS16480_REG_GLOB_CMD, \ 948 .status_error_msgs = adis16480_status_error_msgs, \ 949 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \ 950 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \ 951 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \ 952 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \ 953 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \ 954 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \ 955 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \ 956 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \ 957 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \ 958 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \ 959 .enable_irq = adis16480_enable_irq, \ 960 .timeouts = (_timeouts), \ 961 .burst_reg_cmd = ADIS16495_REG_BURST_CMD, \ 962 .burst_len = (_burst_len), \ 963 .burst_max_speed_hz = _burst_max_speed \ 964 } 965 966 static const struct adis_timeout adis16485_timeouts = { 967 .reset_ms = 560, 968 .sw_reset_ms = 120, 969 .self_test_ms = 12, 970 }; 971 972 static const struct adis_timeout adis16480_timeouts = { 973 .reset_ms = 560, 974 .sw_reset_ms = 560, 975 .self_test_ms = 12, 976 }; 977 978 static const struct adis_timeout adis16495_timeouts = { 979 .reset_ms = 170, 980 .sw_reset_ms = 130, 981 .self_test_ms = 40, 982 }; 983 984 static const struct adis_timeout adis16495_1_timeouts = { 985 .reset_ms = 250, 986 .sw_reset_ms = 210, 987 .self_test_ms = 20, 988 }; 989 990 static const struct adis_timeout adis16545_timeouts = { 991 .reset_ms = 315, 992 .sw_reset_ms = 270, 993 .self_test_ms = 35, 994 }; 995 996 static const struct adis16480_chip_info adis16480_chip_info[] = { 997 [ADIS16375] = { 998 .channels = adis16485_channels, 999 .num_channels = ARRAY_SIZE(adis16485_channels), 1000 /* 1001 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 1002 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 1003 * it gives better approximation. However, in this case we 1004 * cannot do it since it would not fit in a 32bit variable. 1005 */ 1006 .gyro_max_val = 22887 << 16, 1007 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 1008 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 1009 .accel_max_scale = 18, 1010 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 1011 .deltang_max_val = IIO_DEGREE_TO_RAD(180), 1012 .deltvel_max_val = 100, 1013 .int_clk = 2460000, 1014 .max_dec_rate = 2048, 1015 .has_sleep_cnt = true, 1016 .filter_freqs = adis16480_def_filter_freqs, 1017 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0, 0), 1018 }, 1019 [ADIS16480] = { 1020 .channels = adis16480_channels, 1021 .num_channels = ARRAY_SIZE(adis16480_channels), 1022 .gyro_max_val = 22500 << 16, 1023 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1024 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 1025 .accel_max_scale = 10, 1026 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 1027 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1028 .deltvel_max_val = 200, 1029 .int_clk = 2460000, 1030 .max_dec_rate = 2048, 1031 .has_sleep_cnt = true, 1032 .filter_freqs = adis16480_def_filter_freqs, 1033 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0, 0), 1034 }, 1035 [ADIS16485] = { 1036 .channels = adis16485_channels, 1037 .num_channels = ARRAY_SIZE(adis16485_channels), 1038 .gyro_max_val = 22500 << 16, 1039 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1040 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 1041 .accel_max_scale = 5, 1042 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 1043 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1044 .deltvel_max_val = 50, 1045 .int_clk = 2460000, 1046 .max_dec_rate = 2048, 1047 .has_sleep_cnt = true, 1048 .filter_freqs = adis16480_def_filter_freqs, 1049 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0, 0), 1050 }, 1051 [ADIS16488] = { 1052 .channels = adis16480_channels, 1053 .num_channels = ARRAY_SIZE(adis16480_channels), 1054 .gyro_max_val = 22500 << 16, 1055 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1056 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 1057 .accel_max_scale = 18, 1058 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 1059 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1060 .deltvel_max_val = 200, 1061 .int_clk = 2460000, 1062 .max_dec_rate = 2048, 1063 .has_sleep_cnt = true, 1064 .filter_freqs = adis16480_def_filter_freqs, 1065 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0, 0), 1066 }, 1067 [ADIS16490] = { 1068 .channels = adis16485_channels, 1069 .num_channels = ARRAY_SIZE(adis16485_channels), 1070 .gyro_max_val = 20000 << 16, 1071 .gyro_max_scale = IIO_DEGREE_TO_RAD(100), 1072 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16), 1073 .accel_max_scale = 8, 1074 .temp_scale = 14285, /* 14.285 milli degree Celsius */ 1075 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1076 .deltvel_max_val = 200, 1077 .int_clk = 4250000, 1078 .max_dec_rate = 4250, 1079 .filter_freqs = adis16495_def_filter_freqs, 1080 .has_pps_clk_mode = true, 1081 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0, 0), 1082 }, 1083 [ADIS16495_1] = { 1084 .channels = adis16485_channels, 1085 .num_channels = ARRAY_SIZE(adis16485_channels), 1086 .gyro_max_val = 20000 << 16, 1087 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1088 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1089 .accel_max_scale = 8, 1090 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1091 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1092 .deltvel_max_val = 100, 1093 .int_clk = 4250000, 1094 .max_dec_rate = 4250, 1095 .filter_freqs = adis16495_def_filter_freqs, 1096 .has_pps_clk_mode = true, 1097 /* 20 elements of 16bits */ 1098 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1099 ADIS16495_BURST_MAX_DATA * 2, 1100 6000000), 1101 }, 1102 [ADIS16495_2] = { 1103 .channels = adis16485_channels, 1104 .num_channels = ARRAY_SIZE(adis16485_channels), 1105 .gyro_max_val = 18000 << 16, 1106 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1107 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1108 .accel_max_scale = 8, 1109 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1110 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1111 .deltvel_max_val = 100, 1112 .int_clk = 4250000, 1113 .max_dec_rate = 4250, 1114 .filter_freqs = adis16495_def_filter_freqs, 1115 .has_pps_clk_mode = true, 1116 /* 20 elements of 16bits */ 1117 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1118 ADIS16495_BURST_MAX_DATA * 2, 1119 6000000), 1120 }, 1121 [ADIS16495_3] = { 1122 .channels = adis16485_channels, 1123 .num_channels = ARRAY_SIZE(adis16485_channels), 1124 .gyro_max_val = 20000 << 16, 1125 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1126 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1127 .accel_max_scale = 8, 1128 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1129 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1130 .deltvel_max_val = 100, 1131 .int_clk = 4250000, 1132 .max_dec_rate = 4250, 1133 .filter_freqs = adis16495_def_filter_freqs, 1134 .has_pps_clk_mode = true, 1135 /* 20 elements of 16bits */ 1136 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts, 1137 ADIS16495_BURST_MAX_DATA * 2, 1138 6000000), 1139 }, 1140 [ADIS16497_1] = { 1141 .channels = adis16485_channels, 1142 .num_channels = ARRAY_SIZE(adis16485_channels), 1143 .gyro_max_val = 20000 << 16, 1144 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1145 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1146 .accel_max_scale = 40, 1147 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1148 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1149 .deltvel_max_val = 400, 1150 .int_clk = 4250000, 1151 .max_dec_rate = 4250, 1152 .filter_freqs = adis16495_def_filter_freqs, 1153 .has_pps_clk_mode = true, 1154 /* 20 elements of 16bits */ 1155 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1156 ADIS16495_BURST_MAX_DATA * 2, 1157 6000000), 1158 }, 1159 [ADIS16497_2] = { 1160 .channels = adis16485_channels, 1161 .num_channels = ARRAY_SIZE(adis16485_channels), 1162 .gyro_max_val = 18000 << 16, 1163 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1164 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1165 .accel_max_scale = 40, 1166 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1167 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1168 .deltvel_max_val = 400, 1169 .int_clk = 4250000, 1170 .max_dec_rate = 4250, 1171 .filter_freqs = adis16495_def_filter_freqs, 1172 .has_pps_clk_mode = true, 1173 /* 20 elements of 16bits */ 1174 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1175 ADIS16495_BURST_MAX_DATA * 2, 1176 6000000), 1177 }, 1178 [ADIS16497_3] = { 1179 .channels = adis16485_channels, 1180 .num_channels = ARRAY_SIZE(adis16485_channels), 1181 .gyro_max_val = 20000 << 16, 1182 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1183 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1184 .accel_max_scale = 40, 1185 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1186 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1187 .deltvel_max_val = 400, 1188 .int_clk = 4250000, 1189 .max_dec_rate = 4250, 1190 .filter_freqs = adis16495_def_filter_freqs, 1191 .has_pps_clk_mode = true, 1192 /* 20 elements of 16bits */ 1193 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts, 1194 ADIS16495_BURST_MAX_DATA * 2, 1195 6000000), 1196 }, 1197 [ADIS16545_1] = { 1198 .channels = adis16545_channels, 1199 .num_channels = ARRAY_SIZE(adis16545_channels), 1200 .gyro_max_val = 20000 << 16, 1201 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1202 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1203 .accel_max_scale = 8, 1204 .temp_scale = 7000, /* 7 milli degree Celsius */ 1205 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1206 .deltvel_max_val = 100, 1207 .int_clk = 4250000, 1208 .max_dec_rate = 4250, 1209 .filter_freqs = adis16495_def_filter_freqs, 1210 .has_pps_clk_mode = true, 1211 .has_burst_delta_data = true, 1212 /* 20 elements of 16bits */ 1213 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts, 1214 ADIS16495_BURST_MAX_DATA * 2, 1215 6500000), 1216 }, 1217 [ADIS16545_2] = { 1218 .channels = adis16545_channels, 1219 .num_channels = ARRAY_SIZE(adis16545_channels), 1220 .gyro_max_val = 18000 << 16, 1221 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1222 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1223 .accel_max_scale = 8, 1224 .temp_scale = 7000, /* 7 milli degree Celsius */ 1225 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1226 .deltvel_max_val = 100, 1227 .int_clk = 4250000, 1228 .max_dec_rate = 4250, 1229 .filter_freqs = adis16495_def_filter_freqs, 1230 .has_pps_clk_mode = true, 1231 .has_burst_delta_data = true, 1232 /* 20 elements of 16bits */ 1233 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts, 1234 ADIS16495_BURST_MAX_DATA * 2, 1235 6500000), 1236 }, 1237 [ADIS16545_3] = { 1238 .channels = adis16545_channels, 1239 .num_channels = ARRAY_SIZE(adis16545_channels), 1240 .gyro_max_val = 20000 << 16, 1241 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1242 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1243 .accel_max_scale = 8, 1244 .temp_scale = 7000, /* 7 milli degree Celsius */ 1245 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1246 .deltvel_max_val = 100, 1247 .int_clk = 4250000, 1248 .max_dec_rate = 4250, 1249 .filter_freqs = adis16495_def_filter_freqs, 1250 .has_pps_clk_mode = true, 1251 .has_burst_delta_data = true, 1252 /* 20 elements of 16bits */ 1253 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts, 1254 ADIS16495_BURST_MAX_DATA * 2, 1255 6500000), 1256 }, 1257 [ADIS16547_1] = { 1258 .channels = adis16545_channels, 1259 .num_channels = ARRAY_SIZE(adis16545_channels), 1260 .gyro_max_val = 20000 << 16, 1261 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 1262 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1263 .accel_max_scale = 40, 1264 .temp_scale = 7000, /* 7 milli degree Celsius */ 1265 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1266 .deltvel_max_val = 400, 1267 .int_clk = 4250000, 1268 .max_dec_rate = 4250, 1269 .filter_freqs = adis16495_def_filter_freqs, 1270 .has_pps_clk_mode = true, 1271 .has_burst_delta_data = true, 1272 /* 20 elements of 16bits */ 1273 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts, 1274 ADIS16495_BURST_MAX_DATA * 2, 1275 6500000), 1276 }, 1277 [ADIS16547_2] = { 1278 .channels = adis16545_channels, 1279 .num_channels = ARRAY_SIZE(adis16545_channels), 1280 .gyro_max_val = 18000 << 16, 1281 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1282 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1283 .accel_max_scale = 40, 1284 .temp_scale = 7000, /* 7 milli degree Celsius */ 1285 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1286 .deltvel_max_val = 400, 1287 .int_clk = 4250000, 1288 .max_dec_rate = 4250, 1289 .filter_freqs = adis16495_def_filter_freqs, 1290 .has_pps_clk_mode = true, 1291 .has_burst_delta_data = true, 1292 /* 20 elements of 16bits */ 1293 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts, 1294 ADIS16495_BURST_MAX_DATA * 2, 1295 6500000), 1296 }, 1297 [ADIS16547_3] = { 1298 .channels = adis16545_channels, 1299 .num_channels = ARRAY_SIZE(adis16545_channels), 1300 .gyro_max_val = 20000 << 16, 1301 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1302 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1303 .accel_max_scale = 40, 1304 .temp_scale = 7000, /* 7 milli degree Celsius */ 1305 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1306 .deltvel_max_val = 400, 1307 .int_clk = 4250000, 1308 .max_dec_rate = 4250, 1309 .filter_freqs = adis16495_def_filter_freqs, 1310 .has_pps_clk_mode = true, 1311 .has_burst_delta_data = true, 1312 /* 20 elements of 16bits */ 1313 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts, 1314 ADIS16495_BURST_MAX_DATA * 2, 1315 6500000), 1316 }, 1317 }; 1318 1319 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc) 1320 { 1321 u32 crc_calc; 1322 u16 crc_buf[15]; 1323 int j; 1324 1325 for (j = 0; j < n_elem; j++) 1326 crc_buf[j] = swab16(buf[j]); 1327 1328 crc_calc = crc32(~0, crc_buf, n_elem * 2); 1329 crc_calc ^= ~0; 1330 1331 return (crc == crc_calc); 1332 } 1333 1334 static irqreturn_t adis16480_trigger_handler(int irq, void *p) 1335 { 1336 struct iio_poll_func *pf = p; 1337 struct iio_dev *indio_dev = pf->indio_dev; 1338 struct adis16480 *st = iio_priv(indio_dev); 1339 struct adis *adis = &st->adis; 1340 struct device *dev = &adis->spi->dev; 1341 int ret, bit, offset, i = 0, buff_offset = 0; 1342 __be16 *buffer; 1343 u32 crc; 1344 bool valid; 1345 1346 adis_dev_auto_scoped_lock(adis) { 1347 if (adis->current_page != 0) { 1348 adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID); 1349 adis->tx[1] = 0; 1350 ret = spi_write(adis->spi, adis->tx, 2); 1351 if (ret) { 1352 dev_err(dev, "Failed to change device page: %d\n", ret); 1353 goto irq_done; 1354 } 1355 1356 adis->current_page = 0; 1357 } 1358 1359 ret = spi_sync(adis->spi, &adis->msg); 1360 if (ret) { 1361 dev_err(dev, "Failed to read data: %d\n", ret); 1362 goto irq_done; 1363 } 1364 } 1365 1366 /* 1367 * After making the burst request, the response can have one or two 1368 * 16-bit responses containing the BURST_ID depending on the sclk. If 1369 * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ, 1370 * we have only one. To manage that variation, we use the transition from the 1371 * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5/0xC3C3. 1372 * If we not find this variation in the first 4 segments, then the data should 1373 * not be valid. 1374 */ 1375 buffer = adis->buffer; 1376 for (offset = 0; offset < 4; offset++) { 1377 u16 curr = be16_to_cpu(buffer[offset]); 1378 u16 next = be16_to_cpu(buffer[offset + 1]); 1379 1380 if (curr == st->burst_id && next != st->burst_id) { 1381 offset++; 1382 break; 1383 } 1384 } 1385 1386 if (offset == 4) { 1387 dev_err(dev, "Invalid burst data\n"); 1388 goto irq_done; 1389 } 1390 1391 crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]); 1392 valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc); 1393 if (!valid) { 1394 dev_err(dev, "Invalid crc\n"); 1395 goto irq_done; 1396 } 1397 1398 for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { 1399 /* 1400 * When burst mode is used, temperature is the first data 1401 * channel in the sequence, but the temperature scan index 1402 * is 10. 1403 */ 1404 switch (bit) { 1405 case ADIS16480_SCAN_TEMP: 1406 st->data[i++] = buffer[offset + 1]; 1407 /* 1408 * The temperature channel has 16-bit storage size. 1409 * We need to perform the padding to have the buffer 1410 * elements naturally aligned in case there are any 1411 * 32-bit storage size channels enabled which are added 1412 * in the buffer after the temprature data. In case 1413 * there is no data being added after the temperature 1414 * data, the padding is harmless. 1415 */ 1416 st->data[i++] = 0; 1417 break; 1418 case ADIS16480_SCAN_DELTANG_X ... ADIS16480_SCAN_DELTVEL_Z: 1419 buff_offset = ADIS16480_SCAN_DELTANG_X; 1420 fallthrough; 1421 case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z: 1422 /* The lower register data is sequenced first */ 1423 st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 3]; 1424 st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 2]; 1425 break; 1426 } 1427 } 1428 1429 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1430 irq_done: 1431 iio_trigger_notify_done(indio_dev->trig); 1432 1433 return IRQ_HANDLED; 1434 } 1435 1436 static const unsigned long adis16545_channel_masks[] = { 1437 ADIS16545_BURST_DATA_SEL_0_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17), 1438 ADIS16545_BURST_DATA_SEL_1_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17), 1439 0, 1440 }; 1441 1442 static int adis16480_update_scan_mode(struct iio_dev *indio_dev, 1443 const unsigned long *scan_mask) 1444 { 1445 u16 en; 1446 int ret; 1447 struct adis16480 *st = iio_priv(indio_dev); 1448 1449 if (st->chip_info->has_burst_delta_data) { 1450 if (*scan_mask & ADIS16545_BURST_DATA_SEL_0_CHN_MASK) { 1451 en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 0); 1452 st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID; 1453 } else { 1454 en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 1); 1455 st->burst_id = ADIS16545_DELTA_ANG_VEL_BURST_ID; 1456 } 1457 1458 ret = __adis_update_bits(&st->adis, ADIS16480_REG_CONFIG, 1459 ADIS16545_BURST_DATA_SEL_MASK, en); 1460 if (ret) 1461 return ret; 1462 } 1463 1464 return adis_update_scan_mode(indio_dev, scan_mask); 1465 } 1466 1467 static const struct iio_info adis16480_info = { 1468 .read_raw = &adis16480_read_raw, 1469 .write_raw = &adis16480_write_raw, 1470 .update_scan_mode = &adis16480_update_scan_mode, 1471 .debugfs_reg_access = adis_debugfs_reg_access, 1472 }; 1473 1474 static int adis16480_stop_device(struct iio_dev *indio_dev) 1475 { 1476 struct adis16480 *st = iio_priv(indio_dev); 1477 struct device *dev = &st->adis.spi->dev; 1478 int ret; 1479 1480 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 1481 if (ret) 1482 dev_err(dev, "Could not power down device: %d\n", ret); 1483 1484 return ret; 1485 } 1486 1487 static int adis16480_enable_irq(struct adis *adis, bool enable) 1488 { 1489 uint16_t val; 1490 int ret; 1491 1492 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1493 if (ret) 1494 return ret; 1495 1496 val &= ~ADIS16480_DRDY_EN_MSK; 1497 val |= ADIS16480_DRDY_EN(enable); 1498 1499 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 1500 } 1501 1502 static int adis16480_config_irq_pin(struct adis16480 *st) 1503 { 1504 struct device *dev = &st->adis.spi->dev; 1505 struct fwnode_handle *fwnode = dev_fwnode(dev); 1506 enum adis16480_int_pin pin; 1507 unsigned int irq_type; 1508 uint16_t val; 1509 int i, irq = 0; 1510 1511 /* Disable data ready since the default after reset is on */ 1512 val = ADIS16480_DRDY_EN(0); 1513 1514 /* 1515 * Get the interrupt from the devicetre by reading the interrupt-names 1516 * property. If it is not specified, use DIO1 pin as default. 1517 * According to the datasheet, the factory default assigns DIO2 as data 1518 * ready signal. However, in the previous versions of the driver, DIO1 1519 * pin was used. So, we should leave it as is since some devices might 1520 * be expecting the interrupt on the wrong physical pin. 1521 */ 1522 pin = ADIS16480_PIN_DIO1; 1523 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1524 irq = fwnode_irq_get_byname(fwnode, adis16480_int_pin_names[i]); 1525 if (irq > 0) { 1526 pin = i; 1527 break; 1528 } 1529 } 1530 1531 val |= ADIS16480_DRDY_SEL(pin); 1532 1533 /* 1534 * Get the interrupt line behaviour. The data ready polarity can be 1535 * configured as positive or negative, corresponding to 1536 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively. 1537 */ 1538 irq_type = irq_get_trigger_type(st->adis.spi->irq); 1539 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */ 1540 val |= ADIS16480_DRDY_POL(1); 1541 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1542 val |= ADIS16480_DRDY_POL(0); 1543 } else { 1544 dev_err(dev, "Invalid interrupt type 0x%x specified\n", irq_type); 1545 return -EINVAL; 1546 } 1547 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1548 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1549 } 1550 1551 static int adis16480_fw_get_ext_clk_pin(struct adis16480 *st) 1552 { 1553 struct device *dev = &st->adis.spi->dev; 1554 const char *ext_clk_pin; 1555 enum adis16480_int_pin pin; 1556 int i; 1557 1558 pin = ADIS16480_PIN_DIO2; 1559 if (device_property_read_string(dev, "adi,ext-clk-pin", &ext_clk_pin)) 1560 goto clk_input_not_found; 1561 1562 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1563 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1564 return i; 1565 } 1566 1567 clk_input_not_found: 1568 dev_info(dev, "clk input line not specified, using DIO2\n"); 1569 return pin; 1570 } 1571 1572 static int adis16480_ext_clk_config(struct adis16480 *st, bool enable) 1573 { 1574 struct device *dev = &st->adis.spi->dev; 1575 unsigned int mode, mask; 1576 enum adis16480_int_pin pin; 1577 uint16_t val; 1578 int ret; 1579 1580 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1581 if (ret) 1582 return ret; 1583 1584 pin = adis16480_fw_get_ext_clk_pin(st); 1585 /* 1586 * Each DIOx pin supports only one function at a time. When a single pin 1587 * has two assignments, the enable bit for a lower priority function 1588 * automatically resets to zero (disabling the lower priority function). 1589 */ 1590 if (pin == ADIS16480_DRDY_SEL(val)) 1591 dev_warn(dev, "DIO%x pin supports only one function at a time\n", pin + 1); 1592 1593 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1594 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1595 /* Only ADIS1649x devices support pps ext clock mode */ 1596 if (st->chip_info->has_pps_clk_mode) { 1597 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1598 mask |= ADIS16480_SYNC_MODE_MSK; 1599 } 1600 1601 val &= ~mask; 1602 val |= mode; 1603 1604 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1605 if (ret) 1606 return ret; 1607 1608 return clk_prepare_enable(st->ext_clk); 1609 } 1610 1611 static int adis16480_get_ext_clocks(struct adis16480 *st) 1612 { 1613 struct device *dev = &st->adis.spi->dev; 1614 1615 st->ext_clk = devm_clk_get_optional(dev, "sync"); 1616 if (IS_ERR(st->ext_clk)) 1617 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n"); 1618 if (st->ext_clk) { 1619 st->clk_mode = ADIS16480_CLK_SYNC; 1620 return 0; 1621 } 1622 1623 if (st->chip_info->has_pps_clk_mode) { 1624 st->ext_clk = devm_clk_get_optional(dev, "pps"); 1625 if (IS_ERR(st->ext_clk)) 1626 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n"); 1627 if (st->ext_clk) { 1628 st->clk_mode = ADIS16480_CLK_PPS; 1629 return 0; 1630 } 1631 } 1632 1633 st->clk_mode = ADIS16480_CLK_INT; 1634 return 0; 1635 } 1636 1637 static void adis16480_stop(void *data) 1638 { 1639 adis16480_stop_device(data); 1640 } 1641 1642 static void adis16480_clk_disable(void *data) 1643 { 1644 clk_disable_unprepare(data); 1645 } 1646 1647 static int adis16480_probe(struct spi_device *spi) 1648 { 1649 const struct spi_device_id *id = spi_get_device_id(spi); 1650 const struct adis_data *adis16480_data; 1651 irq_handler_t trigger_handler = NULL; 1652 struct device *dev = &spi->dev; 1653 struct iio_dev *indio_dev; 1654 struct adis16480 *st; 1655 int ret; 1656 1657 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1658 if (indio_dev == NULL) 1659 return -ENOMEM; 1660 1661 st = iio_priv(indio_dev); 1662 1663 st->chip_info = &adis16480_chip_info[id->driver_data]; 1664 indio_dev->name = spi_get_device_id(spi)->name; 1665 indio_dev->channels = st->chip_info->channels; 1666 indio_dev->num_channels = st->chip_info->num_channels; 1667 if (st->chip_info->has_burst_delta_data) 1668 indio_dev->available_scan_masks = adis16545_channel_masks; 1669 indio_dev->info = &adis16480_info; 1670 indio_dev->modes = INDIO_DIRECT_MODE; 1671 1672 adis16480_data = &st->chip_info->adis_data; 1673 1674 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data); 1675 if (ret) 1676 return ret; 1677 1678 ret = __adis_initial_startup(&st->adis); 1679 if (ret) 1680 return ret; 1681 1682 /* 1683 * By default, use burst id for gyroscope and accelerometer data. 1684 * This is the only option for devices which do not offer delta angle 1685 * and delta velocity burst readings. 1686 */ 1687 st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID; 1688 1689 if (st->chip_info->has_sleep_cnt) { 1690 ret = devm_add_action_or_reset(dev, adis16480_stop, indio_dev); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 ret = adis16480_config_irq_pin(st); 1696 if (ret) 1697 return ret; 1698 1699 ret = adis16480_get_ext_clocks(st); 1700 if (ret) 1701 return ret; 1702 1703 if (st->ext_clk) { 1704 ret = adis16480_ext_clk_config(st, true); 1705 if (ret) 1706 return ret; 1707 1708 ret = devm_add_action_or_reset(dev, adis16480_clk_disable, st->ext_clk); 1709 if (ret) 1710 return ret; 1711 1712 st->clk_freq = clk_get_rate(st->ext_clk); 1713 st->clk_freq *= 1000; /* micro */ 1714 if (st->clk_mode == ADIS16480_CLK_PPS) { 1715 u16 sync_scale; 1716 1717 /* 1718 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence, 1719 * default the IMU sample rate to the highest multiple of the input clock 1720 * lower than the IMU max sample rate. The internal sample rate is the 1721 * max... 1722 */ 1723 sync_scale = st->chip_info->int_clk / st->clk_freq; 1724 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale); 1725 if (ret) 1726 return ret; 1727 } 1728 } else { 1729 st->clk_freq = st->chip_info->int_clk; 1730 } 1731 1732 /* Only use our trigger handler if burst mode is supported */ 1733 if (adis16480_data->burst_len) 1734 trigger_handler = adis16480_trigger_handler; 1735 1736 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1737 trigger_handler); 1738 if (ret) 1739 return ret; 1740 1741 ret = devm_iio_device_register(dev, indio_dev); 1742 if (ret) 1743 return ret; 1744 1745 adis16480_debugfs_init(indio_dev); 1746 1747 return 0; 1748 } 1749 1750 static const struct spi_device_id adis16480_ids[] = { 1751 { "adis16375", ADIS16375 }, 1752 { "adis16480", ADIS16480 }, 1753 { "adis16485", ADIS16485 }, 1754 { "adis16488", ADIS16488 }, 1755 { "adis16490", ADIS16490 }, 1756 { "adis16495-1", ADIS16495_1 }, 1757 { "adis16495-2", ADIS16495_2 }, 1758 { "adis16495-3", ADIS16495_3 }, 1759 { "adis16497-1", ADIS16497_1 }, 1760 { "adis16497-2", ADIS16497_2 }, 1761 { "adis16497-3", ADIS16497_3 }, 1762 { "adis16545-1", ADIS16545_1 }, 1763 { "adis16545-2", ADIS16545_2 }, 1764 { "adis16545-3", ADIS16545_3 }, 1765 { "adis16547-1", ADIS16547_1 }, 1766 { "adis16547-2", ADIS16547_2 }, 1767 { "adis16547-3", ADIS16547_3 }, 1768 { } 1769 }; 1770 MODULE_DEVICE_TABLE(spi, adis16480_ids); 1771 1772 static const struct of_device_id adis16480_of_match[] = { 1773 { .compatible = "adi,adis16375" }, 1774 { .compatible = "adi,adis16480" }, 1775 { .compatible = "adi,adis16485" }, 1776 { .compatible = "adi,adis16488" }, 1777 { .compatible = "adi,adis16490" }, 1778 { .compatible = "adi,adis16495-1" }, 1779 { .compatible = "adi,adis16495-2" }, 1780 { .compatible = "adi,adis16495-3" }, 1781 { .compatible = "adi,adis16497-1" }, 1782 { .compatible = "adi,adis16497-2" }, 1783 { .compatible = "adi,adis16497-3" }, 1784 { .compatible = "adi,adis16545-1" }, 1785 { .compatible = "adi,adis16545-2" }, 1786 { .compatible = "adi,adis16545-3" }, 1787 { .compatible = "adi,adis16547-1" }, 1788 { .compatible = "adi,adis16547-2" }, 1789 { .compatible = "adi,adis16547-3" }, 1790 { }, 1791 }; 1792 MODULE_DEVICE_TABLE(of, adis16480_of_match); 1793 1794 static struct spi_driver adis16480_driver = { 1795 .driver = { 1796 .name = "adis16480", 1797 .of_match_table = adis16480_of_match, 1798 }, 1799 .id_table = adis16480_ids, 1800 .probe = adis16480_probe, 1801 }; 1802 module_spi_driver(adis16480_driver); 1803 1804 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1805 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1806 MODULE_LICENSE("GPL v2"); 1807 MODULE_IMPORT_NS(IIO_ADISLIB); 1808